JPH05315534A - Ic package - Google Patents

Ic package

Info

Publication number
JPH05315534A
JPH05315534A JP4118884A JP11888492A JPH05315534A JP H05315534 A JPH05315534 A JP H05315534A JP 4118884 A JP4118884 A JP 4118884A JP 11888492 A JP11888492 A JP 11888492A JP H05315534 A JPH05315534 A JP H05315534A
Authority
JP
Japan
Prior art keywords
external lead
contact
outer leads
external
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4118884A
Other languages
Japanese (ja)
Inventor
Hiroshi Yamanouchi
博 山之内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4118884A priority Critical patent/JPH05315534A/en
Publication of JPH05315534A publication Critical patent/JPH05315534A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the clearance between contact regions and outer leads down to exceeding 100mum compared with the conventional clearance by covering the periphery of the contact regions wherein measuring pins come into contact with the outer leads. CONSTITUTION:An insulating film 9 of polyimide, etc., 25mum-100mum thick with aperture parts previously zigzag formed on the positions corresponding to set up pins 10 is applied to one main surface of outer leads 7. This insulating film 9 is to be apllied before a semiconductor pellet is assembled into or after an outer vessel 6 is formed. The size of the aperture parts 8 is specified not to come into contact with adjacent outer leads 7. In such a structure of the outer leads 7, the periphery of the contact regions in contact with the measuring pins 10 is covered with the insulating film 9 so that the possibility of electrical shortcircuit between the measuring pins 10 and the outer leads 7 may be precluded thereby enabling the clearance between the contact regions and the adjacent outer leads 7 to be reduced down to several scores of mum.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置用外部容器
(ICパッケージ)の外部リード構造体に関し、特に表
面実装型のICパッケージの外部リード構造体に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an external lead structure for an external container (IC package) for a semiconductor device, and more particularly to an external lead structure for a surface mount type IC package.

【0002】[0002]

【従来の技術】まず、図2(A)及び(B)を参照し
て、従来のICパッケージについて説明する。ICパッ
ケージは、半導体ペレット1を搭載するマウント領域3
を備えており、さらに、半導体ペレットの外部引き出し
電極2とAu,Al等の金属細線(ボンディング線)4
で接続される金属導体のボンディング領域5と、そのボ
ンディング領域5の長手方向に延在し、かつ半導体ペレ
ット1とボンディング線4とボンディング領域5とを密
封する外部容器6と、外部容器6から直線上に突出した
金属導体の外部リード7とを備えている。
2. Description of the Related Art First, a conventional IC package will be described with reference to FIGS. The IC package has a mount area 3 on which the semiconductor pellet 1 is mounted.
And an external lead electrode 2 for the semiconductor pellet and a fine metal wire (bonding wire) 4 such as Au or Al.
A bonding area 5 of a metal conductor connected to each other, an external container 6 extending in the longitudinal direction of the bonding area 5 and sealing the semiconductor pellet 1, the bonding wire 4 and the bonding area 5, and a straight line from the external container 6. And an external lead 7 of a metal conductor protruding upward.

【0003】上述のようなICパッケージを用いて、半
導体ペレットが組み込まれた半導体装置の動作試験(電
気テスト)を行う際には、図2(B)に示すように、外
部リード7に測定用治具(図示せず)の測定ピン10を
接触して、動作試験を行う。この際、測定ピンは接触領
域(コンタクト領域)で外部リードと接触される。
When performing an operation test (electrical test) of a semiconductor device in which a semiconductor pellet is incorporated using the above IC package, as shown in FIG. An operation test is performed by contacting the measuring pin 10 of a jig (not shown). At this time, the measuring pin is brought into contact with the external lead in the contact area (contact area).

【0004】ところで、測定ピンと外部リードとの接触
領域(コンタクト領域)の大きさは、(1)測定用治具
の測定ピンの位置精度、及び(2)外部リードと測定ピ
ンとの位置決め精度の2点から決定される。そして、従
来、望ましいとされるコンタクト領域の大きさは幅が
0.25mm〜0.30mm、コンタクト領域と隣接の
外部リードとの間隔(クリアランス)が0.15mm〜
0.20mmである。
By the way, the size of the contact area (contact area) between the measuring pin and the external lead is (1) the positional accuracy of the measuring pin of the measuring jig, and (2) the positioning accuracy of the external lead and the measuring pin. Determined from the points. Conventionally, it is desirable that the contact region has a width of 0.25 mm to 0.30 mm, and a space (clearance) between the contact region and an adjacent external lead is 0.15 mm to.
It is 0.20 mm.

【0005】[0005]

【発明が解決しようとする課題】ところが、従来の外部
リード構造では、金属導体が露出した構造であるため、
半導体装置の電気テストの際測定ピンが隣接の外部リー
ドに接触し電気的短絡が発生する危険があり、このた
め、コンタクト領域と隣接する外部リードとのクリアラ
ンスを小さくすることが難しく結果的に外部リードの微
細パターン化の妨げとなっている。
However, in the conventional external lead structure, since the metal conductor is exposed,
When conducting an electrical test of a semiconductor device, there is a risk that the measuring pin may contact an adjacent external lead and cause an electrical short circuit. Therefore, it is difficult to reduce the clearance between the contact area and the adjacent external lead, and as a result external This hinders the fine patterning of leads.

【0006】また、測定ピンが外部リードに接触した
際、測定ピンは縦方向(外部リードに対して垂直)だけ
でなく横方向(外部リードの表面方向)にも変位し、こ
の横方向の変位により外部リードの表面がわずかだが削
り取られる。このため、数多く電気テストを繰り返す
と、測定ピンの先端には削り取られた外部リードの金属
が金属くずとして付着し易い。このようにして、金属く
ずが付着した測定ピンで電気テストを行なうと、金属く
ずにより隣接の外部リードと測定ピンとが電気的短絡を
起こすことが多い。さらに、測定ピンから金属くずが外
部リードに再付着してしまい再付着した金属くずが、半
導体装置の使用中に隣り合った外部リード間で電気的短
絡を起こす場合がある。この結果、半導体装置の誤動作
あるいは半導体装置の破壊が生じてしまうという問題点
がある。そして、この金属くずに基因する問題は、外部
リードの材質が軟い金属程発生し易い。
Further, when the measuring pin comes into contact with the external lead, the measuring pin is displaced not only in the vertical direction (perpendicular to the external lead) but also in the lateral direction (surface direction of the external lead). Causes the surface of the external lead to be slightly scraped off. For this reason, when a large number of electrical tests are repeated, the scraped metal of the external lead easily adheres to the tip of the measuring pin as metal scrap. In this way, when the electrical test is performed on the measuring pin to which the metal scrap is attached, the metal scrap often causes an electrical short circuit between the adjacent external lead and the measuring pin. Further, the metal scraps may be re-attached from the measurement pin to the external leads, and the re-attached metal scraps may cause an electrical short circuit between the adjacent external leads during use of the semiconductor device. As a result, there is a problem that the semiconductor device malfunctions or the semiconductor device is destroyed. The problem caused by the metal scrap is more likely to occur when the metal of the outer lead is softer.

【0007】本発明の目的は、半導体装置の動作試験に
おいて電気的短絡が生じることのない外部リード構造体
を提供することにある。
An object of the present invention is to provide an external lead structure which does not cause an electrical short circuit in the operation test of a semiconductor device.

【0008】[0008]

【課題を解決するための手段】本発明の外部リードは、
外部リードの一主面に測定用治具の測定ピンと相対する
位置に開孔部を千鳥状に形成した絶縁体を有し、かつこ
の開孔部の大きさを隣接の外部リードに接触しない大き
さとしたことを特徴としている。
The external lead of the present invention comprises:
The main surface of the external lead has an insulator with staggered openings at positions facing the measurement pins of the measuring jig, and the size of this opening is large enough not to contact adjacent external leads. It is characterized by the fact that it does.

【0009】かかる構造の外部リードは半導体装置の電
気テストの際、測定ピンは開孔部を通して外部リードと
接触する構造となっている。
The external lead having such a structure has a structure in which the measuring pin is brought into contact with the external lead through the opening portion in the electrical test of the semiconductor device.

【0010】[0010]

【実施例】以下本発明について実施例によって説明す
る。
EXAMPLES The present invention will be described below with reference to examples.

【0011】図1(A)及び(B)を参照して、本実施
例において、図2に示すICパッケージと同一の構成要
素については同一の参照番号を付し説明を省略する。本
実施例では、外部リード7の一主面に予め測定ピン10
に対応する位置(測定ピンが接触される位置)に開孔部
8が千鳥状に形成された厚さ25μm〜100μmのポ
リイミド等の絶縁フィルム9が貼付される。絶縁フィル
ム9の貼付は、半導体ペレット1を組み込む前かあるい
は外部容器6を形成した後に行われる。なお、開孔部8
の大きさは隣接の外部リードに接触しない大きさとす
る。
With reference to FIGS. 1A and 1B, in the present embodiment, the same components as those of the IC package shown in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted. In this embodiment, the measuring pin 10 is previously formed on one main surface of the external lead 7.
An insulating film 9 of polyimide or the like having a thickness of 25 μm to 100 μm, in which the openings 8 are formed in a zigzag shape, is attached to a position corresponding to (a position where the measuring pin is contacted). The attachment of the insulating film 9 is performed before the semiconductor pellet 1 is incorporated or after the outer container 6 is formed. In addition, the opening 8
The size of is such that it does not contact the adjacent external lead.

【0012】上述の構造の外部リードでは、測定ピンが
接触するコンタクト領域の周囲は絶縁フィルムで覆われ
ている為、測定ピンが隣接の外部リードと電気的短絡を
起こす心配がなく、その結果コンタクト領域と隣接の外
部リードとのクリアランスを数十μmまで小さくするこ
とが可能である。
In the external lead having the above-mentioned structure, since the periphery of the contact area where the measuring pin contacts is covered with the insulating film, there is no fear that the measuring pin electrically short-circuits with the adjacent external lead, resulting in contact. It is possible to reduce the clearance between the region and the adjacent external lead to several tens of μm.

【0013】さらに、コンタクト領域の配置を千鳥状と
しているから、コンタクト領域の幅を小さくすることな
く外部リードのピッチを縮小できる。
Further, since the contact areas are arranged in a staggered pattern, the pitch of the external leads can be reduced without reducing the width of the contact areas.

【0014】ここで、図4にコンタクト領域の大きさと
外部リードピッチとの相関関係を示す。
FIG. 4 shows the correlation between the size of the contact area and the external lead pitch.

【0015】ここでは、コンタクト領域を千鳥状に配置
し、外部リードの幅を外部リードピッチの40%と仮定
して、外部リードピッチ、コンタクト領域の幅、及びコ
ンタクト領域のクリアランスの相関関係を示す。図4か
ら明らかなように従来の外部リード構造でコンタクト領
域を千鳥状に配置しても、コンタクト領域と隣接の外部
リードとの間隔を縮小することはできず、可能な外部リ
ードピッチは0.4mmが限定であるが、本発明の第1
の実施例では0.3mmまで可能であることがわかる。
Here, the contact regions are arranged in a staggered pattern, and assuming that the width of the external leads is 40% of the external lead pitch, the correlation between the external lead pitch, the width of the contact regions, and the clearance of the contact regions is shown. .. As is apparent from FIG. 4, even if the contact regions are arranged in a staggered manner in the conventional external lead structure, the distance between the contact regions and the adjacent external leads cannot be reduced, and the possible external lead pitch is 0. The first of the present invention is limited to 4 mm.
It is understood that in the embodiment of the above, it is possible to reach 0.3 mm.

【0016】このような外部リード構造では、金属くず
が付着した測定ピンで電気テストを行っても、金属が露
出したコンタクト領域(開孔部内の外部リード)とコン
タクト領域との間は厚さ25μ〜100μの絶縁フィル
ムが存在するから、金属くずによって電気的短絡が発生
するには、凹部(開孔部)−凸部(絶縁フィルム)−凹
部(開孔部)と3領域にまたがって金属くずが付着しな
い限り電気的短絡は発生せず、従って電気的短絡が発生
する危険性はほとんどない。
In such an external lead structure, even if an electrical test is performed with a measuring pin having metal scrap attached, a thickness of 25 μ is provided between the contact region where the metal is exposed (external lead in the opening) and the contact region. Since ~ 100μ of insulating film is present, in order to cause an electrical short circuit due to metal scraps, metal scraps are formed across recesses (openings) -projections (insulating films) -concave (openings) and three regions. No electrical short circuit will occur unless is attached, so there is little risk of an electrical short circuit occurring.

【0017】次に、図3(A)及び(B)を参照して、
本発明による第2の実施例について説明する。第2の実
施例では、外部リード7の一主面に絶縁体を塗布する為
のポリイミド等の支持フィルム11を貼付し、その支持
フィルム11と対応する位置において外部リードの他方
の面にソルダーレジスト等の絶縁体9を塗布し、その
後、測定ピン10と対応する位置に開孔部8を形成す
る。なお、開孔部8の大きさは隣接の外部に接触しない
大きさとされる。そして、第1の実施例と同様にして開
孔部8は千鳥状に配置される。
Next, referring to FIGS. 3A and 3B,
A second embodiment according to the present invention will be described. In the second embodiment, a support film 11 made of polyimide or the like for applying an insulator is attached to one main surface of the external lead 7, and solder resist is applied to the other surface of the external lead at a position corresponding to the support film 11. An insulating material 9 such as the above is applied, and then the opening portion 8 is formed at a position corresponding to the measuring pin 10. The size of the opening 8 is set so that it does not come into contact with the adjacent outside. Then, the apertures 8 are arranged in a staggered manner as in the first embodiment.

【0018】第2の実施例に示す構造の外部リードで
は、絶縁体を外部リードの一主面に塗布した後、写真蝕
刻法等を用いて、開孔部を形成しているから、第1の実
施例における外部リードの構造に比べて外部リードと開
孔部との位置精度は高くその結果、コンタクト領域と隣
接の外部リードとの間隔を小さくできる。
In the external lead having the structure shown in the second embodiment, since the insulating material is applied to one main surface of the external lead and then the opening portion is formed by using a photo-etching method or the like, the first lead is formed. As compared with the structure of the external lead in the above embodiment, the positional accuracy of the external lead and the opening portion is high, and as a result, the distance between the contact region and the adjacent external lead can be reduced.

【0019】一方、第2の実施例では、外部リードの両
面が絶縁材で覆われているので、半導体装置を実装基板
に実装する際、実装部分を外して外部リードにコンタク
ト領域を設ける必要がある。
On the other hand, in the second embodiment, since both surfaces of the external lead are covered with the insulating material, when mounting the semiconductor device on the mounting substrate, it is necessary to remove the mounting portion and provide a contact region on the external lead. is there.

【0020】[0020]

【発明の効果】以上説明したように、本発明では測定ピ
ンと外部リードとが接触するコンタクト領域の周囲を絶
縁体で覆うようにしたので、従来に比べてコンタクト領
域と隣接の外部リードとの間隔を100μm以上小さく
できる。さらに、半導体装置の電気テストの際、金属く
ずによる電気的短絡を防ぐことができ、また、金属くず
の外部リードへの再付着を防止することができるという
効果がある。
As described above, according to the present invention, the contact area around the contact between the measuring pin and the external lead is covered with the insulator, so that the distance between the contact area and the adjacent external lead is larger than that in the conventional case. Can be reduced by 100 μm or more. Further, in the electrical test of the semiconductor device, there is an effect that an electrical short circuit due to metal scrap can be prevented, and that the metal scrap can be prevented from reattaching to the external lead.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明によるICパッケージの一実施例を示す
図で、(A)は平面図、(B)は(A)のX−X′線で
の断面図である。
1A and 1B are views showing an embodiment of an IC package according to the present invention, FIG. 1A is a plan view, and FIG. 1B is a sectional view taken along line XX ′ of FIG.

【図2】従来のICパッケージを示す図で、(A)は平
面図、(B)は(A)のX−X′線での断面図である。
2A and 2B are views showing a conventional IC package, FIG. 2A being a plan view and FIG. 2B being a cross-sectional view taken along line XX ′ in FIG.

【図3】本発明によるICパッケージの第2の実施例を
示す図で、(A)は平面図、(B)は(A)のX−X′
線での断面図である。
3A and 3B are views showing a second embodiment of an IC package according to the present invention, FIG. 3A is a plan view, and FIG.
It is sectional drawing in a line.

【図4】外部リード・ピッチとコンタクト領域の大きさ
との相関関係を示す図である。
FIG. 4 is a diagram showing a correlation between an external lead pitch and a size of a contact region.

【符号の説明】[Explanation of symbols]

1 半導体ペレット 2 外部引き出し電極 3 マウント領域 4 ボンディング線 5 ボンディング領域 6 外部容器 7 外部リード 8 開孔部 9 絶縁体 10 測定ピン 11 支持フィルム 1 Semiconductor Pellet 2 External Extraction Electrode 3 Mounting Area 4 Bonding Line 5 Bonding Area 6 External Container 7 External Lead 8 Open Hole 9 Insulator 10 Measuring Pin 11 Support Film

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子が搭載されるマウント領域
と、該半導体素子の外部引出電極と電気的に接続される
ボンディング領域と、前記マウント領域及び前記ボンデ
ィング領域を密封する外部容器と、前記ボンディング領
域上を延在し該ボンディング領域から外方に突出する複
数の外部リードと、前記外部リードの一主面上に形成さ
れた絶縁体とを有し、該絶縁体の所定位置には前記外部
リードに達する開孔部が形成されていることを特徴とす
るICパッケージ。
1. A mount area on which a semiconductor element is mounted, a bonding area electrically connected to an external lead electrode of the semiconductor element, an external container for sealing the mount area and the bonding area, and the bonding area. A plurality of external leads extending upward and projecting outward from the bonding region; and an insulator formed on one main surface of the external lead, the external lead being provided at a predetermined position of the insulator. The IC package is characterized in that an opening reaching up to is formed.
【請求項2】 請求項1に記載されたICパッケージに
おいて、前記開孔部は前記外部リードのおのおのに対応
して形成されており、これら複数の開孔部は千鳥状に配
列されていることを特徴とするICパッケージ。
2. The IC package according to claim 1, wherein the openings are formed corresponding to each of the external leads, and the openings are arranged in a staggered pattern. IC package characterized by.
JP4118884A 1992-05-12 1992-05-12 Ic package Withdrawn JPH05315534A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4118884A JPH05315534A (en) 1992-05-12 1992-05-12 Ic package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4118884A JPH05315534A (en) 1992-05-12 1992-05-12 Ic package

Publications (1)

Publication Number Publication Date
JPH05315534A true JPH05315534A (en) 1993-11-26

Family

ID=14747527

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4118884A Withdrawn JPH05315534A (en) 1992-05-12 1992-05-12 Ic package

Country Status (1)

Country Link
JP (1) JPH05315534A (en)

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