JPH05315519A - Semiconductor element - Google Patents

Semiconductor element

Info

Publication number
JPH05315519A
JPH05315519A JP11583292A JP11583292A JPH05315519A JP H05315519 A JPH05315519 A JP H05315519A JP 11583292 A JP11583292 A JP 11583292A JP 11583292 A JP11583292 A JP 11583292A JP H05315519 A JPH05315519 A JP H05315519A
Authority
JP
Japan
Prior art keywords
solder
tip
lead wire
lead
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11583292A
Other languages
Japanese (ja)
Inventor
Takahiro Kobayashi
高弘 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP11583292A priority Critical patent/JPH05315519A/en
Publication of JPH05315519A publication Critical patent/JPH05315519A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the short circuit between lead wires by fused solder, and to improve junction strength by a method wherein the tip of the lead wires of a semiconductor element, having a plurality of lead wires, is formed into a tapered shape. CONSTITUTION:A GFP 1, with a plurality of lead wires, has a tapered part 3 in which the thickness of the tip 2 of a lead wire, which comes in contact with a circuit substrate, is thinned off. The solder, which is fused and adhered on the tip 2 of the lead wire, is adhered and bonded covering the tip of the lead wire. Accordingly, the bonding strength can be increased twice or more when compared with the lead wire bonded by solder on the outer circumference. Also, as the tip of the lead wire can be covered by a small quantity of solder, the quantity of solder cream can be reduced to obtain the same strength, and the defective short circuit generating between leads, which is called a bridge, can be decreased remarkably.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電子機器等の回路基板
に搭載される複数のリード線を有する表面実装用半導体
素子のリード線先端形状に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead wire tip shape of a surface mounting semiconductor element having a plurality of lead wires mounted on a circuit board of an electronic device or the like.

【0002】[0002]

【従来の技術】従来の複数のリード線を有する表面実装
用半導体素子を図4に示す。図4はQFP1の例である
が、リード線先端2から根元まで均一の厚みである。こ
のQFP1を回路基板上のランド部に印刷等によって塗
られた半田クリーム上にマウンター等でセットしリフロ
ー炉においてリード線と回路基板上の半田とを加熱接合
している。加熱後のリード線先端2の半田の接合部は図
5に示すような円弧状の半田フィレット4となってい
る。
2. Description of the Related Art FIG. 4 shows a conventional surface mount semiconductor device having a plurality of lead wires. FIG. 4 shows an example of the QFP 1, which has a uniform thickness from the lead wire tip 2 to the root. The QFP1 is set on a solder cream applied to the land portion on the circuit board by printing or the like by a mounter or the like, and the lead wire and the solder on the circuit board are heat-bonded in a reflow furnace. The solder joint portion of the lead wire tip 2 after heating is an arc-shaped solder fillet 4 as shown in FIG.

【0003】[0003]

【発明が解決しようとする課題】しかし、前述の従来技
術では、塗布される半田クリーム量の増減や加わる熱量
のばらつきによりブリッジと呼ばれるリード線間の半田
による短絡不良が発生したり、その発生を少なくするた
めに半田クリームの塗布量を全体的に少なくすると強度
不足不良になるなど製造歩留まりが悪いという課題を有
する。また、回路基板実装の外観検査の自動化が進んで
きているが、例えば、リード線先端の半田フィレット部
に照明をあて、その反射光によって良不良を判定する方
法においてはフィレット形状がばらつき易い従来方法で
は検出精度を上げることが非常に難しく、検査コストが
上昇するという課題を有する。今後は、表面基板実装に
おいても、ますます高密度化され、リード線間ピッチの
極小化、部品点数の増大によって、半田付け不良による
不良コストまた、検査コスト等がさらに上昇することが
予想される。従って、これらの課題を解決する半導体素
子の開発が望まれている。そこで本発明はこのような課
題を解決するもので、その目的とするところは半導体素
子のリード線先端の簡単な形状変更で、半田ブリッジ不
良をおさえ接合強度も確保するとともに外観検査もしや
すく検査コスト削減を図ることの出来る半導体素子を提
供するところにある。
However, in the above-mentioned prior art, short-circuit defects due to solder between the lead wires called bridges may occur or may occur due to variations in the amount of applied solder cream or variations in the amount of heat applied. If the coating amount of the solder cream is reduced as a whole in order to reduce the amount, there is a problem that the manufacturing yield is poor such as insufficient strength and defects. Further, automation of appearance inspection of circuit board mounting is progressing. For example, in the method of illuminating the solder fillet portion at the tip of the lead wire and determining good or defective by the reflected light, the conventional method in which the fillet shape is likely to vary Therefore, it is very difficult to improve the detection accuracy, and there is a problem that the inspection cost increases. In the future, even in surface board mounting, it is expected that the density will become higher and higher, the pitch between lead wires will be minimized, and the number of parts will increase, resulting in higher defective costs due to poor soldering and higher inspection costs . Therefore, development of a semiconductor device that solves these problems is desired. Therefore, the present invention solves such a problem, and the purpose thereof is to easily change the shape of the lead wire tip of the semiconductor element, suppress solder bridge defects, secure the bonding strength, and easily perform the appearance inspection and the inspection cost. It is an object to provide a semiconductor element that can be reduced.

【0004】[0004]

【課題を解決するための手段】本発明の半導体素子は、
複数のリード線を有する半導体素子において、回路基板
に当接する前記半導体素子のリード線の先端部がテーパ
上に薄くなっていることを特徴とする。また、リード線
先端に半田がプリコートされていることを特徴とする。
The semiconductor device of the present invention comprises:
In a semiconductor element having a plurality of lead wires, the tip of the lead wire of the semiconductor element that contacts the circuit board is tapered and thin. Further, it is characterized in that the tip of the lead wire is pre-coated with solder.

【0005】[0005]

【実施例】(実施例1)以下、本発明の実施例を図1、
図2により説明する。図1に示すように、複数のリード
線を有するQFP1において、回路基板に接するリード
線先端2が先端厚みが薄くなるようなテーパ部3を有し
ている。この素子を回路基板のランド上にあらかじめス
クリーン印刷された半田クリームあるいは、他の方法で
あらかじめコーティングした半田の上にマウントし、リ
フロー炉等によって加熱接合した後の半田フィレット4
の形状を図2に示す。図2に示すように、リード線先端
2では溶融し固着した半田はリード線先端を覆う形で固
着接合している。従って接合強度はリード線外周を半田
で固着している場合に比べ、倍以上確保できる。また、
少ない半田でもリード線先端を覆うことが出来るので、
同じ強度を得るにも半田クリーム量を減らすことが出
来、ブリッジと呼ばれるリード間の短絡不良を極端に低
減することが出来る。これは、高密度になりリード線間
のピッチが狭くなるとますます効果が大きくなる。この
様に、リード線先端をテーパ上にすることにより実装で
の歩留りは大きく向上する。また、回路基板上がりで外
観検査を自動で行う場合に、半田フィレット部に照明を
あてその反射光によって良否の判定を行う場合や半田フ
ィレット上をレーザー光で走査してその形状によって良
否を判定する場合には、半田フィレットのばらつきによ
って良否の誤判定率が高く、実用レベルにまで立ち上げ
る事が非常に困難である。しかし、リード線先端をテー
パ状にすることによって、良否判定基準を単純にするこ
とができるため、外観自動検査が非常に簡便になる。こ
の良否判定基準は、例えばリード線先端のテーパ部中心
をレーザー光を走査した時のテーパ角度の変化の有無と
すれば良い。リード線先端と半田の接合が良好であれ
ば、リード線先端が半田で覆われるためテーパ角度が変
化するのでこの場合には良品と判定すれば良い。逆に、
半田の濡れが悪かったり、リード線の浮きがあったりす
ると、リード線先端のテーパ部は半田が無く、角度が一
定で変化が無いので、不良と判定すれば良い。このリー
ド線先端のテーパ角度5の大きさは、各半導体素子によ
って任意に設定すれば良いが、上記効果を出すために
は、テーパ角度5は45度程度以下であればよいが、出
来れば30度近辺が最適である。また、リード線先端高
さ6は出来る限り小さい方が良く、余り大きくすると狙
いとする効果が得られなくなる。
(Embodiment 1) Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. As shown in FIG. 1, in a QFP 1 having a plurality of lead wires, a lead wire tip 2 in contact with a circuit board has a tapered portion 3 such that the tip thickness becomes thin. This element is mounted on a solder cream previously screen-printed on a land of a circuit board or a solder previously coated by another method, and is heat-bonded by a reflow furnace or the like to fill the solder fillet 4.
The shape of is shown in FIG. As shown in FIG. 2, the solder melted and fixed at the tip 2 of the lead wire is fixedly joined to cover the tip of the lead wire. Therefore, the bonding strength can be more than doubled as compared with the case where the outer circumference of the lead wire is fixed with solder. Also,
Since the tip of the lead wire can be covered with a little solder,
Even if the same strength is obtained, the amount of solder cream can be reduced, and a short circuit between leads called a bridge can be extremely reduced. This becomes more effective as the density becomes higher and the pitch between the lead wires becomes narrower. In this way, by tapering the tip of the lead wire, the yield in mounting is greatly improved. In addition, when the appearance inspection is automatically performed after the circuit board is raised, when the solder fillet is illuminated and the quality of the light is determined by the reflected light, or when the solder fillet is scanned with a laser beam, the quality is determined by the shape. In this case, the erroneous determination rate of quality is high due to the variation of the solder fillet, and it is very difficult to start up to a practical level. However, by tapering the tip of the lead wire, the quality judgment standard can be simplified, so that the automatic appearance inspection becomes very simple. This quality criterion may be, for example, the presence or absence of a change in the taper angle when the center of the taper portion at the tip of the lead wire is scanned with laser light. If the connection between the lead wire tip and the solder is good, the taper angle changes because the tip of the lead wire is covered with the solder, and in this case, it may be determined as a good product. vice versa,
If the wetness of the solder is bad or the lead wire floats, the taper portion at the tip of the lead wire has no solder, the angle is constant and there is no change, so it can be determined as defective. The size of the taper angle 5 at the tip of the lead wire may be arbitrarily set according to each semiconductor element. To obtain the above effect, the taper angle 5 may be about 45 degrees or less, but if possible, 30 The best is around. Further, it is preferable that the height 6 of the tip of the lead wire is as small as possible, and if it is too large, the desired effect cannot be obtained.

【0006】この、半導体素子のリード線先端にテーパ
をつける方法は、通常行われているリードフレームから
半導体素子を切り離し、同時にリード線先端形状のフォ
ーミングを行う、プレス工程において、切断時のプレス
型を、切断後にリード線先端をつぶす事が出来る形状に
変更するだけで良い。
[0006] This method of tapering the tip of the lead wire of the semiconductor element is performed by a pressing die at the time of cutting in a pressing step in which the semiconductor element is separated from a lead frame which is usually used, and at the same time, the shape of the tip of the lead wire is formed. Need only be changed to a shape that allows the tip of the lead wire to be crushed after cutting.

【0007】(実施例2)今後ますます、高密度化が進
むと、従来の回路基板への半田クリーム印刷による半田
の供給では品質的に対応が取れなくなって来る。そこ
で、本実施例においては図3に示すように複数のリード
線を有し、そのリード線先端2がテーパ状に先端が薄く
なっている半導体素子のリード線先端2に、プリコート
半田7を備えている。回路基板上の任意のランド上に、
この素子をマウントし、加熱ツールを押し当てて、プリ
コートされた半田を溶融し、回路基板と素子を固着接合
する。この時、溶融した半田はリード線先端のテーパ部
をスムーズに流れ、リード先端部を覆い固着する。従来
からの半導体素子のリード線先端に半田をプリコートし
たものについては、同じ方法を取ると、半田がリード線
周囲に流れ、半田がリード線先端を覆うことはなくリー
ド線回りのフィレット部のみで固着されるので、強度を
確保するためには半田プリコートの量をある程度充分に
確保しておく必要があるが、本実施例の場合において
は、従来よりもプリコート半田の量を少なくしても強度
が確保できるので、半田のプリコートに要する時間が短
くでき、量産時においては低コスト化が図れる。この、
リード線先端に半田をプリコートする方法については、
例えば、電気的な半田メッキや溶融半田のスプレー塗布
等で行えばよい。
(Example 2) As the density becomes higher and higher in the future, the conventional solder supply by solder cream printing to a circuit board cannot meet the quality requirement. Therefore, in the present embodiment, as shown in FIG. 3, the lead wire tip 2 of the semiconductor element having a plurality of lead wires and the tip of the lead wire 2 being tapered is provided with the precoat solder 7. ing. On any land on the circuit board,
This element is mounted, and a heating tool is pressed to melt the precoated solder, and the element is fixedly bonded to the circuit board. At this time, the melted solder smoothly flows through the taper portion at the tip of the lead wire to cover and fix the tip portion of the lead. For the conventional semiconductor element with the lead wire tip pre-coated with solder, if the same method is used, the solder will flow around the lead wire and the solder will not cover the lead wire tip, only the fillet part around the lead wire. Since it is fixed, it is necessary to secure a sufficient amount of solder precoat in order to secure the strength, but in the case of this embodiment, even if the amount of precoat solder is reduced compared to the conventional case, the strength is improved. Can be secured, the time required for pre-coating the solder can be shortened, and the cost can be reduced in mass production. this,
For pre-coating solder on the tip of the lead wire,
For example, electrical solder plating or spray application of molten solder may be used.

【0008】[0008]

【発明の効果】本発明によれば、複数のリード線を有す
る半導体素子のリード線先端をテーパ状にすることによ
って、回路基板への半導体素子の固着時において、リー
ド線間の溶融半田による短絡を防止し、高密度表面実装
時における歩留の向上、及び品質の向上が図れるという
効果を有する。さらに、表面実装基板の外観検査の自動
化において、簡単に短時間で検査が出来るようになるこ
とから、回路基板実装に掛かるコストを大幅に削減でき
るという効果を有する。
According to the present invention, the tip of the lead wire of the semiconductor element having a plurality of lead wires is tapered, so that when the semiconductor element is fixed to the circuit board, a short circuit is caused by the molten solder between the lead wires. This has the effect of preventing the above, and improving the yield and quality at the time of high-density surface mounting. Further, in the automation of the appearance inspection of the surface mounting board, the inspection can be easily performed in a short time, so that the cost for mounting the circuit board can be significantly reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明における実施例1の半導体素子の部分斜
視図。
FIG. 1 is a partial perspective view of a semiconductor device according to a first embodiment of the present invention.

【図2】本発明における実施例1の半田フィレット形状
を示す部分断面図。
FIG. 2 is a partial cross-sectional view showing a solder fillet shape according to the first embodiment of the present invention.

【図3】本発明における実施例2の半導体素子のリード
線先端の部分断面図。
FIG. 3 is a partial cross-sectional view of a tip of a lead wire of a semiconductor device according to a second embodiment of the present invention.

【図4】従来の半導体素子の部分斜視図。FIG. 4 is a partial perspective view of a conventional semiconductor device.

【図5】従来の半田フィレット形状を示す部分断面図。FIG. 5 is a partial sectional view showing a conventional solder fillet shape.

【符号の説明】[Explanation of symbols]

1 QFP(半導体素子) 2 リード線先端 3 テーパ部 4 半田フィレット 5 テーパ角度 6 リード線先端高さ 7 プリコート半田 1 QFP (semiconductor element) 2 Lead wire tip 3 Tapered part 4 Solder fillet 5 Taper angle 6 Lead wire tip height 7 Precoat solder

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 複数のリード線を有する半導体素子にお
いて、回路基板に当接する該半導体素子のリード線の先
端部がテーパ状に薄くなっていることを特徴とする半導
体素子。
1. A semiconductor element having a plurality of lead wires, wherein a tip of a lead wire of the semiconductor element that abuts a circuit board is tapered and thinned.
【請求項2】 リード線先端に半田がプリコートされて
いることを特徴とする請求項1記載の半導体素子。
2. The semiconductor element according to claim 1, wherein the tip of the lead wire is pre-coated with solder.
JP11583292A 1992-05-08 1992-05-08 Semiconductor element Pending JPH05315519A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11583292A JPH05315519A (en) 1992-05-08 1992-05-08 Semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11583292A JPH05315519A (en) 1992-05-08 1992-05-08 Semiconductor element

Publications (1)

Publication Number Publication Date
JPH05315519A true JPH05315519A (en) 1993-11-26

Family

ID=14672228

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11583292A Pending JPH05315519A (en) 1992-05-08 1992-05-08 Semiconductor element

Country Status (1)

Country Link
JP (1) JPH05315519A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109962050A (en) * 2019-04-19 2019-07-02 苏州浪潮智能科技有限公司 A kind of pin on component
IT202000007411A1 (en) * 2020-04-07 2021-10-07 St Microelectronics Srl Leadframe for semiconductor products

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109962050A (en) * 2019-04-19 2019-07-02 苏州浪潮智能科技有限公司 A kind of pin on component
CN109962050B (en) * 2019-04-19 2024-04-26 苏州浪潮智能科技有限公司 Pin for component
IT202000007411A1 (en) * 2020-04-07 2021-10-07 St Microelectronics Srl Leadframe for semiconductor products

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