JPH05315335A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent a short circuit between interconnection lines caused by lateral hillocks, and to obtain a semiconductor integrated circuit which allows automatic design rule checks to be easily executed by arranging a metal interconnection line whose line width is finer than a specific value disposed adjacent to a metal interconnection line whose line width exceeds the specific value. CONSTITUTION:Aluminum films or aluminum alloy films are arranged on a semiconductor substrate at an interval of 2mum and less, and a number of metal interconnections 2a-2c, which are coated with a metal thin film having a high fusing point or a silicid thin film and are arranged in a laminated structure, are laid over the top surface of the alminum film or the aluminum alloy film. In such a semiconductor integrated circuit, a metal interconnection line 2c having a width L which is finer than 10mum is arranged adjacent to a metal interconnection line 2a which exceeds 10mum. It is desirable that the metal interconnection 2a which exceeds 10mum and the metal interconnection 2c whose width L is finer than 10mum be formed so that they can be always equal in electric potential. Thereby, the laminated metal interconnection line 2c having the fine line width L serves as a barrier, and it is possible to prevent a short circuit between the metal interconnection line and another laminated metal interconnection line 2b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is used for the layout of laminated metal wiring of a semiconductor integrated circuit. The present invention relates to a semiconductor integrated circuit capable of preventing a short circuit between wirings due to a lateral hillock.

[0002]

2. Description of the Related Art Conventionally, electrical connections inside semiconductor integrated circuits have been made of aluminum or aluminum alloys, but stress migration countermeasures have become apparent due to the miniaturization of metal wiring accompanying the high integration of integrated circuits. As a method, a laminated metal wiring in which a refractory metal thin film or a silicide thin film thereof is formed in the upper layer or the upper and lower layers of the wiring is beginning to be used.

In the case of this laminated metal wiring, lateral hillocks are generated in a wide laminated metal wiring having a width of several tens of μm such as a power supply line during a heat treatment of a post-process such as wiring alloying and formation of a passivation film. The spacing is 2 μm
In the case of the wirings laid out below, there is a risk of short-circuiting between the wiring and another adjacent laminated metal wiring. In order to prevent a short circuit between wirings due to this lateral hillock, the following two methods have been conventionally used.

FIGS. 3A and 3B are views for explaining the process for preventing the occurrence of lateral hillocks. In this method, after the laminated metal wiring 2 is formed on the semiconductor substrate 1,
As shown in FIG. 4A, a thin plasma oxide film 3 of about 1000 Å is grown in a short time by a plasma-assisted chemical vapor deposition method (hereinafter referred to as plasma CVD) under a low temperature condition of 300 ° C. or less, and this thin plasma oxide film is formed. 3, the alloy treatment is performed at 400 to 450 ° C. for 5 to 30 minutes with the laminated metal wiring 2 being covered, and then the passivation film 4 made of a thick inorganic film of several thousand liters is formed by plasma CVD at 300 to 400 ° C. Is formed.

FIG. 4 is a diagram for explaining a method of preventing a short circuit between wirings due to a lateral lock by a wiring layout. In this method, the laminated metal wiring 2a having a wide wiring width of several tens of μm in which the lateral hillocks 5 may be generated in the heat treatment step after the wiring formation is replaced with another laminated metal wiring 2b.
It is arranged at a sufficient distance from, and is laid out so as not to cause a short circuit even if a lateral hillock 5 is generated.

[0006]

The method of preventing the generation of lateral hillocks shown in FIG. 3 leads to an increase in the number of steps, and the thermal stress during heat treatment causes a thin plasma oxide film covering the laminated metal wiring. Concentrates on the weaker areas of, and strikes the thin plasma oxide film, which may cause larger lateral hillocks.

Further, in the wiring layout shown in FIG. 4, in order to prevent a short circuit between wirings, it is necessary to set a wiring interval of about 4 μm when the average of the generated lateral hillock length is 1 μm. It becomes a problem for high integration. Furthermore, in an automatic design rule check program executed by a computer in recent years, it is customary to check the wiring interval based on the minimum allowable wiring interval.
In an integrated circuit in which a value of around μm is used, it is difficult to check by automatic design rule check whether or not wiring intervals adjacent to a wiring having a large wiring width are designed at proper intervals. Therefore, there is a problem that the manual check by human beings has to intervene and the efficiency of the circuit design check is lowered.

The present invention has been made under such a background, and an object thereof is to provide a semiconductor integrated circuit capable of preventing a short circuit between wirings due to a lateral hillock and easily performing an automatic design rule check. ..

[0009]

According to the present invention, an aluminum film or an aluminum alloy film having a thickness of 2 μm is formed on a semiconductor substrate.
In a semiconductor integrated circuit having a plurality of metal wirings of a laminated structure which are arranged at intervals of m or less and whose upper surface is covered with a refractory metal thin film or a silicide thin film,
It is characterized in that a metal wiring having a finer width than 10 μm is arranged adjacent to a metal wiring having a wiring width exceeding m.

The metal wiring exceeding 10 μm and the metal wiring
It is desirable that the metal wiring having a width finer than μm is always formed to have the same potential.

[0011]

The laminated metal wiring having a fine width in which lateral hillocks are unlikely to be formed adjacent to the laminated metal wiring having a large width serves as a barrier to prevent short-circuiting between other laminated metal wirings. Further, by increasing the potential of the wide laminated metal wiring and the fine-width laminated metal wiring, the electric conduction is improved,
The automatic design rule check can be performed easily.

[0012]

Embodiments of the present invention will now be described with reference to the drawings. (First Embodiment) FIG. 1 is a diagram showing a wiring layout in a first embodiment of the present invention.

In the first embodiment of the present invention, a plurality of laminated structures in which an aluminum film or an aluminum alloy film is arranged at intervals of 2 μm or less on a semiconductor substrate, and a refractory metal thin film or a silicide thin film is coated on the upper surface thereof Among the metal wirings, a laminated metal wiring 2c having a fine width of more than 10 μm is arranged adjacent to the laminated metal wiring 2a having a wide wiring width of more than 10 μm. 2c is always formed to have the same potential.

That is, for the laminated metal wiring 2a having a wide wiring width (for example, several tens of μm) in which a lateral hillock may occur, the minimum wiring interval and the fine width designed with the minimum wiring width allowed by the design rule ( For example, a laminated metal wiring 2c of 1 μm) is arranged adjacently, and the laminated metal wiring 2c having a fine width serves as a barrier to prevent a short circuit between wirings with another laminated metal wiring 2b. Although the laminated metal wiring 2c having a fine width is electrically floating in FIG. 1, it may be connected to the laminated metal wiring 2a having a wide wiring width to have the same potential. Further, the wiring width to be implemented is slightly different depending on the material of the film to be laminated and the laminated structure, but it is desirable to apply it to laminated wiring having a width of 10 μm or more.

W in the figure is a laminated metal wiring 2 having a wide wiring width.
The wiring width of a is shown, and S and L show the minimum wiring interval and the minimum wiring width which are allowed in the design rule. (Second Embodiment) FIG. 2 is a diagram showing a wiring layout in a second embodiment of the present invention. In the second embodiment, as in the first embodiment, instead of adding the laminated metal wiring 2c having a fine width adjacent to the laminated metal wiring 2a having a wide wiring width with the minimum wiring interval and the minimum wiring width, Wide laminated metal wiring 2
Wiring width that does not cause lateral hillock from a (for example, 10
a laminated metal wiring having a fine width
As c, they are separated at the minimum wiring interval, and are electrically contributed to the same potential by positively contributing to electric conduction. As a result, it becomes possible to integrate by 2 × the minimum wiring width as compared with the case of the first embodiment.

In the figure, W'represents the wiring width of the modified laminated metal wiring 20a having a wide wiring width, W _m represents the wiring width of the laminated metal wiring 20c having a fine width, and L≤W _m <lateral hillock The effective wiring width W is W = W '+ 2W _m .

[0017]

As described above, according to the present invention, 1
1 adjacent to a laminated metal wiring having a wiring width of 0 μm or more
By installing the laminated metal wiring finer than 0 μm at the same potential, it is possible to prevent a short circuit between the wirings due to the lateral hillock without changing the process, and it is possible to easily perform the automatic design rule check by the computer. ..

[Brief description of drawings]

FIG. 1 is a diagram showing a wiring layout in a first embodiment of the present invention.

FIG. 2 is a diagram showing a wiring layout according to a second embodiment of the present invention.

3A and 3B are cross-sectional views illustrating a process of preventing lateral hillocks in a conventional example.

FIG. 4 is a diagram showing a conventional wiring layout for preventing a short circuit between wiring lines.

[Explanation of symbols]

 1 semiconductor substrate 2 laminated metal wiring 2a, 20a laminated metal wiring with wide wiring 2b other laminated metal wiring 2c, 20c laminated metal wiring with fine width 3 thin plasma oxide film 4 passivation film 5 lateral hillocks

Claims (2)

[Claims] 1. A semiconductor integrated device having an aluminum film or an aluminum alloy film arranged at an interval of 2 μm or less on a semiconductor substrate, and having a plurality of metal wirings of a laminated structure covered with a refractory metal thin film or a silicide thin film on the upper surface thereof. In the circuit, 10 μm adjacent to the metal wiring with a wiring width exceeding 10 μm
A semiconductor integrated circuit in which metal wiring having a finer width than that of the semiconductor integrated circuit is arranged. 2. The metal wiring having a thickness of more than 10 μm and the metal wiring
2. The semiconductor integrated circuit according to claim 1, wherein the metal wiring having a width smaller than 0 μm is always formed to have the same potential.