JPH0531330B2 - - Google Patents

Info

Publication number
JPH0531330B2
JPH0531330B2 JP62042103A JP4210387A JPH0531330B2 JP H0531330 B2 JPH0531330 B2 JP H0531330B2 JP 62042103 A JP62042103 A JP 62042103A JP 4210387 A JP4210387 A JP 4210387A JP H0531330 B2 JPH0531330 B2 JP H0531330B2
Authority
JP
Japan
Prior art keywords
output
circuit
delay
input signal
demodulator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62042103A
Other languages
Japanese (ja)
Other versions
JPS63208330A (en
Inventor
Yukitsuna Furuya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP62042103A priority Critical patent/JPS63208330A/en
Publication of JPS63208330A publication Critical patent/JPS63208330A/en
Publication of JPH0531330B2 publication Critical patent/JPH0531330B2/ja
Granted legal-status Critical Current

Links

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は無線器の送信増幅器の歪を入力信号を
歪ませることにより補償し、かつその補償量を送
信増幅器出力と入力信号とを比較することにより
適応的に変化させるアダプテイブプリデイストー
ター付送信機に関する。
[Detailed Description of the Invention] (Industrial Application Field) The present invention compensates for distortion in a transmitting amplifier of a wireless device by distorting an input signal, and compares the amount of compensation between the output of the transmitting amplifier and the input signal. The present invention relates to a transmitter with an adaptive predistorter that changes adaptively.

(従来の技術) 一般に無線器、特に移動通信用の無線器におい
ては電力の有効利用の為に送信増幅器を飽和領域
で動作させるのが普通である。このような無線器
においてQAMのような振幅の変化する線形変調
方式を用いようとすると、送信増幅器の非線形特
性により歪が生じてスペクトラムが広がつてしま
う。これに対する対策として送信増幅器への入力
を予め歪ませておき送信増幅器の出力で歪が無い
ようにするプリデイストーターがある。更に送信
増幅器の温度変化や時間変化による特性の変動を
補償する為に送信増幅器の出力を復調して入力と
比較し送信増幅器の出力が常に歪が無いように制
御するアダプテイブプリデイストーターが提案さ
れている。
(Prior Art) In general, in radio equipment, particularly in radio equipment for mobile communication, it is common to operate a transmission amplifier in a saturation region in order to use power effectively. If an attempt is made to use a linear modulation method in which the amplitude changes, such as QAM, in such a radio device, distortion will occur due to the nonlinear characteristics of the transmission amplifier, and the spectrum will widen. As a countermeasure against this problem, there is a predistorter that distorts the input to the transmission amplifier in advance so that the output of the transmission amplifier is free of distortion. Furthermore, in order to compensate for fluctuations in characteristics due to temperature changes and time changes in the transmitting amplifier, an adaptive predistorter is installed that demodulates the output of the transmitting amplifier and compares it with the input to control the output of the transmitting amplifier so that it is always distortion-free. Proposed.

このアダプテイブプリデイストーターは昭和60
年発行の論文集である昭和60年度電子通信学会情
報、システム部門全国大会論文集の第2分冊の70
ページに詳しい。
This adaptive pre-day stator is from the 1980s.
Volume 70 of the second volume of the 1985 IEICE Information and Systems Division National Conference Proceedings, a collection of papers published in 2005.
Familiar with the page.

(発明が解決しようとする問題点) しかしながら従来のアダプテイブプリデイスト
ーターにおいては変調器、送信増幅器および復調
器からなる回路での遅延が考慮されていない。従
つて、異なつた時刻での入力信号と復調器出力を
比較してしまい適応化がうまくいかない可能性が
ある。さらにこの遅延量は周波数帯によつて異な
るので自動車電話機のように呼ごとに異なつた周
波数で送信するような場合にはその度に異なつた
遅延量を補償しなくてはならず正しく適応化させ
るのは極めて難しいという欠点があつた。
(Problems to be Solved by the Invention) However, in the conventional adaptive predistorter, delay in a circuit including a modulator, a transmission amplifier, and a demodulator is not taken into account. Therefore, the input signal and the demodulator output at different times may be compared, and the adaptation may not be successful. Furthermore, this amount of delay differs depending on the frequency band, so if each call is transmitted on a different frequency, such as in a car phone, it is necessary to compensate for the different amount of delay each time, and to ensure proper adaptation. The drawback was that it was extremely difficult.

本発明の目的は、上述の従来のアダプテイブプ
リデイストーターの欠点を取除き、遅延の補償を
も適応的に行う遅延補償型アダプテイブプリデイ
ストーター付送信機を提供することにある。
An object of the present invention is to provide a transmitter with a delay compensation type adaptive predistorter that eliminates the drawbacks of the conventional adaptive predistorter described above and also adaptively compensates for delay.

(問題点を解決するための手段) 本発明においては、入力信号のそれぞれの値に
対応した歪量を記憶するメモリーと、このメモリ
ーの出力と前記入力信号とを加算する加算器と、
この加算器の出力を変調する変調器と、この変調
器の出力を増幅する送信増幅器と、この送信増幅
器の出力を復調する復調器と、前記入力信号を遅
延させる可変長遅延回路と、この可変長遅延回路
の出力と前記復調器出力との差を取る減算器と、
この減算器の出力を用いて前記メモリーの内容を
更新する適応化回路と、前記可変長遅延回路の出
力を時間微分する微分回路と、この微分回路の出
力の符号と前記減算器出力を乗算する乗算器と、
この乗算器の出力を積分するローパスフイルター
と、このローパスフイルターの出力により前記可
変長遅延回路の遅延量を補正する遅延制御回路と
を有することを特徴とした遅延補償型アダプテイ
ブプリデイストーター付送信機によつて上記問題
点を解決している。
(Means for Solving the Problems) The present invention includes: a memory that stores the amount of distortion corresponding to each value of an input signal; an adder that adds the output of this memory and the input signal;
a modulator that modulates the output of the adder; a transmission amplifier that amplifies the output of the modulator; a demodulator that demodulates the output of the transmission amplifier; a variable length delay circuit that delays the input signal; a subtracter that takes the difference between the output of the long delay circuit and the output of the demodulator;
an adaptation circuit that updates the contents of the memory using the output of the subtracter; a differentiation circuit that time-differentiates the output of the variable length delay circuit; and a differentiation circuit that multiplies the sign of the output of the differentiation circuit by the output of the subtracter. a multiplier;
With a delay compensation type adaptive predistorter, comprising: a low-pass filter that integrates the output of the multiplier; and a delay control circuit that corrects the amount of delay of the variable-length delay circuit using the output of the low-pass filter. The above problem is solved by the transmitter.

(作用) 遅延量を適応的に補償するには現時点での遅延
量が進みすぎなのか遅れすぎなのかを知る必要が
ある。本発明の装置は送信増幅器の非線形歪と遅
延量との両方を復調器出力を用いて補償しなくて
はならない。その為には非線形歪と遅延誤差によ
り生ずる歪の性質の違いを考慮する必要がある。
非線形歪は信号の振幅の関数であり入力信号の振
幅が一定ならば常に同じ歪を発生する。これに対
して遅延の誤差による歪は入力信号の振幅は一定
でもその時点での時間微分の値が異なれば異なつ
たものとなる。第4図にその様子を示す。第4図
aは入力信号と遅れて来た復調器出力を比較する
場合である。この場合、信号値が増加中であるな
らば入力信号の方が大きくなる。逆に入力信号に
遅延を入れすぎて入力信号が復調器出力よりも遅
れてしまつた場合の例を第4図bに示す。この場
合には信号値が増加中の時に入力信号の方が小さ
くなる。信号値が減少中の時にはこの逆になる。
この事は入力信号の振幅にはよらない現象であ
る。従つて誤差信号を入力信号の時間微分で割れ
ば入力信号と復調器出力の遅延時間差を求めるこ
とができる。しかしながら入力信号と復調器出力
の誤差には送信増幅器の歪も同時に含まれている
ので単一の観測値からは正しく歪を求めることが
できない。この送信増幅器の歪の影響をのぞく為
に割算器出力をローパスフイルターで平均化して
遅延量を増減するように制御すれば良いのであ
る。現実問題としては割算器は回路が複雑でかつ
0で割るとオーバーフローを起こしてしまうとい
う問題があるので時間微分値そのもので割るので
はなく時間微分の符号で割るようにする。こうす
れば誤差信号の符号を変えるだけで良いので回路
が著しく簡単になる。符号のみで割るという操作
は絶対値が変化しないので符号を乗算することに
等しい。従つて本発明では符号を乗算するという
表現を採用する。
(Operation) In order to adaptively compensate for the amount of delay, it is necessary to know whether the amount of delay at present is too advanced or too late. The device of the present invention must compensate for both the nonlinear distortion and delay of the transmitting amplifier using the demodulator output. For this purpose, it is necessary to consider the difference in the characteristics of distortion caused by nonlinear distortion and delay error.
Nonlinear distortion is a function of signal amplitude, and if the input signal amplitude is constant, the same distortion will always occur. On the other hand, distortion due to delay errors will vary if the time differential value at that point in time differs even if the amplitude of the input signal is constant. Figure 4 shows the situation. FIG. 4a shows a case where the input signal and the delayed demodulator output are compared. In this case, if the signal value is increasing, the input signal will be larger. On the other hand, an example in which too much delay is added to the input signal so that the input signal lags behind the output of the demodulator is shown in FIG. 4b. In this case, the input signal becomes smaller when the signal value is increasing. The opposite is true when the signal value is decreasing.
This phenomenon does not depend on the amplitude of the input signal. Therefore, by dividing the error signal by the time differential of the input signal, the delay time difference between the input signal and the demodulator output can be obtained. However, since the error between the input signal and the demodulator output also includes the distortion of the transmission amplifier, it is not possible to accurately determine the distortion from a single observed value. In order to eliminate the influence of distortion of the transmission amplifier, the output of the divider can be averaged with a low-pass filter and the amount of delay can be controlled to increase or decrease. As a practical matter, the circuit of the divider is complex and there is a problem that dividing by 0 will cause an overflow, so instead of dividing by the time differential value itself, divide by the sign of the time differential. This greatly simplifies the circuit because it is only necessary to change the sign of the error signal. Dividing only by the sign does not change the absolute value, so it is equivalent to multiplying by the sign. Therefore, the present invention adopts the expression of multiplying by signs.

(実施例) 次に図面を参照して本発明について詳細に説明
する。まず従来のアダプテイブプリデイストータ
ーについて説明する。第2図にはこの基本ブロツ
ク図を示す。入力端子200からは送信信号がデ
イジタル信号で入力される。RAM201には補
正すべき歪量が記憶されている。この値の例を第
3図に示す。そもそもプリデイストーターは第3
図aの様な飽和特性を有する送信増幅器を第3図
bの様な特性を有する送信増幅器の様に動作させ
る為に入力信号を歪ませて送信増幅器に入力する
ものである。例えば、第3図のA点に対応する直
線増幅出力をaの特性をもつ送信増幅器で得るに
は、Aの入力信号に対してΔAを加えて送信増幅
器に入力すればBの出力(直線増幅出力)が得ら
れ、送信増幅器の歪が除去される。RAM201
の値は加算器202で入力信号に加算され、変調
器203で変調される送信増幅器204に入力さ
れる。送信増幅器204の出力は端子210から
出力されると共に復調器205で復調される。復
調器205の出力は入力信号から減算器206で
減算され、復調器の出力が大きすぎる時には
RAM201の内容を減らし、逆に小さすぎる時
にはRAM201の内容を増やすよう適応化回路
207で制御する。これはRAM201の出力に
減算器206の出力を加算器(適応化回路20
7)で加え、RAM201に書込むことで簡単に
実現できる。入力信号と復調器205の出力が等
しくなれば減算器206の出力はOとなりRAM
201の内容は一定値となる。
(Example) Next, the present invention will be described in detail with reference to the drawings. First, a conventional adaptive predistorter will be explained. FIG. 2 shows this basic block diagram. A transmission signal is input as a digital signal from the input terminal 200. The RAM 201 stores the amount of distortion to be corrected. An example of this value is shown in FIG. In the first place, Preday Stotor is the third
In order to operate a transmission amplifier having saturation characteristics as shown in FIG. 3A like a transmission amplifier having characteristics as shown in FIG. For example, to obtain the linear amplified output corresponding to point A in Figure 3 using a transmitting amplifier with characteristics a, add ΔA to the input signal of A and input it to the transmitting amplifier, and the output of B (linear amplified output) is obtained and the distortion of the transmitting amplifier is removed. RAM201
The value of is added to the input signal by an adder 202 and input to a transmission amplifier 204 where it is modulated by a modulator 203. The output of transmission amplifier 204 is output from terminal 210 and demodulated by demodulator 205 . The output of the demodulator 205 is subtracted from the input signal by a subtracter 206, and when the output of the demodulator is too large,
The adaptation circuit 207 controls the content of the RAM 201 to be reduced, and conversely to increase the content of the RAM 201 if it is too small. This is an adder (adaptation circuit 20
In addition to 7), this can be easily achieved by writing to the RAM 201. When the input signal and the output of the demodulator 205 become equal, the output of the subtracter 206 becomes O and the RAM
The contents of 201 are constant values.

しかしながら実際の回路では変調器203、送
信増幅器204、復調器205を信号が通過する
間に遅延が生じる。そうすると入力信号を同じだ
け遅らせて減算器206に入力しないと正しく送
信増幅器204による歪を補償することができな
い。本発明においては第1図の様な構成によつて
入力信号を自動的に最適時間だけ遅延させる回路
を付加し、この問題を解決している。
However, in an actual circuit, a delay occurs while the signal passes through the modulator 203, transmission amplifier 204, and demodulator 205. In this case, the distortion caused by the transmission amplifier 204 cannot be correctly compensated unless the input signal is delayed by the same amount and inputted to the subtracter 206. In the present invention, this problem is solved by adding a circuit that automatically delays the input signal by an optimum time using the configuration shown in FIG.

入力端子100から入力された信号は加算器1
02でRAM101からの補正量を加えられ、変
調器103で変調されて送信増幅器104に入力
される。送信増幅器104の出力は端子120か
ら出力されると共に復調器105で復調される。
復調器105の出力は減算器106に加えられ
る。減算器106は、可変長遅延回路112で遅
延させられた入力信号から復調器105の出力を
減じ、減算値を適応化回路107に加える。適応
化回路107は復調器105の出力が大き過ぎる
ときにはRAM101の内容を減らし、逆に小さ
過ぎるときにはRAM101の内容を増やすよう
に作用する。適応化回路107は、加算器からな
り、RAM101の出力に減算器106の出力を
その加算器で加え、RAM101に書込む。可変
長遅延回路112での遅延量が正しくないと減算
器106の出力には送信増幅器104による歪と
遅延誤差による歪が混在したものとなる。遅延誤
差を除く為に、微分回路108で可変長遅延回路
112の出力を微分し、微分回路108の出力の
符号を減算器106の出力に乗算器109で乗算
する。こうすることにより乗算器109の出力は
可変長遅延回路112の遅延量が不足していると
(第4図aの状態)正の値になり、逆に大きすぎ
ると(第4図bの状態)負の値になる。したがつ
て本実施例では、ローパスフイルター110で送
信増幅器104の歪の影響を取除き、遅延制御回
路111でローパスフイルター110の出力が正
ならば可変長遅延回路112の遅延量を増やし負
ならば可変長遅延回路112の遅延量を減らすよ
うに、可変長遅延回路112の遅延量を制御し、
遅延誤差による歪を自動的に最小にする。微分回
路108はレジスタ121で可変長遅延回路11
2の出力を微小時間だけ遅延させ、可変長遅延回
路112の出力との差を取ることにより求められ
る。可変長遅延回路112はシフトレジスタを何
段か用いれば簡単にできる。レジスタ121は、
可変長遅延回路112がシフトレジスタであれ
ば、可変長遅延回路のシフトレジスタと一体的な
回路を用いることができる。
The signal input from input terminal 100 is sent to adder 1
At step 02, the correction amount from the RAM 101 is added to the signal, modulated by the modulator 103, and input to the transmission amplifier 104. The output of transmission amplifier 104 is output from terminal 120 and demodulated by demodulator 105 .
The output of demodulator 105 is applied to subtractor 106. Subtractor 106 subtracts the output of demodulator 105 from the input signal delayed by variable length delay circuit 112 and applies the subtracted value to adaptation circuit 107 . Adaptation circuit 107 operates to reduce the contents of RAM 101 when the output of demodulator 105 is too large, and to increase the contents of RAM 101 when it is too small. The adaptation circuit 107 consists of an adder, which adds the output of the subtracter 106 to the output of the RAM 101, and writes the result to the RAM 101. If the amount of delay in the variable length delay circuit 112 is incorrect, the output of the subtracter 106 will contain a mixture of distortion caused by the transmission amplifier 104 and distortion caused by the delay error. In order to remove delay errors, a differentiating circuit 108 differentiates the output of the variable length delay circuit 112, and a multiplier 109 multiplies the output of the subtracter 106 by the sign of the output of the differentiating circuit 108. By doing this, the output of the multiplier 109 becomes a positive value when the delay amount of the variable length delay circuit 112 is insufficient (the state shown in FIG. 4 a), and conversely, when it is too large (the state shown in FIG. 4 b) ) becomes a negative value. Therefore, in this embodiment, the low-pass filter 110 removes the influence of distortion of the transmission amplifier 104, and the delay control circuit 111 increases the delay amount of the variable length delay circuit 112 if the output of the low-pass filter 110 is positive, and increases the delay amount of the variable length delay circuit 112 if the output is negative. controlling the amount of delay of the variable length delay circuit 112 so as to reduce the amount of delay of the variable length delay circuit 112;
Automatically minimizes distortion due to delay errors. Differential circuit 108 is connected to variable length delay circuit 11 by register 121.
It is obtained by delaying the output of the variable length delay circuit 112 by a minute amount of time and taking the difference between the output of the variable length delay circuit 112 and the output of the variable length delay circuit 112. The variable length delay circuit 112 can be easily constructed by using several stages of shift registers. The register 121 is
If the variable length delay circuit 112 is a shift register, a circuit integrated with the shift register of the variable length delay circuit can be used.

(発明の効果) 以上に詳細に述べたように、本発明によれば、
変調器、送信増幅器および復調器からなる回路に
於ける遅延による直線性の劣化を自動的に補正す
る遅延補償型アダプテイブプリデイストーター付
の送信機を提供することができる。
(Effects of the Invention) As described in detail above, according to the present invention,
It is possible to provide a transmitter with a delay compensation type adaptive predistorter that automatically corrects linearity deterioration due to delay in a circuit including a modulator, a transmission amplifier, and a demodulator.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す回路ブロツク
図、第2図は従来のアダプテイブプリデイストー
ターを示す回路ブロツク図、第3図はプリデイス
トーターの原理を示す図、第4図は遅延誤差の影
響を示す模式的な波形図である。 101……メモリー、102……加算器、10
3……変調器、104……送信増幅器、105…
…復調器、106……減算器、107……適応化
回路、108……微分回路、109……乗算器、
110……ローパスフイルター、111……遅延
制御回路、112……可変長遅延回路。
Fig. 1 is a circuit block diagram showing an embodiment of the present invention, Fig. 2 is a circuit block diagram showing a conventional adaptive predistorter, Fig. 3 is a diagram showing the principle of the predistorter, and Fig. 4. is a schematic waveform diagram showing the influence of delay error. 101...Memory, 102...Adder, 10
3...Modulator, 104...Transmission amplifier, 105...
... Demodulator, 106 ... Subtractor, 107 ... Adaptation circuit, 108 ... Differentiation circuit, 109 ... Multiplier,
110...Low pass filter, 111...Delay control circuit, 112...Variable length delay circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 無線器の送信増幅器の歪を入力信号を歪ませ
ることにより補償し、かつその補償量を前記送信
増幅器の出力と前記入力信号とを比較することに
より適応的に変化させるアダプテイブプリデイス
トーター付送信機において、前記入力信号のそれ
ぞれの値に対応した歪量を記憶するメモリーと、
このメモリーの出力と前記入力信号とを加算する
加算器と、この加算器の出力を変調して前記送信
増幅器に加える変調器と、前記送信増幅器出力を
復調する復調器と、前記入力信号を遅延させる可
変長遅延回路と、この可変長遅延回路の出力と前
記復調器出力との差を取る減算器と、この減算器
の出力を用いて前記メモリーの内容を更新する適
応化回路と、前記可変長遅延回路の出力を時間微
分する微分回路と、この微分回路の出力の符号と
前記減算器出力を乗算する乗算器と、この乗算器
の出力を積分するローパスフイルターと、このロ
ーパスフイルターの出力により前記可変長遅延回
路の遅延量を補正する遅延制御回路とを有するこ
とを特徴とした遅延補償型アダプテイブプリデイ
ストーター付送信機。
1. An adaptive predistorter that compensates for distortion in a transmitting amplifier of a radio device by distorting an input signal, and adaptively changes the amount of compensation by comparing the output of the transmitting amplifier with the input signal. a memory for storing an amount of distortion corresponding to each value of the input signal;
an adder that adds the output of this memory and the input signal; a modulator that modulates the output of the adder and applies it to the transmission amplifier; a demodulator that demodulates the output of the transmission amplifier; and a demodulator that delays the input signal. a subtracter that takes the difference between the output of the variable length delay circuit and the output of the demodulator, an adaptation circuit that updates the contents of the memory using the output of the subtracter; A differentiating circuit that time-differentiates the output of the long delay circuit, a multiplier that multiplies the sign of the output of this differentiating circuit by the output of the subtracter, a low-pass filter that integrates the output of this multiplier, and the output of this low-pass filter. A transmitter with a delay compensation type adaptive predistorter, comprising a delay control circuit that corrects the amount of delay of the variable length delay circuit.
JP62042103A 1987-02-24 1987-02-24 Transmitter with delay compensation type adaptive predistorter Granted JPS63208330A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62042103A JPS63208330A (en) 1987-02-24 1987-02-24 Transmitter with delay compensation type adaptive predistorter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62042103A JPS63208330A (en) 1987-02-24 1987-02-24 Transmitter with delay compensation type adaptive predistorter

Publications (2)

Publication Number Publication Date
JPS63208330A JPS63208330A (en) 1988-08-29
JPH0531330B2 true JPH0531330B2 (en) 1993-05-12

Family

ID=12626643

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62042103A Granted JPS63208330A (en) 1987-02-24 1987-02-24 Transmitter with delay compensation type adaptive predistorter

Country Status (1)

Country Link
JP (1) JPS63208330A (en)

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JPWO2004045067A1 (en) * 2002-11-14 2006-03-16 株式会社日立国際電気 Distortion compensation circuit, distortion compensation signal generation method, and power amplifier
JP2007129744A (en) * 2006-12-13 2007-05-24 Fujitsu Ltd Adaptive controller

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Publication number Priority date Publication date Assignee Title
JP2513289B2 (en) * 1989-01-06 1996-07-03 日本電気株式会社 Modulator
WO2001069778A2 (en) * 2000-03-16 2001-09-20 Rohde & Schwarz Gmbh & Co. Kg Method for determining the parameters of an n-gate
US6949976B2 (en) 2002-10-10 2005-09-27 Fujitsu Limited Distortion compensating amplifier device, amplifier system, and wireless base station
JP4641715B2 (en) 2003-11-14 2011-03-02 富士通株式会社 Distortion compensation apparatus and radio base station
JP4961661B2 (en) * 2004-09-10 2012-06-27 株式会社日立製作所 Digital predistortion type transmitter and radio base station

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2004045067A1 (en) * 2002-11-14 2006-03-16 株式会社日立国際電気 Distortion compensation circuit, distortion compensation signal generation method, and power amplifier
JP4657920B2 (en) * 2002-11-14 2011-03-23 株式会社日立国際電気 Distortion compensation circuit, distortion compensation signal generation method, and power amplifier
JP2007129744A (en) * 2006-12-13 2007-05-24 Fujitsu Ltd Adaptive controller
JP4480711B2 (en) * 2006-12-13 2010-06-16 富士通株式会社 Adaptive controller

Also Published As

Publication number Publication date
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