JPH0530113B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an address code mixing device in a receiving device, and particularly contributes to preventing unauthorized copying by a terminal receiving device for paid information such as paid broadcasting. This invention relates to an address code mixing device.

[Prior Art] Currently, information provision services are being provided using paid communication systems, such as paid broadcasting on CATV and other paid information provision using personal computer communications. In these communication systems, a terminal receiving device unique to the communication system is provided that allows information to be provided only to members who have paid a predetermined fee.
Information is not available to anyone other than members.

However, in the above case, the information obtained by a legitimate member may actually be provided to a third party by the member using a playback device, and it is important not to allow such unauthorized use to occur. The thing to keep is
It is clear that this will result in a major economic loss for pay TV operators.

Therefore, in the past, measures such as inserting a copy prohibition code into the information data or including a screen displaying the unique address number assigned to the terminal in the video signal were taken to prevent the copying of paid information. I was trying to prevent it.

However, the conventional means for preventing copying mentioned above can generally be easily removed technically. That is, by using an easily available device such as an oscilloscope, it is possible to relatively easily remove the screen containing the copy prohibition code signal and the address number of the terminal.

Therefore, in order to solve the above-mentioned problems, the present applicant proposed an address code mixing method and mixing device in Japanese Patent Application No. 62-238763. According to this address code mixing device, address information unique to the terminal device that received the signal is mixed into the video signal, and furthermore, this address information cannot be easily separated from the signal. Therefore, in the event that an unauthorized copy is made, the terminal device that made the copy can be quickly and easily discovered, thereby making it possible to prevent unauthorized copying.

[Problem to be solved by the invention] By the way, in the address code mixing device,
Since an oscillation signal of a predetermined frequency is generated and address information is obtained by performing frequency modulation on this signal, filter processing is required, and the entire structure is based on analog technology. However, on the other hand, there is also a strong desire for digitization of circuits based on demands for greater integration of circuits and miniaturization of devices.

An object of the present invention is to provide an address code mixing device that enables digital processing and is configured entirely as a digital circuit, thereby achieving the use of an IC in the device and effectively preventing unauthorized use of paid broadcasting services. .

[Means for Solving the Problems] An address code mixing device in a terminal receiving device capable of receiving a pay broadcast service according to the present invention includes a storage means for storing a unique address code assigned to the terminal receiving device, and a television. an initialization processing means that generates an initial value in response to a synchronization signal of an address signal, a PN code generation means that generates a PN code based on the initial value, and an address code that accesses the storage means based on the PN code, and It consists of address code generating means that generates each bit in synchronization with the horizontal period of the television signal, and address code mixing means that mixes the address code with the television signal.

[Operation] According to the above address code mixing device, the horizontal period of a predetermined field of the television signal into which each bit of the address code is mixed is pseudo-randomly selected by the initialization processing means and the PN code generation means. In this way, each bit of the address code can be inserted in digital form on the front porch of the selected horizontal period, so that the television signal output from the terminal receiver always includes the terminal receiver. The address code assigned to the address code is mixed in.

[Embodiments] Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows a terminal receiving device including an address code mixing device according to the present invention, and this terminal receiving device is a receiving device for a terminal device that receives a pay broadcast signal. In FIG. 1, 1 is an address code mixing device according to the present invention, 2 is a TV tuner,
3 is a descrambler for restoring scrambled television signals used in CATV, etc.; 4 is a video signal amplification circuit; and 5 is a video signal output terminal. The address code mixing device 1 and the descrambler 3 are, as shown by block 100,
It is physically sealed and integrated so that it is difficult to open. This is accomplished by incorporating them into the same package or by forming them on the same chip.

In the above configuration, the video and audio signals, that is, the television signals, scrambled and transmitted on the transmitting side are received by the TV tuner 2, and then supplied to the descrambler 3 and the address code mixing device 1. The descrambler 3 removes the scramble, extracts normal video and audio signals, and outputs them. The descrambled normal video and audio signals are input to the address code mixing device 1. The address code mixing device 1 mixes a unique address code assigned to the terminal device based on the synchronization signal into a video signal in the form of a digital signal, and then sends the video signal to the video signal amplification circuit 4. Therefore, according to this configuration, the address code mixing device 1 is included in the composite video signal supplied to the video signal amplification circuit 4.
This means that the address code prepared within is always mixed in. The television signal output from output terminal 5 is then displayed on a CRT or
Used for recording with VTR etc.

Next, a specific configuration of the address code mixing device 1 and a method for mixing an address code into a video signal will be explained.

First, a description will be given of the unique address code assigned to a terminal device, and the location and manner in which it is mixed. The number of bits in the address code is set to 64 bits in consideration of actual operation. In other words, considering the current social and industrial conditions, the number of bits required to represent the manufacturer's classification, device type, and terminal device manufacturing code is 20 bits (approximately 1 million bits). company), 10 bits (approximately 1000
It is sufficient to allocate 34 bits (for about 16 billion units) for each type of address code (for each type), so an address code of at least 64 bits in total is sufficient. Also, the address code is given as a 64-bit “0” or “1”.
The insertion position of the pulse corresponding to “1” in the video signal is determined by the descrambler 3 as shown in FIG.
In the n-th horizontal period _{of the} normal composite video signal φ ₁₁ , which is _the output signal _of
~t ₁₀₂ (e.g. front porch t ₁₀₁ position)
is possible. In the example below, during the retrace period,
The case of inserting at position _t101 will be explained. Regarding the address code, it is assumed that a narrow pulse with a pulse width of 0.3 μs, for example, is inserted at the position _t101 in correspondence with "1", and nothing is inserted for "0".

If the address code for the terminal device is 64 bits as described above, it is only necessary to specify 64 points in the horizontal period of the video signal in order to mix the address code, but if these specified points are fixed and the address is continuously If we mix in each bit of the code,
There is a risk that an address code mixed in by an unauthorized user may be easily discovered. Therefore, in the address code mixing device 1 according to the present invention, as will be described later, the horizontal periods at 64 locations in which each bit forming the address code is inserted are pseudo-randomly changed. That is, the address code mixing device 1 uses, for example, an 8-bit shift register to be described later.
2 ⁸ −1 (255) bit m-sequence PN code (Psudo
-noise code) from the beginning of the 255-bit PN code as shown in Figures 6 and 10.
Correlate the 64 “1” parts with the horizontal period,
It has a circuit configuration in which the above-mentioned pulse is mixed into the horizontal period corresponding to "1" among the address codes a ₁ to a ₆₄ among the 64 horizontal periods corresponding to "1".

Next, the configuration of the address code mixing device 1 will be explained with reference to FIG. 6 is a synchronization signal separation circuit,
Various necessary timing signals such as a horizontal synchronizing signal (hereinafter referred to as H pulse), a vertical synchronizing signal (hereinafter referred to as V pulse), and a horizontal blanking signal are separated from the composite video signal supplied from the TV tuner 2 and output. Reference numeral 7 denotes an initialization processing circuit, which inputs the V pulse from the synchronization signal separation circuit 6 and sets an initial value for each field in synchronization with this. This initial value consists of 8 bits, and one of the 255 values from 00000001 to 11111111 is selected. The initial values will be expressed as d ₁ to d ₈ below.
8 is a PN code generation circuit which inputs the initial values d ₁ to d ₈ from the initialization processing circuit 7 at the start of the field and also inputs the H pulse from the synchronization signal separation circuit 6, and generates 255 8-bit patterns as described above. Signal H
Generated in synchronization with the pulse, a 255-bit PN code is created and output.

Here, an example of a known PN code generation circuit 8 will be briefly described based on FIGS. 2 and 3. As shown in FIG. 2, the PN code generation circuit 8 includes a shift register 80 and three exclusive OR gates 81, 82, 83.
It consists of The shift register 80 is ²⁰ to ²⁷
The exclusive OR gate 81 has 8 bits of
The bit outputs of 2 ³ and 2 ⁷ are input, the bit outputs of 2 ¹ and 2 ² are input to the exclusive OR gate 82, and the exclusive OR gates 81 and 8 are input to the exclusive OR gate 83.
The outputs of the exclusive OR gate 83 are connected to the input end of the shift register 80 so as to be fed back to the input end of the shift register 80. In this configuration, if the 8-bit initial values d ₁ to _{d 8} from the initialization processing circuit 7 are loaded into the shift register 80 and clocked 255 times with the H pulse given from the synchronization signal separation circuit 6, the shift register 80 is 2 as ⁷ bit output
A 255-bit PN code can be obtained. now,
Assuming that the initial value is 10111001 as shown in FIGS. 2 and 3, the state of the 8 bits in the shift register 80 changes from top to bottom as shown in FIG. Shift sequentially toward As a result, a bit string shown in columns for the ²⁷ bits of the shift register 80 in FIG. 3 is generated at the output terminal ( ²⁷ bits) of the shift register 80. After the 256th clock cycle, the internal state of shift register 80 returns to its initial state. Regarding the shift register 80,
The input type may be a parallel type or a serial type, but the output type must be a parallel type.

Returning again to FIG. 1, the explanation of the configuration will be continued. 9 is a mixed gate forming circuit. The mixing gate forming circuit 9 receives the V pulse from the synchronization signal separation circuit 6, the initial value from the initialization processing circuit 7, and the PN code generation circuit 8.
Input each PN code from . Figure 6 c, d
As shown in FIG. 6, a pulse signal φ ₁₃ (FIG. 6 d) representing a PN code (FIG. 6 d) synchronized with the horizontal period of the television signal is applied from the PN code generating circuit 8 to the mixing gate forming circuit 9. . Based on this pulse signal φ ₁₃ , the mixing gate forming circuit 9 generates a pulse signal φ ₁₂ in response to a change in its state.
A circuit section that generates a gate pulse _φ14 in response to a rise from "0" to "1" is included. The gate pulse _φ14 is a pulse signal for superimposing each bit of the address code at _t101 during the horizontal period of the composite video signal in correspondence with "1" of the PN code. A mixed gate forming circuit having the above function is, for example, 3
Since it is realized with one input AND gate and can be easily manufactured by a digital circuit engineer, a detailed explanation of the configuration will be omitted.

The gate pulse φ ₁₄ outputted from the mixing gate forming circuit 9 is supplied to the address signal generating circuit 10 and the address code mixing circuit 11 .

The address signal generation circuit 10 is constituted by an address counter, and receives the V pulse from the synchronization signal separation circuit 6 in addition to the gate pulse _φ14 . This address signal generating circuit 10 counts gate pulses _φ14 for each field using a counter, and generates an address signal in synchronization with the horizontal period of the television signal. This address signal is supplied to the address code mixing circuit 11.

A specific configuration of the address code mixing circuit 11 is shown in FIG. Address code mixing circuit 11
consists of an address ROM 12 that stores the 64-bit address code assigned to the terminal device, an OR gate 13 that inputs the output of the address ROM 12 to one input terminal, and a pulse with a pulse width of 0.3 μs that receives the output of the OR gate 13. It consists of a pulse generator 14 that generates , and a switching gate 15 that has three input terminals and inputs the output of the pulse generator 14 to one input terminal. The other two input terminals of the switching gate 15 are supplied with the composite video signal φ ₁₁ from the descrambler 3 and the gate pulse φ ₁₄ and pulse signal φ ₁₂ from the mixing gate forming circuit 9. The output terminal of the switching gate 15 is connected to the input terminal of the video signal amplification circuit 4 as the output terminal of the address code mixing circuit 11. This switching gate 15 is an analog gate that allows the composite video signal φ ₁₁ to pass through without distortion, and includes a clamp circuit and the like for matching the levels of the output of the descrambler 3 and the output of the pulse generator 14 . Further, the other input terminal of the OR gate 13 is connected to the initialization processing circuit 7.
Initial values d ₁ to _{d 8} output from are input.

Next, a method of mixing an address code with the above configuration will be explained. As described above, each bit of the 64-bit address code is mixed into the front porch of an appropriately selected horizontal period of the composite video signal _φ11 . FIG. 7 shows a portion of a television signal (same as the composite video signal _φ11 ) in units of fields. In Figure 7, y _o-1 , y _o , y _o+1 , y _o+2 ,
..., y _l-1 , y _l , y _l+1 each represent one field. In this example, one field y _o+2 ,
Address codes a ₁ to a ₆₄ are mixed in y _l+1 , . In this case, the fields y _o+2 , y _l-1 ,
The signal φ ₁₆ shown in FIG. 8 is mixed into the two fields y _o , y _{l - 1} of ..., and the signal φ 16 shown in FIG. A signal _φ17 is mixed in. The signal φ ₁₆ inserts a start bit “10” and a stop bit “10” in 11 consecutive horizontal periods n ₀ to n ₁₀ in fields yo _and y _l-1 , and changes to “0” from n ₂ to n ₉ . ” is a continuous 8-bit signal. This signal φ ₁₆ corresponds to the address code a ₁ ~
It is used when detecting _a64 , and is a start signal to notify that there is an address code after this signal _φ16 . The signal φ ₁₇ is
A start bit "10" and a stop bit "10" are inserted in 11 consecutive horizontal periods k ₀ to k ₁₀ in fields y _o+1 and y _l , and the above-mentioned initial value d ₁ is inserted from k ₂ to k ₉ . This is a signal mixed with ~ _d8 . This signal _φ17 is also used for address code detection and is a set signal for setting the shift register on the detection side.

Each bit of the signals φ ₁₆ and φ ₁₇ is inserted into the front porch t ₁₀₁ of each horizontal retrace period in the same way as the address code.

In this example, address codes a ₁ to _{a 64} mixed into fields y _o+2 and y _l+ 1 are mixed into roughly the first half of each field. Here, the 255 mentioned above
The correspondence between the m-series PN code of bits, the horizontal scanning line number, and the address codes _a1 to _a64 will be explained with reference to FIG. In FIG. 10, from the top, the horizontal scanning line number, the bit number of the PN code, the PN code, and the address code are shown, respectively. In this example,
18H corresponds to the 1st bit of the PN code, and the 272nd H (that is, the meaning of 9H in the next field) corresponds to the 255th bit. However, the correspondence between horizontal scanning line numbers and PN codes is arbitrary. Further, there is no problem even if the number of bits of the PN code is smaller than the number of horizontal scanning lines of one field. Shown in Figure 10
When each bit a1 to _a64 of a 64-bit address code is made to correspond to " ₁ " of the PN code, the number of bits k in the figure becomes around 128H. “0” in PN code,
Since the distribution of “1” is uniform and almost equal, the above k is approximately in the middle of the sequence 1 to 255, and therefore k
+17 is also close to 145H. When transmitting a 64-bit address code in this way, 1
It is not necessary to use all 272H, which is equivalent to one field, and in fact only about half is enough. 10th
In the figure, the pulses of the address code bits a ₁ , a ₂ , a ₃ , ... are inserted in correspondence with the horizontal scanning lines where the PN code bits 18H, 21H, 22H, ... become "1". go. The m-series PN code synchronized with the horizontal scanning line is created by clocking with the ^H pulse in the shift register 80 of FIG. 272H after (k+17)H
The horizontal scan line up to the eye is ignored.

The scrambled composite video signal received by the TV tuner 2 is descrambled by the descrambler 3 and is supplied to the switching gate 15 of the address code mixing circuit 11 as a normal composite video signal φ ₁₁ . In the synchronization signal separation circuit 6, H pulse and V
A pulse is output, and the initialization processing circuit 7 is set to the initial value.
d ₁ to _{d 8} are applied to the OR gate 13 of the address code mixing circuit 11 and the PN code generation circuit 8. The PN code generating circuit 8 generates a PN code using the initial values _d1 to _d8 and the H pulse clock, and the mixed gate forming circuit 9 generates a gate pulse at a portion corresponding to "1" in each bit of the PN code. Generates _φ14 . The gate pulse generation position corresponds to the front porch of the composite video signal. This gate pulse φ ₁₄ is supplied to the switching gate 15 of the address code mixing circuit 11 and the address signal generating circuit 10 . Further, as shown in FIG. 4, the aforementioned signal φ ₁₂ is supplied to the switching gate 15 under certain conditions along with the gate pulse φ ₁₄ on the same line.

In the address code mixing circuit 11, the switching gate 15 mixes signals φ ₁₆ , φ ₁₇ and address codes a ₁ to a ₆₄ into a predetermined field of the composite video signal φ ₁₁ (television signal) as shown in FIG. urge Regarding the fields y _o and y _l-1 , a signal φ ₁₆ is sent from the initialization processing circuit 7 during the horizontal period n ₀ to n ₁₀ (Fig. 8).
and a signal φ ₁₂ is output from the mixing gate forming circuit 9, which is applied to the switching gate 15 via the OR gate 13 and the pulse generator 14. Then, because they are synchronized with each other, the horizontal periods of fields y _o and y _l-1 of the composite video signal φ ₁₁
The signal _φ16 is mixed into _{the front porch of n0 to n10 .} Regarding the fields y _o+1 and y _l , the mixing gate forming circuit 9 outputs the signal φ ₁₂ during the horizontal period k ₀ to _{k 10} , and the initialization processing circuit 7 outputs the signal φ 12.
The initial value is passed through the OR gate 13 and the pulse generator 14.
d ₁ to _{d 8} are generated and applied to these switching gates 15. As a result, the signal φ ₁₇ (FIG. 9) is mixed into the front porch of the horizontal period k ₀ to _{k 10} of the fields y _o+1 and y _l of the composite video signal φ ₁₁ .

Next, address code mixing in fields y _o+2 and y _l+1 will be explained. An address signal generating circuit 10 generates an address signal in response to a gate pulse φ ₁₄ applied from a mixed gate forming circuit 9, and supplies this address signal to an address ROM 12. Specifically, the address signal generating circuit 10 is, for example, a 6-bit binary counter, and specifies an address within the address ROM 12 using 6 bits. The address signal generating circuit 10 clears each field with a V pulse and counts gate pulses _φ14 . for example,
In field y _o+2 , an address signal is generated in synchronization with each gate pulse while counting gate pulses based on the gate pulse φ ₁₄ depending on the presence or absence of "1" of the PN code from the position of the signal φ ₁₂ of 18H. The circuit 10 sequentially outputs address signals from 000000 to 111111. At address ROM12
Since 000000 corresponds to a ₁ , 111111 corresponds to a ₆₄ , and the values in between correspond to a ₂ to a ₆₃ , the stored contents are read out in accordance with the output of the address signal generation circuit 10 synchronized with the gate pulse φ ₁₄ . . Therefore, the address is
The readout of the ROM 12 changes. Address ROM
When the output of 12 is “1”, OR gate 13,
A predetermined high level signal is applied to the switching gate 15 via the pulse generator 14, and a 0.3 μs pulse is inserted into the front porch _t101 as described above. In this way, address codes a ₁ to a ₆₄ are mixed into each of the front porches of 64 horizontal periods that are pseudo-randomly selected in fields y _o+2 and y _l+1 . Note that if the contents of address codes a ₁ to a ₆₄ are "0", no pulse exists.

Also, the field containing the address y _o+2 ,
Addresses in other fields other than y _l+1 ,...
Regarding the operation of the ROM 12, as shown in FIG. 4, an output inhibit signal φ ₁₈ is supplied from the initialization processing circuit 7 to the output control (read inhibit or chip enable) terminal of the address ROM 12. This configuration prevents address codes a ₁ to a ₆₄ from being mixed into the other fields.

As described above, in the switching gate 15 of the address code mixing circuit 11, the front porch t ₁₀₁ of 64 pseudo-randomly selected horizontal periods in the fields y _o+2 , y _l+1 , . . . of the composite video signal φ ₁₁ is used. Each bit of the address code is mixed into the video signal, and then the video signal is supplied to the video signal amplification circuit 4. Therefore, the address ROM 12 is always included in a predetermined field of the video signal output from the video signal amplification circuit 4.
This means that the address code assigned to the terminal device stored in the address code is mixed in.

On the other hand, when detecting the above address code from a video signal recorded on a VTR, etc., first detect the start signal _φ16 in the field y _o , and then detect the field containing the address codes _a1 to _a64 . Anticipating the arrival of the field
Initial values d ₁ to _{d 8} are taken in with y _o+1 , the shift register prepared in the detection device is initialized, and the next field y _o+2 is used to shift the shift register from 18H every 1H to generate a PN code. is reproduced, and the address code is detected from the front porch _t101 during the retrace period of the video signal corresponding to the 64 "1"s. Regarding the m-series PN code, “0” in the case of 2 ⁸ −1
Since there are no eight consecutive PN codes, when field y _o is not detected, it is impossible to mistake a part of the PN code of field y _o+2 as a start signal.

In the above description, the pulse width of the pulse mixed into the position of the front porch _t101 was assumed to be 0.3 μs,
The fundamental frequency component of this pulse can be considered to be approximately 3.3/2MHz, so even if it is recorded on a VTR, this fundamental frequency component will not be lost.

The following modifications can be made to the embodiments of the present invention described above. First, it is also possible to omit field y _o+1 and transmit the contents of field y _o+2 next to field y _o . That is, the 8 bits of initial values d ₁ to _{d 8} are inserted into the front porch of the horizontal period corresponding to the first eight "1"s of the PN code, and are then inserted into the front porch of the horizontal period corresponding to the "1" of the subsequent PN code. By including a 64-bit address code as in the example below, the number of fields can be reduced by one field. Further, the interval between the field into which the start signal _φ16 is inserted and the field into which the address code is inserted is arbitrary. Furthermore, the positions of the horizontal periods n ₀ -n ₁₀ and k ₀ -k ₁₀ in which the start signal φ ₁₆ and set signal φ ₁₇ shown in FIGS. 8 and 9 are inserted are also arbitrary.

[Effects of the Invention] As is clear from the above description, according to the present invention, the address code assigned to the pay television terminal device in a horizontal period pseudo-randomly selected in a predetermined field of a television signal is digitally transmitted. Therefore, if an unauthorized copy is made via a terminal device, this terminal device can be quickly, reliably, and easily discovered, suppressing unauthorized use, and preventing the entire digital address code from being copied. , it becomes easy to convert to LSI,
Furthermore, there is an effect that it is difficult to determine the location where the address code is mixed.

[Brief explanation of the drawing]

Fig. 1 is a block circuit diagram showing an embodiment of the address code mixing device according to the present invention, Fig. 2 is a specific circuit diagram of the PN code generation circuit, and Fig. 3 shows the change state of the shift register in the PN code generation circuit. The state change diagram shown in the table, Figure 4 is a specific circuit diagram of the address code mixing circuit, Figure 5 is a waveform diagram to explain the address code insertion position in a composite video signal, and Figure 6 is a waveform diagram between various signals. FIG. 7 is a schematic diagram showing the television signal in units of fields; FIG. 8 is a signal diagram showing the code used as a start signal for detection; FIG. 9 is a waveform diagram to explain the correspondence relationship. A signal diagram showing a code used as a set signal for detection, and FIG. 10 is an explanatory diagram showing the relationship between a horizontal scanning line number, a PN code, and an address code. [Description of symbols] 1... Address code mixing device, 2... TV tuner, 3... Descrambler, 4... Video signal amplification circuit, 7... Initialization processing circuit, 8... PN code generation circuit, 9...Mixing gate formation circuit, 10...Address signal generation circuit, 1
1...Address code mixing circuit, 12...Address ROM.

Claims (1)

[Scope of Claims] 1. A terminal receiving device that outputs a television signal, comprising: a storage means for storing an address code assigned to the terminal receiving device; and an initial value corresponding to a vertical synchronization signal of the television signal. an initialization processing means for generating a PN code; a PN code generating means for generating a PN code based on the initial value; An address code mixing device comprising address code generating means for generating the address code in synchronization with the horizontal period of the television signal, and address code mixing means for mixing each bit of the address code into the television signal.