JPH05300437A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To provide the solid-state image pickup device which can perform image pickup without generating sensitivity difference in first and second fields at the time of image pickup due to an interlace operation. CONSTITUTION:An image part 2 of a vertical CCD 1 is constituted by alternately arranging plural first three-phase CCD forming respective electrodes to receive clocks phi1-phi3 and second three-phase CCD forming respective electrodes to receive the clocks phi1, phi2a and phi3a. Signal charges are stored by forming a potential well under the electrodes to receive the clocks phi1 of the respective CCD at this image part 2, frame transfer is performed by mixing signal charges for the two steps of the different CCD in the first and second fields in the image part 2 before the frame transfer, and the interlace operation is realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image sensor,
In particular, the present invention relates to a solid-state image pickup device in which an image is formed by an interlace operation.

[0002]

2. Description of the Related Art FIGS. 15 and 16 are views for explaining the structure and operation of a conventional frame transfer type solid-state image pickup device using a three-phase CCD as a vertical CCD.
FIG. 16 is a plan view schematically showing the structure, and FIG. 16 is a view schematically showing the potential distribution in the CCD at the cross section of the line XIV-XIV in FIG. 15 at the time of imaging, and the frame transfer type solid The image sensor is a vertical CCD1
And a horizontal CCD 4, the vertical CCD 1 is divided into an image part 2 in a region where light is input and a storage part 3 in a light-shielded region to which signal charges accumulated in the image part 2 are transferred. ing. The areas separated by broken lines are CCs of a plurality of stages that constitute the vertical CCD 1.
One CCD of D, three CCDs 6 for receiving three different clocks for each CCD are provided for each CCD, and electrodes for receiving the same clock are connected by the same wiring.

As shown in these figures, in this solid-state image pickup device, three clocks (clock φ1, clock φ2, clock φ3) are provided to each CCD stage of the image section 2.
And three clocks (clock Ψ1, clock Ψ2, clock Ψ3) are applied to each CCD stage of the storage unit 3. The horizontal CCD 4 is
The signal charges accumulated in the storage unit 3 are received in parallel and transferred in series toward the output unit 5.

The operation will be described below. In the case of imaging by interlace drive, first, in the first field, of the three clocks φ1 to φ3 given to the image section 2, the clock φ1 is set to the high level, the clock φ2 and the clock φ3 are set to the low level, and the clock is set to the clock. The signal charge is accumulated under the electrode to which φ1 is applied. Then, after the end of this accumulation period, when entering the vertical blanking period, the clocks φ1 to φ3 given to the image section 2 are made into three-phase clocks, and the clocks Ψ1 to φ given to the storage section 3 are changed.
By using Ψ3 as a three-phase clock, the signal charges accumulated in the image section 2 are transferred to the storage section 3.
Note that this transfer is called frame transfer, and clock φ1 and clock Ψ1, clock φ2 and clock Ψ2,
The clock φ3 and the clock Ψ3 have the same phase and the same frequency. The clocks φ1 to φ3 and the clock Ψ1 to
Ψ3 have a phase difference of 120 ° with each other. And
After this transfer (frame transfer), the image part 2
Enters the charge accumulation in the second field. At this time, the clock φ2 and the clock φ3 are set to the high level, the clock φ1 is set to the low level, and the signal charges are accumulated under the electrodes to which the clock φ2 and the clock φ3 are applied. Also, during this accumulation period, the signal charges of the first field stored in the storage unit 3 are vertically transferred to the horizontal CCD 4 one CCD at a time, and the signal charges transferred to the horizontal CCD 4 are sequentially output. Transferred to. Then, in the vertical blanking period after the end of charge accumulation in the second field, the image portion 2
The signal charges of the second field stored in the storage unit 3 are transferred to the storage unit 3, the image unit 2 stores the signal charges of the first field again, and the storage unit 3 stores the signal charges obtained in the second field. In the same manner as above, the signal charges are transferred to the horizontal CCD 4 and the signal charges are output. The operation described above is repeated thereafter, and a two-dimensional image is picked up by the interlacing operation.

Next, referring to FIG. 16, the operation of accumulating signal charges in the image section 2 in the first field and the second field will be described in detail.

The shaded area in FIG. 16 shows the accumulated signal charges, the electrode 6 is made of a light-transmissive material such as polysilicon, and light is incident from above the electrode through the electrode. Is becoming In this figure, the clock φ1 becomes high level in the first field, and the potential well is formed under the electrode 6 corresponding to the clock φ1.
In the field, the clock φ2 and the clock φ3 are at high level, a potential well is formed under the electrode 6 corresponding to these, and signal charges are accumulated in this portion. In the image portion 2 in which such a potential distribution is formed, the peak value of the sensitivity potential corresponds to the central portion under the electrode receiving the clock φ1 in the first field, and the clock φ2, clock in the second field. The peak value of the sensitivity potential corresponds between the electrodes receiving φ 3, respectively, and the position of the peak of the sensitivity potential in the first field and the second field is just 0.5 stage in the vertical CCD, that is, the phase is 180. It will be shifted by °, which allows interlaced operation.

Although only the interlace operation has been described here, of course, the solid-state image pickup device can also perform a normal non-interlace operation. At this time, the CCD of a plurality of stages forming the image section 2 can be used. All C
In the CD, signal charges are accumulated under the electrodes receiving the same clock, and the charges are transferred to the storage unit 3 by frame transfer, and the horizontal CCD 4 transfers the signal charges transferred to the storage unit 3 row by row to the outside. Imaging is performed by outputting. As described above, in the conventional frame transfer type solid-state imaging device shown in FIG. 15, it is possible to perform imaging by the interlace operation and the non-interlace operation according to the respective applications by the clock given to the image part 2 and the storage part 3. It has become. It should be noted that the imaging by the interlace drive is generally
It is used to reduce flicker on the screen and improve the image quality. In non-interlaced drive imaging, for example, information on all pixel data is obtained by a single exposure such as an electronic still camera. Used in some cases.

[0008]

The conventional frame transfer type solid-state image pickup device using the three-phase CCD is constructed as described above, and the control clock given to the image section 2 causes a signal to be transmitted between the first field and the second field. The position of the potential well where the charge is accumulated is set to 0.5 with CCD.
By shifting the signal charges by a step, the phase of the signal charges transferred to the storage unit 3 is shifted by 180 ° C., whereby the interlace operation is performed. However, in such a conventional solid-state imaging device, as shown in FIG. 15, the position of the signal charge accumulated in the first field and the second field by the control clock is changed to C
The first field and the second to shift 0.5 steps on the CD
The form of the potential well in which the signal charge is accumulated changes between fields, and as a result, the form of the sensitivity potential obtained between fields also changes, resulting in a difference in sensitivity between the first field and the second field, resulting in interlaced operation. Despite this, there was a problem that flicker (flicker) still occurred on the imaged screen.

The present invention has been made to solve the above problems, and provides a solid-state image pickup device capable of performing image pickup without causing a sensitivity difference between the first field and the second field during the interlacing operation. The purpose is to get.

[0010]

A solid-state image pickup device according to the present invention has a first structure when an image is picked up by an interlace operation.
In the field and the second field, a potential well is formed under the same electrode that receives the same clock of CCDs of the respective stages forming the image part to accumulate signal charges, and at the time of frame transfer of each field,
The frame charge is performed after mixing the signal charges accumulated in two CCDs adjacent to each other in the image part, and at this time, by the transfer clock given to the image part and the storage part, between the first field and the second field. A combination of two adjacent CCDs that mix signal charges is shifted by one CCD stage and transferred to the storage section.

Further, the solid-state image pickup device according to the present invention is
The number of CCDs forming the storage section is half the number of CCDs forming the image section, and the image is picked up only by the interlacing operation.

Further, the solid-state image pickup device according to the present invention is
When an image is picked up by the interlace operation, in the first field and the second field, potential wells are formed under the same electrode receiving the same clock of CCDs of the respective stages forming the image part to accumulate signal charges, The signal charges accumulated in the storage unit are independently transferred to the storage unit without being mixed, and then the horizontal C is transferred from the storage unit.
The signal charges transferred to the storage unit are mixed by two stages of CCDs and transferred to the horizontal CCD by the transfer clock when transferring the signal charges to the CD. At this time, the transfer clock applied to the storage unit and the horizontal CCDs. In the above, the combination of two adjacent signal charges for mixing the signal charges between the first field and the second field is shifted by one CCD.

Furthermore, the solid-state image sensor according to the present invention is
In an interline transfer type solid-state imaging device, signal charges are transferred from a plurality of photodiodes to the vertical CCD, and the signal charges for each die transferred from the plurality of photodiodes are transferred from the vertical CCD to a horizontal CCD. In this case, in both the first field and the second field, the horizontal C while mixing two adjacent signal charges of the signal charges for each die transferred to the vertical CCD.
The signal is read out to the CD, and the combination of the two mixed signal charges is shifted by the signal charge of one photodiode between the first field and the second field.

[0014]

In the present invention, the potential well for accumulating the signal charge between the first field and the second field is formed under the electrode receiving the same clock, so that it is obtained between the first field and the second field. Since the form of the sensitivity potential is the same, the interlacing operation can be performed without causing the sensitivity difference between the first field and the second field, and the occurrence of flicker on the imaging screen can be eliminated.

Further, according to the present invention, in the interline transfer type solid-state image pickup device, when the signal charges accumulated in the photodiodes are read out from the vertical CCDs to the horizontal CCDs, the signal charges for two photodiodes are mixed. In reading, at this time, interlacing is performed by shifting the combination of signal charges mixed in the first field and the second field by the signal charge of one photodiode. Therefore, the sensitivity obtained between the first field and the second field is obtained. The potential forms are the same, the interlace operation can be performed without causing a sensitivity difference between the first field and the second field, and the occurrence of flicker on the imaging screen can be eliminated.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic plan view showing the structure of a frame transfer type solid-state imaging device according to an embodiment of the present invention.
In the figure, the same reference numerals as those in FIG. 12 indicate the same or corresponding portions. In this solid-state image pickup device, the image portion 2 of the vertical CCD 1 has three electrodes for receiving a clock φ1, a clock φ2a and a clock φ3a for each clock. First with
CCD, clock φ1, clock φ2b, clock φ
Second C with 3 electrodes receiving 3b every clock
A plurality of CDs are alternately arranged, and a CCD having three electrodes that the storage unit 3 receives for each clock of clock Ψ1, clock Ψ2, and clock Ψ3 is arranged in half the number of stages of the image unit 2. It is configured. It should be noted that this solid-state image pickup device picks up an image only by the interlace operation.

Next, the operation will be described. FIG. 2 is a timing chart of clocks given to the image section 2, and FIG. 3 is timings t1 to t6 in FIG.
4 is a diagram showing a potential distribution in each CCD constituting the image part 2 in FIG. 4 and FIG. 4 is a diagram showing a transfer clock given to the image part 2 and the storage part 3 at the time of frame transfer. In addition, A, B, and
Reference symbols C and D are provided to define the signal charge accumulated in the potential well for the sake of convenience.

The operation will be described below with reference to FIGS. 2, 3 and 4. First, at the timing t1 in the charge accumulation period of the first field of FIG.
Since only 1 is at the high level, as shown in FIG. 3, potential wells are formed under the respective electrodes to which the clock .phi.1 of each CCD of the image section 2 is applied, and signal charges are accumulated therein. Next, at the timing of t2 in the vertical blanking period after the end of the charge accumulation period of FIG. 2, the clock φ2a and the clock φ3a also become high level,
As shown in FIG. 3, each CCD clock φ2a,
A potential well is formed below the electrode to which the clock φ3a is applied, and this potential well is connected to the potential wells formed below the electrode to which the clock φ1 is applied, which are adjacent to both sides of the potential well. The signal charges accumulated in the potential well below the electrode to which the clock .phi.1 is applied are mixed and accumulated in the well (signal charge A + B, signal charge C + D). Next, t3 in the vertical blanking period of FIG.
When the clock φ1 and the clock φ2a become low level in this order at the timing of, the mixed and accumulated signal charge A + B and signal charge C + D are applied to the electrode to which the high level clock φ3a is applied as shown in FIG. After moving to the potential well formed below, a frame transfer is performed as shown in FIG. In this frame transfer, since the image section 2 is in the state where the signal charges are accumulated every other CCD as described above, and the storage section 3 is composed of CCDs having half the number of stages of the image section 2, 3, the clock φ1, the clock φ2a, and the clock φ3a supplied to the image unit 2 are three-phase clocks, and the clocks Ψ1 to Ψ provided to the storage unit 3 are shown.
By setting 3 to be a three-phase clock having a half frequency of the clock φ1, the clock φ2a, and the clock φ3a given to the image section 2, the signal charges accumulated every other CCD in the image section 2 are stored in the CCD1 of the storage section 3. It is transferred step by step. Next, the charge accumulation period of the second field is entered, and during this period, only the clock φ1 is at the high level (at the timing of t4 in FIG. 2), and as in the charge accumulation period of the first field shown in FIG. Clock φ as shown
A potential well is formed under the electrode of each CCD to which 1 is applied, and signal charges are accumulated therein. Next, in the vertical blanking period, when the clock φ2b and the clock φ3b become high level at the timing of t5 in FIG. 2, potential wells are formed under the electrodes receiving these clock φ2b and clock φ3b as shown in FIG. Was
The potential well and the potential wells formed under the electrodes to which the clock φ1 is applied on both sides of the potential well are coupled to each other, and the mixed signal charge is accumulated in the coupled potential well (signal charge). B + C). Next, at the timing indicated by t6 in FIG.
When the clock φ1 and the clock φ2b are set to the low level in this order, the accumulated signal charge B + C is moved below the electrode receiving the transfer clock φ3b, and then the frame transfer is performed. At the time of this frame transfer, at the beginning of the frame transfer, the position where the electric charge exists in the image portion 2 is CC compared to the first field.
Since it is deviated by one step in D, the frame transfer clocks Ψ 1, Ψ 2, Ψ 3 consisting of three-phase clocks given to the storage unit 3 at this time are 90 times as compared with those of the first field as shown by the broken line in FIG. ° It is necessary to shift the phase. At this time, the clock φ1, the clock φ2b, and the clock φ3b given to the image section 2 are the same three-phase clocks as in the first field, and the frame transfer clocks Ψ1 to Ψ3 are the same as those in the first field.
Phase clock (clock φ1, clock φ2b, clock φ
A three-phase clock with half the frequency of 3b) is used. Then, the operation described above is repeated thereafter, and the image is taken by the interlace operation.

In such a frame transfer type solid-state image pickup device of this embodiment, clock φ1 and clock φ2
a, a first CCD having three electrodes for receiving clock φ3a at each clock, clock φ1, clock φ2b,
The image portion 2 is provided by alternately arranging a plurality of stages of the second CCD having three electrodes for receiving the clock φ3b for each clock.
In each of the first field and the second field, signal charges are stored under the electrodes receiving the clock φ1, and before the frame transfer in each field, the clock φ1, the clock φ2a, and the clock φ3a in the first field The signal charges of two adjacent CCD stages are combined and accumulated under the electrode receiving the clock φ3a of one CCD stage, and the clock φ is accumulated in the second field.
1, the clock φ2b and the clock φ3b combine and store the signal charges of two CCDs adjacent to each other, which are one CCD stage different from the first field, under the electrodes receiving the clock φ3b of one CCD stage, and respectively. In the frame transfer of the field, the transfer clocks Ψ 1 to Ψ 3 having half the frequency of the transfer clock given to the image section 2 and having a phase difference of 90 ° between the first field and the second field are given to the storage section 3. By that,
Since the signal charges that have been combined and accumulated in each of the fields are transferred to the storage unit 3, the sensitivity potentials of the signal charges between the first field and the second field become equal, and as a result, the first field and the second field. The interlacing operation can be performed without causing a sensitivity difference between them, and an image can be captured without causing flicker.

In the frame transfer type solid-state image pickup device of the present embodiment, the signal charges accumulated in every other CCD of the image part 2 are transferred to the CC of half the number of steps of the image part 3.
In order to transfer the data to the storage unit 3 configured by D, as shown in FIG.
As compared with the conventional frame transfer type solid-state image pickup device shown in FIG. 2, the number of CCD stages of the entire image pickup device can be reduced, and the device can be downsized.

Further, in the above embodiment, the transfer clocks Ψ 1 to Ψ 3 given to the storage unit 3 at the time of frame transfer in the second field are 90 ° out of phase with those in the first field, but in the second field shown in FIG. During the timing t5 to t6 of the vertical blanking period, appropriate clocks are applied to the clocks φ1, φ2a, φ3a, φ2b, and φ3b, and the accumulated signal charge (B + C in the figure) is fed to the clock φ.
If the data is transferred below the electrode for receiving 3a (A + B in the figure), the interlacing operation can be performed without shifting the phases of the transfer clocks Ψ1 to Ψ3 given to the storage section between the first and second fields.

FIG. 5 is a plan view showing the structure of a frame transfer type solid-state image pickup device according to the second embodiment of the present invention. The same reference numerals as those in FIG. 1 indicate the same or corresponding portions. , The storage section 3 and the image section 2 have the same number of CCD stages, and control clocks φ1, φ2a, φ3a, φ given to the image section 2 and the storage section 3
The non-interlaced operation and the interlaced operation can be selectively performed by 2b, φ3b, Ψ1, Ψ2, Ψ3. FIG. 6 is a timing chart of transfer clocks given to the image section 2 and the storage section 3 in the frame transfer during the interlace operation.

The operation will be described below. That is, in this solid-state imaging device, during the non-interlaced operation, similar to the conventional frame transfer type solid-state imaging device shown in FIG. 14, signal charges are accumulated under a predetermined electrode of each CCD of the image section 2, The signal charges are directly transferred to the storage unit 3 without being mixed, and the transferred signal charges are sequentially read from the output unit 5 through the horizontal CCD 4. During the interlacing operation, the same as in the first embodiment described above. In the first and second fields, the clocks φ1, φ2a, φ3a, φ2b, φ given to the image section 2 are
By 3b, the signal charges are accumulated under the electrodes which receive the clock φ1 of each CCD constituting the image part 2, and the two adjacent CCDs which mix the signal charges between the first field and the second field in the image part By changing the combination, the signal charges of two CCDs are mixed, and thereafter, the signal charges mixed in the image part are frame-transferred to the storage part by the transfer clock given to the image part 2 and the storage part 3. Then, at the time of this frame transfer, transfer clocks (clocks φ1, φ2a, φ3a, φ2b,
.phi.3b and clocks .psi.1 to .psi.3) are supplied with transfer clocks having the same phase and the same frequency as shown in FIG. 6, and the signal charges accumulated in every other CCD of the image section 2 are stored in the CCD of the storage section 3. Transfers every other stage.
At this time, in the first field and the second field, as in the first embodiment, adjacent CCs in the image section 2 are
Since the accumulation positions of the signal charges accumulated by mixing the signal charges of D2 stages are shifted by one CCD, it is necessary to shift the application timing of the transfer clock given to the storage unit by the amount of one CCD transfer. The signal charges transferred to the storage unit 3 in this manner are then applied to the storage unit 3 and the horizontal CCD 4 as CCs of the storage unit 3.
It is transferred to the horizontal CCD 4 by the transfer clock for transferring the signal charges of D2 stages, and is read out to the outside via the output unit 5.

In the frame transfer type solid-state image pickup device of this embodiment, the image section 2 is constructed in the same manner as in the first embodiment, and the storage section 3 is constructed by CCDs having the same number of stages as the image section 2. Therefore, image formation can be performed by both non-interlaced operation and interlaced operation.
Since the potential wells for accumulating the signal charges in the first field and the second field are formed under the same electrode of the same CCD as in the first embodiment, the sensitivity of the signal charges between the first field and the second field is increased. The potentials can be made equal, and an image without flicker can be obtained. Further, since the interlace operation and the non-interlace operation can be selected by the control clock given to the image section 2, the storage section 3 and the horizontal CCD 4, the interlace operation and the non-interlace operation can be used properly according to their respective applications. You can

FIG. 7 is a plan view showing the structure of a frame transfer type solid-state image pickup device according to the third embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 1 designate the same or corresponding parts. In the image pickup device, similarly to the conventional solid-state image pickup device shown in FIG. 15, the image section 2 is configured by arranging a plurality of CCDs each having three electrodes for receiving the clocks φ1 to φ3 at each clock, and storing the CCD. The unit 3 is constructed by arranging CCDs for receiving the clocks ψ1 to ψ3 in half the number of stages of the image unit 2. Incidentally, this solid-state image pickup device picks up an image only by the interlacing operation as in the first embodiment.

On the other hand, FIG. 8 is a timing chart of transfer clocks .phi.1 to .phi.3 and transfer clocks .psi.1 to .psi.3 respectively given to the image section 2 and the storage section 3 at the time of frame transfer, and FIG. 8A shows in the first field. 8B shows a timing chart, and FIG. 8B shows a timing chart in the second field. Further, FIG. 9 shows timings t11 to t21 and t111 in FIG.
C of each of the image section 2 and the storage section 3 from t116 to t116
FIG. 9 is a diagram showing a potential distribution in CD, and FIG.
(a) shows the potential distribution of the first field, as shown in FIG.
(b) shows the potential distribution of the second field. The symbols A to E in the figure represent the accumulated signal charges and C.
It is a code added for convenience to define the correspondence with the CD stage. The operation will be described below with reference to these drawings.

That is, in this solid-state image sensor, as shown in FIG.
As shown in FIG. 9, in the first field and the second field, a potential well is formed under the same electrode receiving the same clock of each CCD of the image part 2 to accumulate signal charges, and the frame transfer in each field is performed. At this time, while the signal charges are transferred from the image section 2 to the storage section 3 by the transfer clocks φ1 to φ3 and the transfer clocks Ψ1 to Ψ3 given to the image section 2 and the storage section 3, the two CCDs adjacent to the image section 2 are charged. The signal charges are mixed, and the signal charges are transferred to one stage of the CCD in the storage unit 3. Here, the transfer clocks Ψ 1 to Ψ 3 given to the storage unit 3 in the first field and the second field are, as shown in FIG. 7, half the frequency of the transfer clocks φ 1 to φ 3 given to the storage unit 3, and The two fields are out of phase with each other by 180 °, so that the combination of the two CCDs of the image portion 2 corresponding to the mixed signal charges is shifted by one stage in the CCD between the first and second fields, and The phase of the signal charge transferred in the first field and the second field is 180 °
It shifts. The transfer clocks Ψ1 to Ψ3 given to the storage unit 3 are one of the three clocks,
That is, the clock Ψ1 is replaced by the other two clocks (clock Ψ1
It consists of a three-phase clock that is inverted with respect to 2 and Ψ3).

As described above, in the frame transfer type solid-state image pickup device of the present embodiment, the potential well is formed below the electrodes that receive the same clock of the CCD constituting the image section 2 in both the first field and the second field. Transfer clocks (clocks φ1 to φ3, clocks Ψ1 to Ψ3) that accumulate signal charges and give them to the image section 2 and the storage section 3 during frame transfer for each field.
), The two adjacent signal charges are mixed while the signal charges are transferred from the image unit 2 to the storage unit 3, and the frequencies of the transfer clocks Ψ 1 to Ψ 3 given to the storage unit 3 at this time are transferred to the image unit 2. The frequency of the transfer clocks φ1 to φ3 given is set to half, and the phase of the transfer clocks Ψ1 to Ψ3 given to the storage unit 3 is shifted by 180 ° between the first field and the second field. The sensitivity potential of the signal charges can be made equal between fields, and an image without flicker can be obtained by the interlacing operation. Further, since the number of CCD stages forming the storage unit 3 is half that of the image unit 2 as in the first embodiment, the number of CCD stages of the entire solid-state image pickup device can be reduced, and the apparatus can be downsized. be able to.

Since the frame transfer type solid-state image pickup device of this embodiment picks up an image only by the interlace operation, the number of CCDs in the storage section 3 is half that of the image section 2. The number of steps may be the same as that of the image unit 2 so that both interlaced operation and non-interlaced operation can be performed.
In this case, during the interlace operation, the signal charges transferred from the strainer unit 3 to the horizontal CCD 4 are output from the horizontal CCD 4 by the transfer clock given to the horizontal CCD 4 in the same manner as in the second embodiment. To be read out.

FIG. 10 is a schematic plan view for explaining the structure and operation of the frame transfer type solid-state image pickup device according to the fourth embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 7 are the same or equivalent. In the figure, reference numerals A to E are reference numerals added for convenience in order to define the correspondence between the signal charges accumulated in each CCD of the image part 2 and each CCD. In the frame transfer type solid-state image pickup device, the image unit 2 and the storage unit 3 have the same C as in the conventional solid-state image pickup device shown in FIG.
It is configured by arranging a plurality of CDs. Note that, for simplification, in this figure, wirings for supplying a clock to the image unit 2 and the storage unit 3 are omitted.

Next, the operation will be described. This solid-state imaging device does not mix signal charges when transferring the signal charges from the image unit 2 to the storage unit 3, but transfers the signal charges from the storage unit 3 to the horizontal CCD unit 4 by a transfer clock given to the horizontal CCD 4. At this time, the signal charges for two CCDs are mixed and transferred, and the combination of the CCDs for mixing the signal charges is changed between the first field and the second field, whereby the image is picked up by the interlacing operation. ..

That is, for example, as shown in FIG.
The signal charge A accumulated in the CCD of each stage of the image part 2
As shown in FIG. 10B, E is transferred to the storage unit 3 independently without being mixed by the frame transfer. Then, when the signal charges are transferred from the storage unit 3 to the horizontal CCD unit 4 in the first field, as shown in FIG.
As shown in 0 (c), the signal charges A and B are mixed and horizontal C
In the D field, the signal charges of two adjacent CCD stages are mixed and read out to the horizontal CCD unit 4 in the order of reading out to the CD unit 4 and then mixing and reading out the signal charges C and D. As shown in 10 (d), CC of the first stage
After reading the signal charge A of D, the signal charges B and C are mixed and read to the horizontal CCD unit 4, and then the signal charges E and D are mixed and read. The CCDs are shifted by one stage, and the signal charges of the adjacent two CCDs are mixed and read out to the horizontal CCD section 4.

FIG. 11 is a timing chart of the drive clock of this frame transfer type solid-state image pickup device, and FIG. 12 is each of the image section 2, the storage section 3 and the horizontal CCD section 4 at the timing shown in FIG. CCD
FIG. 3 is a diagram showing a potential distribution in FIG. 3, and the above operation will be described in detail below with reference to these diagrams.

First, at the timing t0 in FIG. 12, the signal charges (A to E) accumulated under the electrodes to which the high level clock φ1 of each CCD in the image section 2 is applied are stored in the image section 2 and the storage section 3, respectively. Transferred from the image section 2 to the storage section 3 by the given clocks φ1 to φ3 and clocks Ψ1 to Ψ3. And FIG.
As shown in, the clock ψ1 consisting of a three-phase clock given to the storage unit 3 during the horizontal blanking period
The signal charges (A to E) transferred to the storage unit 3 by Ψ3 and the high-level clock φH given to the horizontal CCD 4 are CCD at timings t22 to t27.
When moving toward the horizontal CCD 4 step by step and entering the horizontal scanning period (at timing t28), the signal charges of the CCD for two steps, that is, the signal charges A, from the CCD side of the storage unit 3 near the horizontal CCD 4 B mixed, horizontal CCD
The mixed charge A + B is read out to No. 4. During this time,
As shown in FIG. 12, the storage unit 3 is supplied with a three-phase clock, and the horizontal CCD 4 is supplied with a clock φH which is a high level periodic pulse which is always at a high level during the horizontal blanking period and has a large frequency during the horizontal scanning period. Be done. After this, in the next horizontal blanking period, the next CCD
The signal charges C and D for two stages are mixed, and the mixed signal charges C + D in the horizontal scanning period are read out. Thereafter, this operation is repeated, and the first field ends. And when the first field ends,
In the second field, as described above, the combination of the signal charges to be mixed is changed. First, the signal charge A closest to the horizontal CCD 4 is read out, and thereafter, by the same operation as in the first field, two CCDs are added. Signal, that is, the signal charges B and C, and the signal charges D and E which are adjacent to each other in this order are mixed and read out to the horizontal CCD 4.

In such a frame transfer type solid-state image pickup device of this embodiment, the signal charges accumulated in the CCDs of the image section 2 are transferred to the storage section 3 as they are without being mixed, and then the signal charges are leveled with the storage section 3. By the transfer clock given to the CCD 4, the signal charges transferred to the strainer unit 3 are mixed with the signal charges of two adjacent CCD stages and read out to the horizontal CCD 4, and are mixed in the first field and the second field. Since the combination of the signals read out to the horizontal CCD 4 is shifted by one stage by the CCD, the first field and the second field are arranged in the same manner as in the above embodiment.
The sensitivity potentials of the signal charges read out between fields can be made equal, and an image without flicker due to the conventional interlace operation can be obtained. Further, in this solid-state image pickup device, similarly to the solid-state image pickup device of the second embodiment, an image can be picked up by a non-interlaced operation by a clock given to the image unit 2, the storage unit 3 and the horizontal CCD 4, and it is suitable for use. Accordingly, the interlaced operation and the non-interlaced operation can be selectively used.

In this embodiment, the signal charges for the two CCDs are mixed, but the signal charges for the CCDs having a larger number of stages are mixed, and the first charge is supplied by the clock given to the storage section 3 and the horizontal CCD 4. By changing the combination of the signal charges mixed in the field and the second field, the phase of the signal charges read between the first field and the second field is set to 1
The reading may be performed by shifting by 80 °, and in this case, the same effect as that of this embodiment can be obtained.

FIG. 13 is a schematic plan view for explaining the structure and operation of the frame interline transfer type solid-state image pickup device according to the fifth embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 7 are the same or equivalent. Shows the part to
In this frame interline transfer type solid-state image sensor, the image part 2 has a photodiode 11 and a vertical CCD.
12, the storage unit 3 has basically the same configuration as that of the solid-state image pickup device of the above-described first to fourth embodiments. The frame interline transfer type solid-state imaging device has signal charges (A to E) obtained by photoelectric conversion in the photodiode 11 of the image unit 2.
However, as in the solid-state image sensor of the fourth embodiment, as shown in FIG.
As shown in (b), the storage unit 3 is not mixed.
After that, as shown in FIGS. 13 (c) and 13 (d), by the clock given to the storage unit 3 and the horizontal CCD 4,
The combination of the signal charges mixed in the first field and the second field is changed, the signal charges read out between the first field and the second field are read out so that the phase thereof is shifted by 180 °, and imaging is performed by the interlacing operation.

In such a frame interline transfer type solid-state image pickup device of the present embodiment, the interlacing operation is performed based on the same signal charge generated in the same photodiode in the first field and the second field, so that the first interlace operation is performed. The sensitivity potential of the signal charges read out between the field and the second field can be made equal, and flicker occurs when imaging is performed by the interlace operation.
You can get a picture without. Further, this frame interline transfer type solid-state image pickup device can also perform image pickup by a non-interlace operation by a clock given to the image section 2, the storage section 3 and the horizontal CCD 4, and the interlace operation and the non-interlace operation can be performed depending on the application. Can be used properly.

FIG. 14 is a schematic plan view for explaining the structure and operation of the interline transfer type solid-state image pickup device according to the sixth embodiment of the present invention. In the figure, 20 is a photosensitive section, and the photosensitive section 20 is shown. Is the photodiode 21,
It is composed of a vertical CCD 22, and the signal charges generated in the photosensitive section 20 are output to the outside through a horizontal CCD 23 and an output section 24.

Then, in this solid-state image pickup device, as shown in FIG.
As shown in (b) and (c), the signal charges obtained by photoelectric conversion in the photodiode 21 are read out to the vertical CCD 22, and thereafter, as in the solid-state image sensor of the fourth embodiment, As shown in FIGS. 14 (d) and 14 (e), the vertical CCD 2
2, by the transfer clock given to the horizontal CCD 23, the first
By changing the combination of the two signal charges mixed in the field and the second field, the signal charges read out between the first field and the second field are read out so that the phase thereof is shifted by 180 °, and imaging by the interlacing operation is performed.

In such an interline transfer type solid-state image pickup device of the present embodiment, the same signal charge generated in the same photodiode in the first field and the second field as in the solid-state image pickup device of the fifth embodiment. Since the interlacing operation is performed based on the above, the sensitivity potentials of the signal charges read out between the first field and the second field can be made equal, and an image without flicker can be obtained when the imaging is performed by the interlacing operation. it can. In addition, this frame interline transfer type solid-state image sensor also has a vertical CCD 22 and a horizontal CC.
Imaging can be performed by a non-interlaced operation by the clock given to D23, and the interlaced operation and the non-interlaced operation can be selectively used according to the application.

[0042]

As described above, according to the solid-state image pickup device of the present invention, in the first field and the second field, the CCDs of the respective stages constituting the image portion are provided under the same electrode receiving the same clock. A potential well is formed to store a signal charge, and two CCs adjacent to each other in the image area are transferred during frame transfer of each field.
The frame transfer is performed after the signal charges accumulated in D are mixed. At this time, the signal charges are mixed between the first field and the second field by the clock applied to the image part and the storage part. Since the combination of two CCDs is shifted by one CCD and transferred to the storage section to perform the interlace operation,
Since the form of the sensitivity potential of the signal charges obtained between the first field and the second field is the same, the interlace operation can be performed without causing the sensitivity difference between the first field and the second field, and It is effective in eliminating the occurrence of flicker.

Further, according to the solid-state image pickup device of the present invention, the number of CCDs forming the storage section is half the number of CCDs forming the image section, and the image is picked up only by the interlacing operation. Similar to the above, the interlace operation can be performed without causing a sensitivity difference between the first field and the second field,
It is possible to eliminate the occurrence of flicker on the image pickup screen and to reduce the size of the entire apparatus.

Further, according to the solid-state image pickup device of the present invention, in the first field and the second field, the potential well is formed under the same electrode which receives the same clock of the CCD of each stage forming the image part. Signal charges are stored in the image part, and the signal charges stored in the image part are independently transferred to the storage part without being mixed. Next, the signal charges are transferred from the storage part to the horizontal CCD, and then applied to the horizontal CCD from the storage part. Depending on the transfer clock,
The signal charges transferred to the storage unit are mixed by two stages of CCD and transferred to the horizontal CCD, and at the time of this transfer, two adjacent signal charges for mixing the signal charges between the first field and the second field are mixed. Since the interlacing operation is performed by shifting the combination of 1 field by one CCD, the form of the sensitivity potential of the signal charge obtained between the first field and the second field is the same, and the first field and the second field are the same. The interlacing operation can be performed without causing a sensitivity difference between them, and there is an effect that the occurrence of flicker on the imaging screen can be eliminated.

Furthermore, according to the solid-state image pickup device of the present invention, the number of CCDs forming the storage section is half the number of CCDs forming the image section, and image pickup is performed only by the interlacing operation. Similar to the above, the interlace operation can be performed without causing a sensitivity difference between the first field and the second field,
It is possible to eliminate the occurrence of flicker on the image pickup screen and to reduce the size of the entire apparatus.

Furthermore, the solid-state image sensor according to the present invention is
In an interline transfer type solid-state imaging device, signal charges are transferred from a plurality of photodiodes to a vertical CCD, and the signal charges of each die transferred from the plurality of photodiodes are transferred from the vertical CCD to a horizontal CCD. At this time, in both the first field and the second field, the horizontal CCD is mixed with the adjacent two signal charges of the signal charges for each die transferred to the vertical CCD.
, The interlace operation is performed by shifting the combination of two mixed signal charges by the signal charge of one photodiode between the first field and the second field. The form of the sensitivity potential of the signal charge obtained between the second fields is the same, the interlace operation can be performed without causing a sensitivity difference between the first field and the second field, and flicker on the imaging screen. The effect of eliminating the occurrence of

[Brief description of drawings]

FIG. 1 is a schematic plan view showing the structure of a frame transfer type solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a timing chart of clocks applied to the image section of the frame transfer type solid-state image sensor shown in FIG.

FIG. 3 is a diagram showing a potential distribution in a CCD of an image portion of the frame transfer type solid-state imaging device shown in FIG.

FIG. 4 is a diagram showing transfer clocks given to an image section and a storage section during frame transfer of the frame transfer type solid-state imaging device shown in FIG.

FIG. 5 is a schematic plan view showing the structure of a frame transfer solid-state image sensor according to the second embodiment of the present invention.

6 is a diagram showing transfer clocks given to an image section and a storage section during frame transfer of the frame transfer type solid-state imaging device shown in FIG.

FIG. 7 is a schematic plan view showing the structure of a frame transfer type solid-state imaging device according to a third embodiment of the present invention.

8 is a diagram showing a transfer clock given to an image unit and a storage unit at the time of frame transfer of the frame transfer type solid-state imaging device shown in FIG.

9 is a diagram showing a potential distribution in CCDs of an image part and a storage part at the time of frame transfer of the frame transfer type solid-state imaging device shown in FIG.

FIG. 10 is a schematic plan view for explaining the structure and operation of the frame transfer type solid-state imaging device according to the fourth embodiment of the present invention.

11 is a timing chart of drive clocks of the frame transfer type solid-state imaging device shown in FIG.

FIG. 12 is a CCD and horizontal C of the image part and the storage part of the frame transfer type solid-state imaging device shown in FIG.
It is a figure which shows the potential distribution in CD.

FIG. 13 is a schematic plan view for explaining the structure and operation of a frame interline transfer type solid-state imaging device according to the fifth embodiment of the present invention.

FIG. 14 is a schematic plan view for explaining the structure and operation of the interline transfer type solid-state imaging device according to the sixth embodiment of the present invention.

FIG. 15 is a schematic plan view showing the structure of a conventional frame transfer type solid-state imaging device.

16 is a schematic diagram of the frame transfer type solid-state image sensor shown in FIG.
It is the figure which showed typically the temporal distribution in the 1st field and the 2nd field in the cross section of the XIV-XIV line.

[Explanation of symbols]

1 Vertical CCD 2 Image part 3 Storage part 4 Horizontal CCD 5 Output part 11 Photodiode 12 Vertical CCD 20 Photosensitive part 21 Photodiode 22 Vertical CCD 23 Horizontal CCD 24 Output part φ1 to φ3, φ2a, φ2b, φ3a, φ3b Image part Clock to be given Ψ1 to Ψ3 Clock to be given to the storage unit φH Clock to be given to the horizontal CCD AE Code for determining the storage position of the signal charge for convenience

Claims (8)

[Claims] 1. A vertical CCD comprising an image section composed of a plurality of CCDs and a storage section composed of a plurality of CCDs, and a signal charge accumulated in the vertical CCDs is read out to a horizontal CCD. A solid-state imaging device for outputting the signal charges to the outside from an output unit connected to the horizontal CCD, wherein the image unit includes electrodes for receiving the same clock and electrodes for receiving different clocks. A plurality of first and second CCDs provided are alternately arranged, and the first and second CCDs forming the image section are formed in both the first field and the second field during imaging by the interlacing operation. A potential well is formed below the electrodes of the CCD for receiving the same clock to store signal charges, and the accumulated signal charges are transferred from the image portion to the scan unit. When transferring to the storage unit, the signal charges accumulated in the two adjacent CCDs in the image unit are mixed, and the mixed signal charges are given to the image unit and the storage unit and the transfer clocks of the same frequency are given. Are transferred to the storage section by means of a first clock, and a combination of the two CCDs adjacent to each other is first changed by a clock given to the image section when the signal charges are mixed.
A solid-state image sensor characterized in that the CCD is shifted by one stage between the field and the second field. 2. A vertical CCD having an image section composed of a plurality of CCDs and a storage section composed of a plurality of CCDs, and reading out signal charges accumulated in the vertical CCDs to a horizontal CCD. A solid-state imaging device for outputting the signal charges to the outside from an output unit connected to the horizontal CCD, wherein the image unit includes electrodes for receiving the same clock and electrodes for receiving different clocks. A plurality of first and second CCDs provided are alternately arranged, and the storage section is composed of CCDs having half the number of stages of the image section. In any of the two fields, a potential well is formed under the electrodes that receive the same clock of the first and second CCDs forming the image section. To store signal charges and transfer the stored signal charges from the image part to the storage part, after mixing the signal charges stored in two adjacent CCDs in the image part, The mixed signal charges are transferred to the storage unit by a transfer clock that gives the image unit and a transfer clock that has a frequency half that of the transfer clock and that is given to the storage unit. 2. A solid-state image pickup device, characterized in that the combination of two adjacent CCDs that perform the above mixing is shifted by one CCD between the first field and the second field. 3. The solid-state imaging device according to claim 2, wherein when the signal charge is transferred from the image section to the storage section, the phase of the transfer clock applied to the storage section is 90 ° between the first field and the second field. A solid-state imaging device characterized by being displaced. 4. The solid-state imaging device according to claim 2, wherein in the second field, the signal charges accumulated in two adjacent CCDs in the image section are mixed, and the mixed signal charges are mixed in the image. The transfer position of the mixed signal charge to the same storage position as the storage position of the mixed charge of the first field by the clock given to the image part before transfer when transferring from the storage unit to the storage unit. A solid-state image sensor. 5. A vertical CCD having an image section composed of a plurality of CCDs and a storage section composed of a plurality of CCDs, and reading out signal charges accumulated in the vertical CCDs to a horizontal CCD. A solid-state imaging device for outputting the signal charges to the outside from an output unit connected to the horizontal CCD, which constitutes the image unit in both the first field and the second field during imaging by an interlacing operation. When the potential well is formed under the electrodes of the CCDs of the plurality of stages receiving the same clock to store the signal charges and the accumulated signal charges are transferred from the image unit to the storage unit, the image unit and the storage unit While the signal charges accumulated in two adjacent CCDs in the image section are mixed by the transfer clock given to So as to transfer the storage unit, and by 180 ° shifting it between the first and second fields the phase of the transfer clock to be supplied to the storage section, two adjacent CCD for mixing the signal charges
The combination of CC between the first and second fields
A solid-state imaging device characterized by being shifted by D1 steps. 6. A vertical CCD having an image part composed of a plurality of stages of CCD and a storage part composed of a plurality of stages of CCD, and reading out a signal charge accumulated in the vertical CCD to a horizontal CCD. A solid-state imaging device for outputting the signal charges to the outside from an output unit connected to the horizontal CCD, wherein the storage unit has a CC of half the number of stages of the image unit.
In addition, the potential well is formed under the electrodes that receive the same clock of the CCDs of the plurality of stages forming the image portion in both the first field and the second field during the imaging by the interlace operation. When the signal charges are accumulated and the accumulated signal charges are transferred from the image part to the storage part, a transfer clock having the same clock as that at the time of accumulating the signal charges is given to the image part, and the storage part is supplied to the storage part. A transfer clock having a frequency half that of the transfer clock applied to the image section is applied to transfer the signal charges accumulated in two adjacent CCDs in the image section to the storage section while mixing the signal charges, and The phase of the transfer clock applied to the storage unit is 180 ° between the first field and the second field. By causing et al., Two adjacent CCD for mixing the signal charges
The combination of CC between the first and second fields
A solid-state imaging device characterized by being shifted by D1 steps. 7. A vertical CCD having an image section composed of a plurality of CCDs and a storage section composed of a plurality of CCDs, and reading out signal charges accumulated in the vertical CCDs to a horizontal CCD. A solid-state imaging device for outputting the signal charges to the outside from an output unit connected to the horizontal CCD, which constitutes the image unit in both the first field and the second field during imaging by an interlacing operation. A potential well is formed under the electrodes of a plurality of CCDs that receive the same clock to store signal charges, the accumulated signal charges are transferred to the storage unit, and the signal charges transferred to the storage unit are transferred to the storage unit. When reading out to the horizontal CCD, the transfer clock given to the above-mentioned strain section and the transfer clock given to the above-mentioned horizontal CCD are used for the storage. The signal charges accumulated in the two adjacent CCDs in the unit are mixed and read out to the horizontal CCD, and the phase of the transfer clock applied to the storage unit is shifted by 180 ° between the first field and the second field. Allows two adjacent CCDs that mix the signal charges described above.
The combination of CC between the first and second fields
A solid-state imaging device characterized by being shifted by D1 steps. 8. The interline transfer type solid-state imaging in which a signal charge generated in a photodiode is transferred to a vertical CCD adjacent to the photodiode, and then the signal charge is output from an output unit through a vertical CCD and a horizontal CCD. A device, which is a device, and at the time of imaging by an interlacing operation, signal charges are transferred from the plurality of photodiodes to the vertical CCD, and the signal charges for each die transferred from the plurality of photodiodes are transferred to the vertical CCD and the horizontal CCD.
When the data is transferred to the horizontal CCD by the transfer clock given to the vertical CCD, in each of the first field and the second field, by the transfer clock given to the vertical CCD and the horizontal CCD, Two adjacent signal charges of the signal charges are mixed and read out to the horizontal CCD, and the phase of the transfer clock given to the vertical CCD is 180 ° between the first field and the second field.
A solid-state imaging device, wherein the combination of the two mixed signal charges is shifted by the amount of the signal charge of one diode between the first field and the second field.