JPH05298410A - Picture processor - Google Patents

Abstract

PURPOSE:To shorten the transfer time of a picture, and to transfer picture data to plural sheets of picture processing circuit substrates at a time. CONSTITUTION:This picture processor is constituted by arranging plural sheets of the picture processing circuit substrates 20 to execute picture processing on the basis of a horizontal/vertical synchronizing signal HV, and a signal is transmitted and received between each substartess2O and another, and each substrate 20 is provided with a synchronizing signal control circuit 1, buffers 4,5, and a master/slave control circuit 2 as a synchronizing signal reset control means, and at the time of the transmission and the reception of the signal, all the synchronizing signals HV of each substrate 20 participating in the transmission and the reception are reset by this synchronizing signal reset control means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus composed of a plurality of image processing circuit boards, each of which performs arbitrary image processing.

[0002]

2. Description of the Related Art A conventional general-purpose image processing circuit board usually has, for example, an image memory in which image data is written / read out so that one image processing circuit board can perform image processing to some extent. An image processor that is the center of image processing, a sync signal generator that generates sync signals required for image processing such as horizontal and vertical sync signals, and image input / output that handles input / output of image data (image signal) Part and. Further, in such an image processing circuit board, an address synchronized with a video signal is supplied to the image memory in order to facilitate writing of image data. Conventionally, a large-scale image processing apparatus is configured by using a plurality of such image processing circuit boards.

[0003]

By the way, in the image processing apparatus composed of a plurality of image processing circuit boards as described above, when image data is transferred (transmitted / received) between the image processing circuit boards, , The image processing circuit board on the image data sending side (sending side) is sent on the receiving side
Since it is necessary to send the image data in synchronization with the synchronization of the video signal on the image processing circuit board, there is a problem in that the image is delayed by a maximum of one frame and the transfer time becomes long.

Further, when image data is transmitted and received between the image processing circuit boards as described above, if the video signals of the image processing circuit boards are not synchronized, a plurality of images are processed at a time. It is impossible to transfer the image data to the processing circuit board.

Therefore, the present invention has been proposed in view of the above situation, and it is possible to shorten the image transfer time and to transfer the image data to a plurality of image processing circuit boards at the same time. It is an object of the present invention to provide an image processing device capable of performing the above.

[0006]

The image processing apparatus of the present invention has been proposed to achieve the above-mentioned object, and performs arbitrary image processing based on a synchronization signal (horizontal / vertical synchronization signal). An image processing device configured by arranging a plurality of image processing blocks (for example, an image processing circuit board) and transmitting and receiving a signal between the image processing blocks,
Each of the image processing blocks has a sync signal reset control means for resetting the sync signal, and at the time of transmitting and receiving the signal, the sync signal of all the image processing blocks involved in the transmission and reception of the signal by the sync signal reset control means. Is to be reset.

More specifically, the image processing apparatus of the present invention uses at least a sync signal generating means for generating a sync signal (horizontal / vertical sync signal), an image memory, and a sync signal from the sync signal generating means. And a plurality of image processing circuit boards having image memory control means for controlling writing / reading of the image memory on the basis of the image memories. Image processing is performed by the plurality of image processing circuit boards. An image processing apparatus for transmitting and receiving signals between processing circuit boards, wherein each image processing circuit board is
As the synchronization signal reset control means, a synchronization signal control means for generating a synchronization reset signal based on a transfer start signal supplied from an external CPU (external CPU board), and an image processing circuit board which is the transmitting side or receiving The discriminating means for discriminating whether the image processing circuit board is the side and the synchronous reset signal output from the synchronizing signal control means are supplied and operate based on the discriminating signal from the discriminating means, and the discriminating signal is the receiving side. The first gate means for limiting the output of the supplied synchronous reset signal and passing the synchronous reset signal when the discrimination signal indicates the transmitting side; and the discrimination means. When the discrimination signal of indicates that the signal is on the transmitting side, the discrimination signal is passed through the synchronous reset signal supplied through the first gate means. And a second gate means for passing a synchronous reset signal sent from another image processing circuit board and sending the passed output to the synchronous signal generating means when the signal is sent to the other side. In transmitting and receiving the above signals, the synchronizing signal generating circuits of all image processing circuit boards involved in transmitting and receiving these signals are reset so that the phases of the synchronizing signals are aligned.

In other words, the image processing device of the present invention is
A device capable of transferring image data between image processing circuit boards having an image memory whose address is determined by a signal synchronized with a video signal. For example, a CPU circuit board is used in addition to the image processing circuit board, and the CPU circuit is used. The board controls the transfer of images between the image processing circuit boards, and the image processing circuit board that transfers image data resets all the synchronization signals of its own circuit board and the circuit board of the transfer side. It is the one. That is, according to the present invention,
When image data is transferred between a plurality of image processing circuit boards, a sync signal reset circuit (sync signal reset control means) is added to each circuit board to improve the image transfer speed and further to provide one circuit. The image data can be simultaneously transferred from the board to a plurality of circuit boards.

[0009]

According to the image processing apparatus of the present invention, since each image processing block has the synchronization signal reset control means for resetting the synchronization signal, each image involved in the transmission and reception of the signal is transmitted and received. By operating the synchronization signal reset control means of all the processing blocks, it is possible to reset the synchronization signals in these image processing blocks. Therefore, all the image processing blocks involved in transmission / reception can be synchronized in the same phase. Become.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, the image processing apparatus of the embodiment of the present invention is provided with a plurality of image processing circuit boards 20 for performing arbitrary image processing based on a synchronization signal (horizontal / vertical synchronization signal HV). Each of the image processing circuit boards 20 is configured.
In the image processing device for transmitting and receiving signals such as image data between the image processing circuit boards 20, each of the image processing circuit boards 20 has a synchronization signal reset control means for resetting the horizontal / vertical synchronization signal HV. At this time, the sync signal reset control means resets the horizontal / vertical sync signals HV of all the image processing circuit boards 20 involved in transmission / reception of the signal. Note that FIG. 1 shows the configuration of only one main part of the image processing circuit board 20.

More specifically, one image processing circuit board 20 constituting the image processing apparatus of this embodiment has, as a basic configuration, an image memory 7 for writing / reading image data, and the above-mentioned image memory 7. The horizontal / vertical synchronizing signal HV is generated and the horizontal / vertical synchronizing signal HV to the image memory 7 is generated.
Address data (image memory address signal M
AD), an image memory control circuit 3 for controlling writing / reading of the image memory 7 based on the horizontal / vertical synchronization signal HV from the synchronization signal generation circuit 6, and image data. And an image input / output circuit 8 including an analog / digital (A / D) converter and a digital / analog (D / A) converter for inputting / outputting.

In this basic configuration, the sync signal generation circuit 6 generates the horizontal / vertical sync signal HV and the image memory address signal MAD, and the sync signal generation circuit 6 is generated.
The horizontal / vertical synchronizing signal HV from the above is sent to the image memory control circuit 3 and also supplied to the image input / output circuit 8, and further, via the image input / output circuit 8, the terminal 2
It is also supplied to the video camera 30 and the monitor 31 connected to 1 and 22. The image memory address signal MAD is
In synchronization with the horizontal / vertical synchronization signal HV, the image data and the address of the image memory 7 in which the image data is stored are controlled so as to be uniquely determined.

The image memory control circuit 3 also generates a control signal MC, which will be described later, necessary for reading and writing the contents of the image memory 7. Further, based on the control signal MC from the image memory control circuit 3 and the image memory address signal MAD from the synchronizing signal generating circuit 6, the image data written in or read out from the image memory 7 is stored in the image data bus. The data is transferred to and from the image input / output circuit 8 via 19, and is also transmitted / received to / from another image processing circuit 20 and the like via the terminal 23.

Here, each image processing circuit board 2 of this embodiment
In addition to the basic configuration described above, reference numeral 0 indicates the synchronization signal reset control means, as will be described later, of the synchronization signal control circuit 1
And a master / slave control circuit 2 as a discriminating means,
Buffers 4 and 5 as first and second gate means are added.

In order to make the description easy to understand, the image processing circuit board on the transmitting side when transmitting and receiving a signal is the master board 20 _M, and the image processing circuit board on the receiving side is the slave board 20 _S.

The sync signal control circuit 1 is a circuit for generating a sync reset signal RS based on a transfer start signal TR supplied from an external CPU (external CPU substrate) via a terminal 9.

Further, the master / slave control circuit 2
Is a discriminating means for discriminating between the master substrate 20 _{M serving as a} transmitting side and the slave substrate 20 _{S serving as a} receiving side. Specifically, for example, a master signal supplied from an external CPU via a terminal 10. Based on the slave signal SL supplied via the MA or the terminal 11, it is determined whether it is the transmission side (master side) or the reception side (slave side), which will be described later according to this determination operation. The buffer control signals CA and CB are output. Furthermore, the master / slave control circuit 2 is a board (master board 20 _M ) on the side where each image processing circuit board 20 sends an image, or a board (on the receiving side) when the image is transferred between the boards. The operation of reading or writing the contents of the image memory 7 in each of the circuit boards 20 differs depending on whether it is the slave board 20 _S ). A designating signal DI) designating read / write is also generated. This designation signal DI is sent to the image memory control circuit 3 and therefore the image memory control circuit 3
Generates the control signal MC based on the designation signal DI.

Buffer 4 as the first gate means
Is supplied with the synchronous reset signal RS output from the synchronous signal control circuit 1 and operates based on the determination signal (buffer control signal CA) from the master / slave control circuit 2 Buffer control signal CA
Is a signal indicating the receiving side (slave side), the output of the supplied synchronous reset signal RS is limited, and the buffer control signal CA indicates that the transmitting side (master side). If it is a signal shown, the current period reset signal RS is passed. From this, the buffer control signal CA from the master / slave control circuit 2 is set to enable / disable the buffer 4.
It becomes a signal for controlling disable.

Buffer 5 as the second gate means
Operates based on the determination signal (buffer control signal CB) from the master / slave control circuit 2 and the buffer control signal CB is a signal indicating that it is the transmission side (master side). When the synchronous reset signal RS supplied through the buffer 4 is passed, and when the buffer control signal CB is a signal indicating the receiving side (slave side) on the contrary, the signal is passed through the terminal 24. The synchronous reset signal RS sent from another image processing circuit board (master board 20 _M ) is passed, and the output terminal is connected to the input terminal of the synchronous signal generating circuit 6. From this, the buffer control signal CB
Is a signal for controlling enable / disable of the buffer 5.

From the above, when the image processing circuit board is the master board 20 _M , the synchronous reset signal RS from the buffer 4 is sent to the synchronous signal generating circuit 6 via the buffer 5. The sync signal generator 6 is sent to reset the horizontal / vertical sync signal HV and the image memory address signal MAD, and
The signal is also sent from the terminal 24 to the terminal 24 of another image processing circuit board 20 (slave board 20 _S ). When the image processing circuit board is the slave board 20 _S , the sync reset signal RS sent from the master board 20 _M via the terminal 24 is sent to the sync signal generating circuit 6 via the buffer 5. Then, the synchronization signal generating circuit 6 of the slave substrate 20 _S is reset.

In other words, the procedure for transferring image data in the apparatus of this embodiment is as follows.

First, from the external CPU, the master substrate 2
0_MIs transmitted to the slave board 20._SOn
The slave signal SL is supplied. The slave board
20 _SYou can specify multiple boards as
For the sake of simplicity, the case where the number of slave boards is one is explained.
To do.

That is, in the master substrate 20 _M , the designation signal DI output from the master / slave control circuit 2 in response to the master signal MA is sent to the image memory control circuit 3 so that the image memory 7 read operations are designated. Further, the buffer 4 is controlled by the buffer control signals CA and CB output from the master / slave control circuit 2 in response to the master signal MA.
And 5 are enabled, whereby the synchronous reset signal RS from the synchronous signal control circuit 9 is supplied to the synchronous signal generating circuit 6 and also from the terminal 24 to the external board (slave board 20 _S ). Supplied.

On the other hand, on the slave substrate 20 _S side, the specified signal ID from the master / slave control circuit 2 according to the slave signal SL is the image memory control circuit 3 as described above.
To the image memory 7, the write operation to the image memory 7 is designated. Further, the buffer 4 is disabled by the buffer control signals CA and CB output from the master / slave control circuit 2 in response to the slave signal SL, and the buffer 5 by the buffer control signal CB.
Is enabled. As a result, the slave board 2
The synchronization reset signal RS from the outside, that is, the master substrate 20 _M via the terminal 24 is supplied to the synchronization signal generation circuit 6 of 0 _S.
Will be supplied.

At this time, the transfer start signal TR is supplied from the external CPU to the sync signal control circuit 6 of the master substrate 20 _M , so that the sync signal control circuit 1 starts the transfer start as described above. The synchronous reset signal RS corresponding to the signal TR is generated, whereby the synchronous signals RS of both the master / slave boards are reset at the same time, so that both can be synchronized in the same phase. In this state, the image memory 7 of the master substrate 20 _M is sequentially read out, and this is read via the image data bus 19 to the slave substrate 2
Supplied to the 0 _S side. On the other hand, on the slave substrate 20 _S side, since the writing operation to the image memory 7 is being performed at the same time, the transfer of the image can be realized.

The image processing apparatus of this embodiment is composed of a plurality of image processing circuit boards 20 as described above, and
Large-scale image processing can be performed by transmitting and receiving signals between these image processing circuit boards 20.

As described above, the image processing apparatus of this embodiment
The address is determined by the signal synchronized with the video signal
Between the image processing circuit boards 20 having the image memory 7
Image processing circuit, which is a device capable of transferring image data of
In addition to the board 20, for example, a CPU circuit board (external CPU)
Use the CPU circuit board between the image processing circuit boards 20.
The image on the side that controls the transfer of the image and transfers the image data
Processing circuit board (master board 20_M) Has its own circuit board
Circuit board on the transfer side (slave board 20 _S) All
Reset all horizontal / vertical sync signals HV
It is a thing. That is, according to the device of this embodiment, each circuit
A reset circuit for the horizontal / vertical synchronization signal HV
Each signal can be
When transferring image data between the image processing circuit boards 20,
Improves image transfer speed and allows multiple circuit boards to be
It is also possible to transfer image data to the circuit board at the same time.
It

According to the image processing apparatus of this embodiment, the synchronization signals HV of both master and slave are reset at the same time,
Since the signals have the same phase and are synchronized with each other, the image transfer time can be shortened as compared with the conventional device that determines the transfer timing by another method. Further, since a plurality of boards 20 _S on the slave side can be designated at the same time, image data can be transferred to a plurality of image processing circuit boards at the same time.

[0030]

As is apparent from the above description, in the image processing apparatus according to the present invention, each of the plurality of image processing circuit boards (image processing blocks) constituting the apparatus has a synchronization signal for resetting the synchronization signal. By having a reset control means and resetting the synchronization signals of all the image processing circuit boards involved in the transmission / reception of this signal, it is possible to shorten the image transfer time, and It becomes possible to transfer image data to a plurality of image processing circuit boards at the same time.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a schematic configuration of one image processing circuit board of an image processing apparatus according to an embodiment of the present invention.

[Explanation of symbols]

 1 ... Synchronization signal control circuit 2 ... Master / slave control circuit 3 ... Image memory control circuit 4, 5 ... Buffer 6 ... Synchronization signal generation circuit 7 ... ... Image memory 8 ... Image input / output circuit 19 ... Image data bus 20 ... Image processing circuit board 30 ... Video camera 31 ... Monitor RS ... Synchronous reset signal HV ... Horizontal / vertical synchronous signal MAD ... Image memory address signal CA, CB ... Buffer control signal DI ... Designation signal MC ... Control signal

Claims (1)

[Claims] 1. A plurality of image processing blocks for performing arbitrary image processing based on a synchronization signal are arranged, and
An image processing apparatus for transmitting and receiving a signal between each image processing block, wherein each image processing block has a synchronization signal reset control means for resetting the synchronization signal, and when transmitting and receiving the signal, the synchronization signal An image processing apparatus characterized in that reset control means resets the synchronization signals of all image processing blocks involved in transmission and reception of the signal.