JPH05298388A - Method for forming test vector - Google Patents

Abstract

PURPOSE:To easily form a test vector after changing a design. CONSTITUTION:Design specification 1 is supplied to a logical value computing part 2 and logical specification 3 is extracted from the computing part 2. On the other hand, the design specification 1 is supplied also to a hardware specification processing part 4 and a hardware-like specifiction 5 to be used for developing a circuit to hardware is extracted from the processing part 4. Then these specifications 3, 5 are supplied to a test vector forming part 6. A test vector 7 is outputted from the forming part 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test vector generation method applied when generating a test vector of an automatically synthesized circuit, for example.

[0002]

2. Description of the Related Art First, a general circuit design method will be described with reference to FIG. That is, in the figure, when the design specifications are determined in step [31], step [3
The theoretical verification is performed in 2]. Further step [33]
It is determined whether the circuit is feasible or not, and if it is not feasible (NO), the theoretical verification of step [32] is repeated.

When it becomes feasible in step [33] (YES), the circuit is designed in step [34]. Further, a circuit test vector is generated in step [35], and a simulation is performed in step [36]. Furthermore, the result of the simulation is judged in step [37], and the result matches the test vector (O
In the case of K), the determination is YES and the work is ended in step [38].

On the other hand, if the result in step [37] does not match the test vector (NO), step [3
4] Returning to [35], the circuit design is performed again, and the test vector of the circuit is generated again. Then, in this step, the result of the simulation is O in step [37].
Repeated until K (YES).

By the way, in such a circuit design method, the test vector generated in step [35] is
For example, it is a data file in which the vector given to the input of the circuit and the expected value output after the throughput delay of the circuit are arranged in time series. Therefore, this test vector contains not only the theoretical value of the circuit, but also many constraints when the circuit is implemented in hardware, such as the bit width of the input / output signal of the circuit, the signal form, and the throughput / delay of the circuit. ing.

Therefore, in order to generate a test vector in the conventional design method, for example, as shown in FIG. 4, the design specification 41 determined in the above step [31] is supplied to the test vector generation unit 42. Then, the test vector 43 is taken out from the test vector generation unit 42.

However, when the test vector is generated by such a method, if the design specification 41 is changed, for example, the generation of the test vector must be restarted from the beginning. For this reason, conventionally, it has been impossible to easily generate the test vector after the design change, which has been an obstacle to the design change. This is especially true when the result in step [37] above does not match the test vector (N
In (O), the design cannot be easily changed, and the work efficiency of the circuit design is significantly deteriorated.

Further, when the generation of the test vector is recreated, all related programs must be changed, which is wasteful. Furthermore, since a lot of information is required when creating the test vector, the processing is complicated, inefficient, and inaccurate. This application is made in view of such a point.

[0009]

The problem to be solved is that the test vector after design change cannot be easily generated, which is an obstacle to the design change.

[0010]

The present invention provides a first theoretical specification that is determined according to the theoretical function of a circuit (design specification 1).
(2, 3) and the second calculation step (4, 5) of the hardware specification determined according to the hardware function of the circuit are provided independently of each other, and This is a test vector generation method in which the results obtained in the second calculation process are combined to generate the test vector of the circuit (6, 7).

[0011]

According to this, it is possible to easily generate the test vector after the design change.

[0012]

[Embodiment] In FIG. 1, a design specification 1 is a theoretical value calculation unit 2
The theoretical specifications 3 are extracted from the theoretical value calculation unit 2. Further, the design specification 1 is supplied to the hardware specification processing unit 4, and the hardware specification 5 when the circuit is implemented in the hardware is taken out from the specification processing unit 4.

Further, the theoretical specifications 3 and the hardware specifications 5 are supplied to the test vector generator 6. Then, from this test vector generation unit 6 to the test vector 7
Is taken out.

That is, in this method, for example, when there is a functional specification 100 of "× 2" as shown in A of FIG. 2, a theoretical specification is applied to an input vector of "5" (= "0101"). The output vector of 3 is “10” (=
"1010").

Therefore, when the first hardware specification 51 is as shown in B of FIG. 2, the test vector 71 at this time is as shown in C of FIG. On the other hand, the second hardware specification 52 is, for example, D in FIG.
Test vector 7 at this time
2 is as shown by E in the figure.

In this case, the input value "0101" indicated by the address 1 of the test vector 71 and the input values "0""1""0""1 indicated by the addresses 1 to 4 of the test vector 72. Is the same value, and the output value "10" shown at address 5 of the test vector 71
10 "is the same value as the output value" 1 "" 0 "" 1 "" 0 "indicated by addresses 9 to 12 of the test vector 72. That is, the theoretical specification 3 is the same, and the Only the wear specification 5 has been changed.

Therefore, in this method, the theoretical value calculation unit 2
The theoretical specification 3 extracted from the above is used as it is, an operation for extracting the hardware specification 5 from the specification processing unit 4 and an operation for supplying the hardware specification 5 to the test vector generation unit 6 and extracting the test vector 7 You only have to do new.

Thus, according to the above apparatus, it is possible to easily generate the test vector after the design change.

Further, according to the above-mentioned apparatus, even when the test vector generation is recreated, only a part of the program needs to be changed, and the waste is reduced. Further, the amount of information to be considered when creating the test vector is reduced, the processing is simple and efficient, and the error of the generated test vector can be reduced.

In the above description, the functional specification 100
Is, for example, “× 2”, but is actually applied to a circuit that performs extremely complicated arithmetic operations such as Galois field arithmetic in error correction of transmission of digital signals. The theoretical specification 3 taken out is extremely complicated.

The above method can be effectively used even when a part of the apparatus is changed due to version up or the like.

[0022]

According to the present invention, it becomes possible to easily generate a test vector after design change.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an example of a test vector generation method according to the present invention.

FIG. 2 is a diagram for explaining the explanation.

FIG. 3 is a flow chart of circuit design.

FIG. 4 is an explanatory diagram of a conventional test vector generation method.

[Explanation of symbols]

 1 Design Specification 2 Theoretical Value Calculation Section 3 Theoretical Specification 4 Hardware Specification Processing Section 5 Hardware Specification 6 Test Vector Generation Section 7 Test Vector

Claims (1)

[Claims] 1. A first calculation process of a theoretical specification determined according to a theoretical function of a circuit and a second calculation process of a hardware specification determined according to a hardware function of the circuit. A test vector generating method, which is provided independently of each other and combines the results obtained in the first and second operation steps to generate a test vector for the circuit.