JPH05298182A - Cache memory - Google Patents

Abstract

PURPOSE:To make it possible to unnecessitate an ECC correction circuit, to reduce quantity of hardware and to improve processing speed for eliminating the ECC correction circuit of a low-order address register by comparing the read data from an address array as it is an ECC code without performing the error correction of the data. CONSTITUTION:In a cache memory where error correction codes are used for address array parts 31 to 3n, an ECC coding is performed for the high-order part of a main memory address for which a memory access request is performed by an ECC generation circuit 90, and the read data from the address arrays 31 to 3n and the ECC coded data are directly compared by the byte unit of the error correction code by a byte comparator 41. As a result, when a noncoincidence does not exist or the noncoincidence of the number of byte at a range where a correction is possible to be performed by the error correction code exists, a cache hit signal is outputted from noncoincidence number of byte decision circuits 5 1 to 5n.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory, and more particularly to a cache hit determination method when an error correction code is used in an address array.

[0002]

2. Description of the Related Art Before describing a conventional cache memory using an error correction code in an address array section, first, a brief description will be given of the cache memory and the error correction code.

A cache memory in which a part of main memory data is held in a high-speed memory and an apparent average memory access time is shortened is generally a data array section that holds a part of main memory data and a data array section. An address array unit that holds the address of the data held by the main memory in the main memory, and an address comparison unit that determines whether or not a memory access requested address (hereinafter referred to as the target address) is registered in the address array. Etc.

When a memory access request is issued, the address array is referred to in order to check whether it is registered in the target address cache memory. When the target address is registered in the address array (hereinafter referred to as cache hit), the data in the data array is read or updated. When the target address is not registered in the address array (hereinafter referred to as cache miss), the corresponding address is registered in the address array, the main memory is accessed, and the data at the corresponding address is loaded into the data array.

Error correction code (Error Correc)
(Ting Code, hereinafter abbreviated as ECC), by providing redundancy in a code, even if an error occurs in a part of the code, if the error is minor, the occurrence of the error is detected and the error is detected. It is a code configured so that the influence can be removed and the original correct code can be corrected. Generally, the larger the redundancy, the larger the range of correctable errors. A data unit for error correction is called "byte". As an application of the error correction code to a storage device, for example, one code is divided into a large number of memory elements and stored, and a memory element is made to correspond to a byte. By using an error correction code that can reproduce the original contents from the contents of the memory element, the effect of the failure can be removed unless a plurality of memory elements fail at the same time.

Next, a conventional cache memory using an error correction code in the address array section will be described.

The address array unit and the address comparison unit of the cache memory using the error correction code in the conventional address array unit are generally constructed as shown in FIG. The address register is composed of an upper address register 10 and a lower address register 20, and the upper part and the lower part of the target address are set therein. The upper address register 10 has an ECC generation circuit 90.
Are connected. Address arrays 31, 32, ...
The upper address registered in 3n is ECC encoded.
The number of address arrays 31, 32, ..., 3n is the same as the number of data arrays (n), and the upper part of the address in the main memory of the data held in each data array is ECC encoded. Hold it in the open state. EC
The C correction circuits 91, 92, ..., 9n correct if there is an error in the upper address portion held by the address arrays 31, 32 ,. The address obtained by synthesizing the upper address part held in the address array and the lower address part set in the lower address register becomes the address in the main memory of the data stored in the data array. Bit comparators 41a, 42
a, ..., 4na are ECC correction circuits 91, 92, ...
.., 9n is output, and the address (upper part) of the data held in the data array in the main memory is compared with the upper part of the target address set in the upper address register 10 bit by bit. Perfect match determination circuit 51
a, 52a, ..., 5na are comparators 41a,
42a, ..., 4na, the cache hit signals 61, 62, ...
.., 6n is output.

Next, the operation of the cache memory thus constructed will be described.

When a memory access request is issued, the target address is set in the upper address register 10 and the lower address register 20. Lower address register 2
According to the contents of 0, address arrays 31, 32, ...
.., 3n, the upper part of the address in the main memory of the data held by the data array is read in the ECC encoded state. The upper part of the address is corrected by the ECC correction circuits 91, 92, ..., 9n and sent to the bit comparators 41a, 42a ,. It is compared bit by bit with the part. Bit comparators 41a, 4
2a, ..., 4na, if there is a complete match of all bits, the corresponding perfect match determination circuits 51a, 5a
Cache hit signal 61 from 2a, ..., 5na,
62, ..., 6n are output, and the data in the corresponding data array is accessed. If none of the bits completely match, a cache miss occurs and the main memory is accessed. When the data is returned from the main memory, it is loaded into one of the data arrays and the target address (upper part) is registered in the corresponding address array.

[0010]

The above-described conventional cache memory has the address arrays 31, 32, ... 3n.
The read data from the ECC correction circuits 91, 92, ...
The cache hit is judged after correction in 9n. Therefore, the same number of ECC correction circuits as the address array are required, and the amount of hardware increases. Further, the path from the lower address register 20 to the cache hit signals 61, 62, ... 6n is often a critical path in terms of the performance of the cache memory, and the ECC correction circuit having a large number of logical stages reduces the processing speed. Let Further, since the memory device with the comparator cannot be used, not only the amount of hardware increases but also the processing speed decreases.

[0011]

A cache memory using an error correction code in an address array unit according to the present invention has an upper portion of a main memory address for which a memory access request is issued, which is E.
The first means for CC encoding, the second means for directly comparing the read data from the address array and the ECC code obtained by the first means in byte units of the error correction code, and as a result, they do not match. Or a third means for outputting a cache hit signal if the number of bytes in the correctable range of the error correction code does not match.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.
The address register is composed of an upper address register 10 and a lower address register 20, and the upper part and the lower part of the target address are set respectively. EC
The C generation circuit 90 uses the ECC for the upper part of the target address.
Encode. The ECC-encoded upper address is output to the address arrays 31, 32, ..., 3n and the byte comparators 41, 42 ,. The number of address arrays 31, 32, ..., 3n is the same as the number of data arrays (n), and the upper part of the address in the main memory of the data held in each data array is
It is held in the ECC encoded state. Byte comparator 4
1, 42, ..., 4n are address arrays 31, 32,
..., 3n output, that is, the upper part of the address in the main memory of the data held in the data array (ECC
The encoded data) and the output of the ECC generation circuit 90, that is, the upper part of the target address (ECC encoded data) are directly compared in byte units of the error correction code.
Here, the “byte” does not necessarily have to be a plurality of bits and may be composed of 1 bit. .., 5n, the comparison results of the byte comparators 41, 42 ,. If the number of bytes in the range does not match, the cache hit signals 61, 62, ..., 6n are output.

Next, the operation of the cache memory thus constructed will be described.

When a memory access request is issued, the target address is set in the upper address register 10 and the lower address register 20. Lower address register 2
According to the contents of 0, address arrays 31, 32, ...
.., 3n, the upper part of the address in the main memory of the data held by the data array is read in the ECC encoded state. The read upper part of the address (ECC encoded) is the byte comparator 41, 4
2, ..., 4n, and compared with the upper part (ECC encoded) of the target address in byte units of the error correction code. The comparison result in units of bytes is sent to the non-coincidence byte number determination circuits 51, 52, ... 5n, and all the bytes are completely coincident or the number of bytes in the correctable range of the error correction code is not coincident. For example, the cache hit signals 61, 62, ..., 6n are output. When any of the cache hit signals 61, 62, ..., 6n is output, the data in the corresponding data array is accessed. If the number of bytes does not match the correctable range of the error correction code, the cache hit signal is not output. If no cache hit signal is output, a cache miss occurs and the main memory is accessed. When data is returned from main memory,
It is loaded into one of the data arrays and the upper part of the desired address is registered in the corresponding address array.

[0016]

As described above, according to the present invention, the read data from the address array can be EC-corrected without error correction.
By comparing the C code as it is, the ECC correction circuit becomes unnecessary, and the amount of hardware can be reduced.
Further, since the ECC correction circuit is eliminated from the critical path from the lower address register to the cache hit signal, the processing speed can be improved. further,
If the memory device with the comparator is used, the address array and the byte comparator can be configured by the same device, so that the speed can be further increased.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional cache memory.

[Explanation of symbols]

 10 High-order address register 20 Low-order address register 31, 32, ..., 3n address array 41, 42, ..., 4n byte comparator 41a, 42a, ..., 4na bit comparator 51, 52 ,. , 5n non-matching byte number judging circuit 51a, 52a, ..., 5na perfect match judging circuit 61, 62, ..., 6n cache hit signal 90 ECC generation circuit 91, 92, ..., 9n ECC correction circuit

Claims (1)

[Claims] 1. In a cache memory using an error correction code in an address array section, first means for ECC-encoding the upper portion of a main memory address for which a memory access request is made, read data from an address array, and Second means for directly comparing the ECC code obtained by the first means with the byte unit of the error correction code, and, as a result,
A cache memory comprising: a third means for outputting a cache hit signal if there is no mismatch or if there is a mismatch in the number of bytes in the correctable range of the error correction code at most.