JPH0529537A - Semiconductor module structure - Google Patents
Semiconductor module structureInfo
- Publication number
- JPH0529537A JPH0529537A JP3179719A JP17971991A JPH0529537A JP H0529537 A JPH0529537 A JP H0529537A JP 3179719 A JP3179719 A JP 3179719A JP 17971991 A JP17971991 A JP 17971991A JP H0529537 A JPH0529537 A JP H0529537A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- chip
- connection pads
- substrate
- substrates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体回路の形成され
た半導体チップを複数個モジュール化して、高密度に実
装する半導体モジュール構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor module structure in which a plurality of semiconductor chips having semiconductor circuits are modularized and mounted at high density.
【0002】近年、電子機器の小型化、高機能化のた
め、複数個の半導体チップを一つの配線基板上に搭載し
てモジュール化することにより、電子機器のマザーボー
ド上に高密度に実装することが行われているが、複数の
半導体チップを配線基板を介して接続してモジュール化
するため、半導体チップ間を平面的に配置する配線基板
をあまり小さくできず、より高密度に半導体チップを実
装することのできる半導体モジュール構造が求められて
いる。In recent years, in order to reduce the size and increase the functionality of electronic devices, a plurality of semiconductor chips are mounted on one wiring board to form a module, so that the electronic devices can be mounted on a motherboard at a high density. However, because a plurality of semiconductor chips are connected via a wiring board to form a module, the wiring board that lays out the semiconductor chips in a plane cannot be made very small, and the semiconductor chips are mounted at a higher density. There is a need for a semiconductor module structure that can do this.
【0003】[0003]
【従来の技術】従来、半導体モジュール構造としては、
図5に示すように、樹脂やセラミック基材等に配線パタ
ーンをプリントしてなるモジュール基板10上に、シリ
コン基板上に半導体回路を形成してなる半導体チップ2
0を、半田パンプやホンディングワイヤ等により接続し
て、複数個搭載し、半導体チップ20をシールキャップ
30や樹脂コートで保護して、半導体モジュールを構成
していた。そして、マザーボード40上には、モジュー
ル基板10に形成された外部接続リード110によって
接続するようになっていた。2. Description of the Related Art Conventionally, as a semiconductor module structure,
As shown in FIG. 5, a semiconductor chip 2 formed by forming a semiconductor circuit on a silicon substrate on a module substrate 10 formed by printing a wiring pattern on a resin or ceramic base material.
A plurality of 0s are connected by a solder pump or a bonding wire, a plurality of them are mounted, and the semiconductor chip 20 is protected by a seal cap 30 or a resin coat to form a semiconductor module. The external connection leads 110 formed on the module substrate 10 are connected to the mother board 40.
【0004】[0004]
【発明が解決しようとする課題】しかしながら、従来の
半導体モジュール構造では、モジュール基板10上に半
導体チップ20を平面的に配置して、それぞれ半導体チ
ップ20間をモジュール基板10上にプリントされた配
線パターンで接続するものであるから、半導体チップ2
0、20、…の搭載部と配線パターンの形成部がモジュ
ール基板10上に必要であり、モジュール基板10の面
積を十分小さくすることができないという欠点があっ
た。However, in the conventional semiconductor module structure, the semiconductor chips 20 are two-dimensionally arranged on the module substrate 10, and the wiring patterns printed on the module substrate 10 between the respective semiconductor chips 20. The semiconductor chip 2 is connected by
There is a drawback that the mounting portions of 0, 20, ... And the wiring pattern forming portion are required on the module substrate 10, and the area of the module substrate 10 cannot be sufficiently reduced.
【0005】本発明は、以上の欠点を解消すべくなされ
たものであって、複数の半導体チップをモジュール基板
上に平面的に配置することなく、実装面積を小さくし
て、小型かつ高密度な半導体モジュール構造を提供する
ことを目的とするものである。The present invention has been made in order to solve the above-mentioned drawbacks, and it is possible to reduce the mounting area, reduce the size, and increase the density without arranging a plurality of semiconductor chips in a plane on the module substrate. An object of the present invention is to provide a semiconductor module structure.
【0006】[0006]
【課題を解決するための手段】本発明を実施例に対応す
る図1ないし図3に基づいて説明すると、半導体回路2
を形成したチップ基板1の表面11および裏面12に
は、それぞれ配線パターン3および接続パッド4を形成
している。さらに、チップ基板1には表裏面11、12
間を貫通して表裏面の配線パターン3、3を接続するビ
アホール5を形成している。そして、複数の前記チップ
基板1の表面側の接続パッド4上に上段のチップ基板1
の裏面側の接続パッド42を重ねて多段に接続して形成
する。The present invention will be described with reference to FIGS. 1 to 3 corresponding to an embodiment. A semiconductor circuit 2 will be described.
Wiring patterns 3 and connection pads 4 are formed on the front surface 11 and the back surface 12 of the chip substrate 1 on which the wiring patterns 3 are formed. Further, the chip substrate 1 has front and back surfaces 11, 12
Via holes 5 are formed penetrating through the space and connecting the wiring patterns 3 and 3 on the front and back surfaces. Then, the upper chip substrate 1 is formed on the connection pads 4 on the front surface side of the plurality of chip substrates 1.
The connection pads 42 on the back side of the above are overlapped and connected in multiple stages.
【0007】[0007]
【作用】上記構成に基づき、本発明においては、チップ
基板1の表裏面11、12間を貫通するビアホール5に
より表裏面の配線パターン3、3および接続パッド4、
4を接続しているため、チップ基板1を複数枚上下に積
み重ねて、下段側の表面部接続パッド4と、積み重ねら
れる上段側の裏面部接続パッド4とを半田等により接続
することによって半導体モジュールを構成することがで
きるため、半導体チップをモジュール化して接続するた
めの配線基板が不要となり、かつ上下に積み重ねること
により、マザーボードへの実装面積を一つのチップ基板
の大きさにして、装置の小型化を図ることができ、高密
度化が可能となる。According to the present invention, the wiring patterns 3 and 3 on the front and back surfaces and the connection pads 4 are formed by the via holes 5 penetrating between the front and back surfaces 11 and 12 of the chip substrate 1 in the present invention.
4 are connected to each other, the plurality of chip substrates 1 are vertically stacked, and the lower surface side connection pads 4 and the upper surface side back surface connection pads 4 to be stacked are connected by soldering or the like. Since the wiring boards for connecting the semiconductor chips into modules are not required, and by stacking them on top of each other, the mounting area on the motherboard can be reduced to the size of a single chip board, thus reducing the size of the device. It is possible to achieve higher density and higher density.
【0008】[0008]
【実施例】以下、本発明の望ましい実施例を添付図面に
基づいて詳細に説明する。図1および図2は本発明の半
導体モジュールを構成する半導体素子のチップ基板1を
示すものであり、図3は複数のチップ基板1、1、…を
マザーボード6上に多段に積み重ねて形成された半導体
モジュールAを示すものである。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings. 1 and 2 show a chip substrate 1 of a semiconductor element that constitutes a semiconductor module of the present invention, and FIG. 3 is formed by stacking a plurality of chip substrates 1, 1, ... 1 shows a semiconductor module A.
【0009】図1に示すように、チップ基板1は半導体
回路2を形成するシリコン基板であり、表面11には、
半導体回路2が形成されている。そして、チップ基板1
には表面11と裏面12とを貫通して導通させるビアホ
ール5を形成している。As shown in FIG. 1, a chip substrate 1 is a silicon substrate for forming a semiconductor circuit 2, and a surface 11 has a
The semiconductor circuit 2 is formed. And the chip substrate 1
A via hole 5 that penetrates the front surface 11 and the rear surface 12 to establish electrical conduction is formed therein.
【0010】チップ基板1の表裏面11、12にはそれ
ぞれ対応する位置に接続パッド4、4が形成されてお
り、半導体回路2と接続パッド4とを接続するように配
線パターン3が形成されている。そして、表裏面11、
12にそれぞれ形成される配線パターン3、3は図2に
示すようにビアホール5によって導通している。Connection pads 4 and 4 are formed on the front and back surfaces 11 and 12 of the chip substrate 1 at corresponding positions, and a wiring pattern 3 is formed to connect the semiconductor circuit 2 and the connection pad 4. There is. And the front and back surfaces 11,
The wiring patterns 3 and 3 respectively formed in 12 are electrically connected by the via holes 5 as shown in FIG.
【0011】そして、チップ基板1は図3に示すように
複数枚重ねてマザーボード6上に搭載されるもので、最
下段のチップ基板1の裏面12に形成されている接続パ
ッド4をマザーボード6の接続パッド61に半田7や導
電接着剤等によって固定される。そして、チップ基板1
の表面側の接続パッド4には同様にして上段のチップ基
板1の裏面側接続パッド42を固定して、多段に積み重
ねられ、全体を樹脂コーティング8によって保護するよ
うに搭載されている。As shown in FIG. 3, a plurality of chip substrates 1 are stacked and mounted on the mother board 6, and the connection pads 4 formed on the back surface 12 of the lowest chip substrate 1 are connected to the mother board 6. It is fixed to the connection pad 61 with solder 7 or a conductive adhesive. And the chip substrate 1
Similarly, the back surface side connection pads 42 of the upper chip substrate 1 are fixed to the front surface side connection pads 4 and stacked in multiple stages, and the whole is mounted so as to be protected by the resin coating 8.
【0012】次にチップ基板1の製造工程について説明
すると、まず、図4(a)に示すように、シリコン基板
13にレーザやエッチング等によって孔加工を行い表面
に酸化シリコン膜14を形成する。そして、半導体作成
プロセスによって半導体を形成し、アルミニウム蒸着、
リソグラフィにより半導体回路2を形成する。Next, the manufacturing process of the chip substrate 1 will be described. First, as shown in FIG. 4A, a hole is formed in the silicon substrate 13 by laser or etching to form a silicon oxide film 14 on the surface. Then, a semiconductor is formed by a semiconductor manufacturing process, aluminum vapor deposition,
The semiconductor circuit 2 is formed by lithography.
【0013】次に、図4(b)に示すようにチップ基板
1の表裏面11、12にイミドスピンコート等により絶
縁層15を形成し、焼付、現像によってビアホール5を
露出させる。そして、メタル蒸着、エッチングによって
ビアホール5、接続パッド4を接続する配線パターン3
を絶縁層15上に形成してチップ基板1を形成するもの
である。Next, as shown in FIG. 4B, an insulating layer 15 is formed on the front and back surfaces 11 and 12 of the chip substrate 1 by imide spin coating or the like, and the via hole 5 is exposed by baking and developing. Then, the wiring pattern 3 for connecting the via hole 5 and the connection pad 4 by metal deposition and etching.
Is formed on the insulating layer 15 to form the chip substrate 1.
【0014】[0014]
【発明の効果】以上説明したように、本発明において
は、半導体回路を形成したチップ基板の表裏面に配線パ
ターンをビアホールで接続して設け、表裏面の接続パッ
ドでチップ基板を多段に積み重ねて、半導体モジュール
を形成するため、チップ基板をモジュール化する配線基
板が不要となり、マザーボードへの搭載面積を小さくし
て、高密度な実装が可能となる。As described above, in the present invention, the wiring patterns are provided on the front and back surfaces of the chip substrate on which the semiconductor circuit is formed by connecting via holes, and the chip substrates are stacked in multiple stages by the connection pads on the front and back surfaces. Since a semiconductor module is formed, a wiring board for modularizing a chip substrate is not required, and a mounting area on a mother board can be reduced to enable high-density mounting.
【図1】本発明の実施例を示す説明図である。FIG. 1 is an explanatory diagram showing an embodiment of the present invention.
【図2】本発明の断面を示す説明図である。FIG. 2 is an explanatory view showing a cross section of the present invention.
【図3】本発明の搭載状態を示す説明図である。FIG. 3 is an explanatory diagram showing a mounting state of the present invention.
【図4】本発明の実施例の製造工程を示す説明図であ
る。FIG. 4 is an explanatory diagram showing a manufacturing process according to the embodiment of the present invention.
【図5】従来例を示す説明図である。FIG. 5 is an explanatory diagram showing a conventional example.
1 チップ基板 11 表面 12 裏面 2 半導体回路 3 配線パターン 4 接続パッド 5 ビアホール 1 chip substrate 11 front surface 12 back surface 2 semiconductor circuit 3 wiring pattern 4 connection pad 5 via hole
Claims (1)
の表面(11)および裏面(12)に配線パターン(3) と接続パ
ッド(4) をそれぞれ形成するとともに、前記表裏面(11、
12) の配線パターン(3、3) をビアホール(5) で接続して
なり、かつ複数の前記チップ基板(1、1、・・)をそれぞれ対
向する表裏面(11、12) の接続パッド(4、4) を介して接続
して積み重ねてなることを特徴とする半導体モジュール
構造。Claims: 1. A chip substrate (1) on which a semiconductor circuit (2) is formed.
The wiring pattern (3) and the connection pad (4) are formed on the front surface (11) and the back surface (12) of the
12) The wiring patterns (3, 3) are connected by via holes (5), and the connection pads (11, 12) on the front and back surfaces (11, 12) facing the chip substrates (1, 1, ...) respectively. 4, 4) A semiconductor module structure characterized by being connected and stacked through.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3179719A JP3016910B2 (en) | 1991-07-19 | 1991-07-19 | Semiconductor module structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3179719A JP3016910B2 (en) | 1991-07-19 | 1991-07-19 | Semiconductor module structure |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0529537A true JPH0529537A (en) | 1993-02-05 |
JP3016910B2 JP3016910B2 (en) | 2000-03-06 |
Family
ID=16070678
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3179719A Expired - Fee Related JP3016910B2 (en) | 1991-07-19 | 1991-07-19 | Semiconductor module structure |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3016910B2 (en) |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6002177A (en) * | 1995-12-27 | 1999-12-14 | International Business Machines Corporation | High density integrated circuit packaging with chip stacking and via interconnections |
JP2002222900A (en) * | 2001-01-26 | 2002-08-09 | Sony Corp | Semiconductor device |
US6962865B2 (en) | 2000-06-02 | 2005-11-08 | Seiko Epson Corporation | Semiconductor device, method of fabricating the same, stack-type semiconductor device, circuit board and electronic instrument |
JP2007019149A (en) * | 2005-07-06 | 2007-01-25 | Seiko Epson Corp | Electronic substrate, manufacturing method thereof and electronic equipment |
US7276738B2 (en) | 2000-07-11 | 2007-10-02 | Seiko Epson Corporation | Miniature optical element for wireless bonding in an electronic instrument |
JP2008160142A (en) * | 2008-01-23 | 2008-07-10 | Sanyo Electric Co Ltd | Semiconductor device, and production method thereof |
JP2009010436A (en) * | 1997-03-10 | 2009-01-15 | Seiko Epson Corp | Electronic component and semiconductor device, and manufacturing method thereof |
JP2009055028A (en) * | 2004-03-26 | 2009-03-12 | Fujikura Ltd | Through wiring board, and method of manufacturing the same |
JP2009141169A (en) * | 2007-12-07 | 2009-06-25 | Shinko Electric Ind Co Ltd | Semiconductor device |
US7745931B2 (en) | 2003-06-09 | 2010-06-29 | Sanyo Electric Co., Ltd. | Semiconductor device and manufacturing method thereof |
JP2011014910A (en) * | 2009-07-06 | 2011-01-20 | Taiwan Semiconductor Manufacturing Co Ltd | Integrated circuit structure |
US8115312B2 (en) | 2004-06-30 | 2012-02-14 | Renesas Electronics Corporation | Semiconductor device having a through electrode |
JP2016171297A (en) * | 2015-03-12 | 2016-09-23 | ソニー株式会社 | Solid-state imaging device, manufacturing method, and electronic device |
-
1991
- 1991-07-19 JP JP3179719A patent/JP3016910B2/en not_active Expired - Fee Related
Cited By (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6002177A (en) * | 1995-12-27 | 1999-12-14 | International Business Machines Corporation | High density integrated circuit packaging with chip stacking and via interconnections |
US6187678B1 (en) | 1995-12-27 | 2001-02-13 | International Business Machines Corporation | High density integrated circuit packaging with chip stacking and via interconnections |
US6236115B1 (en) | 1995-12-27 | 2001-05-22 | International Business Machines Corporation | High density integrated circuit packaging with chip stacking and via interconnections |
JP2009010436A (en) * | 1997-03-10 | 2009-01-15 | Seiko Epson Corp | Electronic component and semiconductor device, and manufacturing method thereof |
US6962865B2 (en) | 2000-06-02 | 2005-11-08 | Seiko Epson Corporation | Semiconductor device, method of fabricating the same, stack-type semiconductor device, circuit board and electronic instrument |
US7102219B2 (en) | 2000-06-02 | 2006-09-05 | Seiko Epson Corporation | Semiconductor device, method of fabricating the same, stack-type semiconductor device, circuit board and electronic instrument |
US7276738B2 (en) | 2000-07-11 | 2007-10-02 | Seiko Epson Corporation | Miniature optical element for wireless bonding in an electronic instrument |
US7879633B2 (en) | 2000-07-11 | 2011-02-01 | Seiko Epson Corporation | Miniature optical element for wireless bonding in an electronic instrument |
US7544973B2 (en) | 2000-07-11 | 2009-06-09 | Seiko Epson Corporation | Miniature optical element for wireless bonding in an electronic instrument |
JP2002222900A (en) * | 2001-01-26 | 2002-08-09 | Sony Corp | Semiconductor device |
US7745931B2 (en) | 2003-06-09 | 2010-06-29 | Sanyo Electric Co., Ltd. | Semiconductor device and manufacturing method thereof |
US8101496B2 (en) | 2003-06-09 | 2012-01-24 | Semiconductor Components Industries, Llc | Method of manufacturing ball grid array type semiconductor device |
JP2009055028A (en) * | 2004-03-26 | 2009-03-12 | Fujikura Ltd | Through wiring board, and method of manufacturing the same |
US8436468B2 (en) | 2004-06-30 | 2013-05-07 | Renesas Electronics Corporation | Semiconductor device having a through electrode |
US8115312B2 (en) | 2004-06-30 | 2012-02-14 | Renesas Electronics Corporation | Semiconductor device having a through electrode |
JP2007019149A (en) * | 2005-07-06 | 2007-01-25 | Seiko Epson Corp | Electronic substrate, manufacturing method thereof and electronic equipment |
JP4572759B2 (en) * | 2005-07-06 | 2010-11-04 | セイコーエプソン株式会社 | Semiconductor device and electronic equipment |
US7746663B2 (en) | 2005-07-06 | 2010-06-29 | Seiko Epson Corporation | Electronic substrate and electronic device |
US8284566B2 (en) | 2005-07-06 | 2012-10-09 | Seiko Epson Corporation | Electronic substrate |
US8416578B2 (en) | 2005-07-06 | 2013-04-09 | Seiko Epson Corporation | Manufacturing method for an electronic substrate |
US9087820B2 (en) | 2005-07-06 | 2015-07-21 | Seiko Epson Corporation | Electronic substrate |
US9496202B2 (en) | 2005-07-06 | 2016-11-15 | Seiko Epson Corporation | Electronic substrate |
JP2009141169A (en) * | 2007-12-07 | 2009-06-25 | Shinko Electric Ind Co Ltd | Semiconductor device |
JP2008160142A (en) * | 2008-01-23 | 2008-07-10 | Sanyo Electric Co Ltd | Semiconductor device, and production method thereof |
JP2011014910A (en) * | 2009-07-06 | 2011-01-20 | Taiwan Semiconductor Manufacturing Co Ltd | Integrated circuit structure |
JP2016171297A (en) * | 2015-03-12 | 2016-09-23 | ソニー株式会社 | Solid-state imaging device, manufacturing method, and electronic device |
Also Published As
Publication number | Publication date |
---|---|
JP3016910B2 (en) | 2000-03-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2996510B2 (en) | Electronic circuit board | |
KR100546374B1 (en) | Multi chip package having center pads and method for manufacturing the same | |
US7889509B2 (en) | Ceramic capacitor | |
US6495912B1 (en) | Structure of ceramic package with integrated passive devices | |
JP2001250911A (en) | Resin-sealed semiconductor device for power | |
JPH081936B2 (en) | Chip carrier and method of manufacturing the same | |
JPH0669402A (en) | Printed-circuit board and its manufacture | |
JP2005150748A (en) | Semiconductor chip package having decoupling capacitor and method for manufacturing same | |
JP3016910B2 (en) | Semiconductor module structure | |
JP2988045B2 (en) | Bare chip structure and bare chip mounting structure | |
JP2001168233A (en) | Multiple-line grid array package | |
JP3158073B2 (en) | Electronic element packaging method and electronic element package | |
JP3656861B2 (en) | Semiconductor integrated circuit device and method for manufacturing semiconductor integrated circuit device | |
JP3450477B2 (en) | Semiconductor device and manufacturing method thereof | |
JP2722451B2 (en) | Semiconductor device | |
JP3024596B2 (en) | BGA type semiconductor device using film carrier tape | |
JP2946361B2 (en) | Substrate for mounting electronic components | |
JP3867875B2 (en) | Semiconductor device | |
JPH0645763A (en) | Printed wiring board | |
JPH0969587A (en) | Bga type semiconductor device and bga module | |
JP2508660Y2 (en) | Semiconductor device | |
JPH0529538A (en) | Semiconductor module structure | |
JPH0231794Y2 (en) | ||
JPH0529532A (en) | Semiconductor module structure | |
KR19980025868A (en) | Metal Ball Grid Array Package |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19990831 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19991214 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071224 Year of fee payment: 8 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081224 Year of fee payment: 9 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091224 Year of fee payment: 10 |
|
LAPS | Cancellation because of no payment of annual fees |