JPH05291262A - Forming method for bump electrode - Google Patents

Abstract

PURPOSE:To provide a simple process and to improve reliability of a semiconductor element by covering an exposed part of a passivation layer and a polyimide layer for protecting a side of a bump electrode. CONSTITUTION:A semiconductor substrate 1 is covered with insulator layers 2, 3, a pad layer 4 is superposed on the layers 2, 3, and passivation layers 5, 6 for burying the pad 4 are formed. Then, a bump electrode 9 having parts passing the layers 5, 6 to connect the pad 4 is formed, and a barrier metal layer 8 for covering the electrode 9 in contact with the layers 5, 6 is mounted. Then, it is covered with the exposed parts of the layers 5, 6 and a polyimide layer 7 for protecting the side of the electrode 9. For example, after a gold bump electrode 9 is mounted by a plating step, it is covered entirely with the layer 7, and then isotropically etched until an uppermost layer of the electrode 9 is observed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a polyimide layer on a semiconductor element, and is particularly suitable for bump electrodes.

[0002]

2. Description of the Related Art As the degree of integration of semiconductor devices has been improved, the assembly process has changed, and so-called bump electrodes have been widely used in addition to the method using a lead frame.
The current situation is that the bump electrodes are being improved.

A semiconductor device using bump electrodes will be described with reference to FIG. 1. For example, a non-doped CVD (Chemical Vapor Drain) is formed on the surface of a semiconductor substrate 1 made of silicon.
epo-sition) Layer 2 and BPSG (Boro Phospho Silicate Glas)
s) A layer 3 is coated and a pad layer 4 made of a conductive metal such as Al or Al alloy ((Al-Si, Al-Si-Cu) is formed on a part of the layer 3. This is built into the semiconductor substrate 1. It goes without saying that the bump electrode 9 is electrically connected to the active element or the passive element, and the bump electrode 9 is formed thereon.

Before and after the explanation, the CVD layer 2 and the BPSG layer 3 are covered with a double layer of a PSG (Phospho Silicate Glass) layer 5 and a silicon nitride layer 6, for example. Since the pad layer 4 on which the metal bump electrode 9 is laminated is embedded in the passivation layer, the barrier metal layer 8 is formed at the contact portion between the two and the bump electrode 9 is fixed by plating. It helps to prevent the migration phenomenon and the like. Although the polyimide layer 7 covers the passivation layer, it is not connected to the metal bump electrodes 9 (see FIG. 1). In addition, the inner electrode 10 is connected to the bump electrode 9 and the mold resin 11 is used to complete the semiconductor device.
The sealing step is performed.

The polyimide layer 7 does not cover the bump electrode 9 or the barrier metal layer 8, as is apparent from FIG.
This is because after the polyimide layer 7 is coated on the entire surface, a patterning process is performed by a known photolithography technique to form an opening in the polyimide layer 7. In addition, this process step is explained by extracting the main ones.
Note that there are many omitted steps.

[0006]

As described above, in forming the bump electrode, a known photolithography technique using an exposure apparatus or the like is indispensable, the process is complicated, and naturally the number of steps is large and the cost is considerable. However, due to its complexity, the frequency of accidents is greater than in simple processes.

In addition to this, since the side wall of the bump electrode is not covered with the polyimide layer 7, it cannot be denied that the reliability of the semiconductor device is lowered. In addition to this, the inner lead 10 and the bump electrode 9 made of metal are formed of a mold resin 11
Because of the stress, the stress causes cracks in the double layer of the PSG layer 5 and the silicon nitride layer 6 that cover the pad layer 4 as an on-passivation layer, and the wiring layer continuous to the pad layer 4 also fails. Occurs.

The present invention has been made under such circumstances, and it is an object of the present invention to provide a method for forming bump electrodes by a simple process.

[0009]

A semiconductor substrate is coated with an insulating layer, a pad layer is overlaid on the insulating layer portion, a passivation layer is formed to fill the pad layer, Forming a bump electrode having a portion connected to the pad layer and penetrating the passivation layer; providing a barrier metal layer covering the bump electrode portion in contact with the passivation layer; and the passivation layer The step of depositing a polyimide layer that protects the exposed portion and the side portion of the bump electrode is characterized by the method for forming the bump electrode according to the present invention.

[0010]

In the present invention, the polyimide film covering the bump electrode made of gold, for example, is subjected to isotropic etching without the exposure device until the upper surface of the bump electrode appears, and the side surface is covered with the polyimide film to form a semiconductor film. Improves device reliability.

Based on the finding that it is very difficult to remove the polyimide film on the side portion when the polyimide film covering the bump electrodes made of gold is subjected to isotropic etching,
The present invention has been completed in which the treatment is carried out until the upper surface of the bump electrode appears.

[0012]

Embodiments of the present invention will be described with reference to FIGS. The semiconductor substrate 1 made of, for example, silicon of the first conductivity type forming the bump electrode according to the present invention,
The passive element or active element is formed by the usual method,
The surface is coated with the CVD film 2 and the BPSG film 3 (see FIG. 2).

On the other hand, the active element and the passive element are made of a conductive metal layer such as Al or Al alloy (Al-Si, Al-Si-C).
u) Electrodes and wiring layers (neither shown) are provided, and the wiring layers are formed on the insulating layer covering the surface of the semiconductor substrate 1.

As shown in FIG. 1, CVD layer 2 and BP
The SG layer 3 is coated with, for example, a double layer of a PSG layer 5 and a silicon nitride layer 6. That is, in the laminated body of the CVD film 2 and the BPSG film 3, Al
Alternatively, the pad electrode 4 made of Al alloy (Al-Si, Al-Si-Cu) is formed by a patterning process using a known photolithography method, and the size is usually 100 μm square to 8 μm.
It is 0 μm square.

In order to prevent the influence of moisture, for example, an On Al passivation layer or insulating layer composed of a PSG layer 5 having a thickness of 0.4 μm and a silicon nitride layer 6 having a thickness of 0.75 μm. The pad electrode 4 is embedded by the step of depositing the physical layer, and subsequently, the deposit portion covering the pad electrode 4 is removed by the patterning step by the well-known photolithography method similarly to the formation of the pad electrode 4 to remove the passivation. A window 12 penetrating the layer is provided to expose the surface of the pad electrode 4. A barrier metal layer 8 is formed on the surface of the pad electrode 4 exposed on the window 12 and on the side portion of the passivation layer to be used for fixing the gold bump electrode 13 in the plating process and prevent migration.

The barrier metal layer 8 has a three-layer structure of titanium, nickel and palladium, and the bump electrode 9 made of gold is used as an electrode for fixing the plating process by the plating process, and both are in a continuous state.

The width of the gold bump electrode 9 is equal to that of the pad electrode 4.
The height is approximately 18 μm, but in each figure, it is noted that it is written in reverse to the width.

After the gold bump electrode 9 is thus installed,
The polyimide layer 7 is entirely covered to form the sectional structure of FIG. Next, isotropic etching is performed until the uppermost layer of the bump electrode 9 made of gold can be seen, and the etching time is determined in advance by the dummy under the same conditions. By this treatment, the bump electrode 9 made of gold with the polyimide layer 7 deposited on the measurement portion A is formed, and the process proceeds to the next step.

In the next step, the bump electrode 9 made of gold is made of copper or copper alloy and has a width of 30 to 40 μm and a thickness of about 35.
An inner lead 10 having a thickness of .mu.m is fixed by a bonding process, and a resin layer 11 is entirely sealed by a transfer molding method to complete a resin-sealed semiconductor element (FIG. 4).
reference).

[0020]

【The invention's effect】

1. In such a bump electrode forming method, the manufacturing process is simplified and the cost is reduced.

2. The etching of the polyimide layer that covers the gold bump electrodes has the advantage that the side portions cannot be removed easily, and conversely, they can be completely covered. Therefore, extremely advantageous temperature cycle test results were obtained as compared with the conventional products. This is shown in the curve diagram of FIG. That is, the vertical axis is the defective rate,
When a cycle is taken on the horizontal axis, the conventional product marked with a circle is 30
At 0 or 500 cycles, a marked difference of one or more digits from the triangle mark of the present invention is seen, and the effect of the present invention is clear. This indicates that the stress due to the sealing resin is relaxed.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a main part of a conventional resin-sealed semiconductor element.

FIG. 2 is a cross-sectional view showing a resin-sealed semiconductor element according to the present invention after a manufacturing process.

FIG. 3 is a cross-sectional view of a resin-sealed semiconductor element obtained by the step after FIG.

FIG. 4 is a cross-sectional view of a resin-sealed semiconductor element obtained by the process after FIG.

FIG. 5 is a curve diagram showing characteristics of a resin-sealed semiconductor element according to the present invention and a conventional product.

[Explanation of symbols]

 1: semiconductor substrate, 2: CVD layer, 3: BPSG layer, 4: pad electrode, 5: PSG layer, 6: silicon nitride layer, 7: polyimide layer, 8: barrier metal layer, 9: bump electrode, 10: inner layer Lead, 11: sealing resin layer.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 23/31

Claims (1)

[Claims] 1. A step of coating a semiconductor substrate with an insulating layer, a step of overlaying a pad layer on the insulating layer portion, and a step of forming a passivation layer filling the pad.
Forming a bump electrode having a portion connected to the pad and penetrating the passivation layer, providing a barrier metal layer covering the bump electrode portion in contact with the passivation layer, and the passivation layer And a step of applying a polyimide layer for protecting exposed portions of the electrodes and side portions of the bump electrodes.