JPH05289888A - Interruption processing circuit - Google Patents

Abstract

PURPOSE:To provide the interruption processing circuit which can output at a high speed a response signal from an input of an interrupting signal irrespective of a state of a CPU. CONSTITUTION:The interruption processing circuit is constituted of a microcomputer 1 for executing an interruption processing, a parallel output port 2 whose output is set by the microcomputer concerned, a flip-flop 3 set by an interruption input signal 3a, a counter 4 to which a counter set value 2b is set by a set value of the parallel output port 2, and which executes a count operation at the time when an output of the flip-flop 3 is '1', and outputs a reset signal 4a to the flip-flop 3 at the time when the count is finished, and a parallel-serial converting circuit 5 for loading the pattern set value 2a from the parallel output port 2 at the time of the output of the flip-flop 3 is '0', and outputting successively a loaded value as output signals 5a1-5an at the time when the output of the flip-flop 3 is '1'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt processing circuit, and more particularly to an interrupt processing circuit which can obtain a response signal output from an interrupt input in a short time.

[0002]

2. Description of the Related Art Conventionally, as a process for an interrupt due to an external signal input to a microcomputer, when a signal is output in a predetermined pattern to the outside, a generally used interrupt processing circuit has a structure as shown in FIG. There is one. That is, the interrupt controller 101
The parallel I / O port 102 and the CPU 103 form an interrupt processing circuit. In the interrupt processing circuit configured as described above, as shown in the flowchart of processing at the time of interrupt input in FIG. 7, the CPU 103 executes an interrupt processing routine at the time of input of an interrupt signal, and outputs a predetermined signal pattern (data). , Is read from the buffer on the memory, and is output as a predetermined signal pattern from the parallel I / O port 102 to the outside. Note that FIG. 8 shows a timing chart of the interrupt signal, the CPU operation, and the output signal.

[0003]

By the way, in the conventional interrupt processing circuit, as shown in the timing chart of FIG. 8, when the interrupt signal is input, the CPU accepts the interrupt acceptance processing, and the signal output during the interrupt processing is output. Since it is performed by software control, the time from the input of the interrupt signal to the output of the response signal (pattern) changes depending on the state of the CPU when the interrupt signal is input, and since it is long, the timing on the external circuit side that receives the response signal Had to be adjusted.

The present invention has been made in order to solve the above problems in the conventional interrupt processing circuit, and an object thereof is to provide an interrupt processing circuit in which the interrupt signal input to the response signal output is short. ..

[0005]

In order to solve the above problems, the present invention is directed to a microcomputer for performing interrupt processing, a parallel output port for setting an output by the microcomputer, and an interrupt input signal. A flip-flop, and a counter that sets a count value by the set value of the parallel output port, performs a counting operation when the output of the flip-flop is active, and outputs a reset signal to the flip-flop at the end of counting; When the output of the flip-flop is inactive, a value is loaded from a parallel output port, and when the output of the flip-flop is active, a parallel-serial conversion circuit that sequentially outputs the loaded value constitutes an interrupt processing circuit. is there.

In the interrupt processing circuit thus constructed, the predetermined signal pattern and its length to be output at the time of interrupt processing can be preset in the parallel output port, and in synchronization with the input of the interrupt signal, The signal pattern set in the parallel output port is output by the length set in the counter. Therefore, the time from the input of the interrupt signal to the output of the response signal can be shortened regardless of the state of the microcomputer.

[0007]

EXAMPLES Next, examples will be described. FIG. 1 is a block diagram showing a basic embodiment of an interrupt processing circuit according to the present invention. In FIG. 1, reference numeral 1 is a microcomputer (CPU) that performs interrupt processing, and 2 is a parallel output port to which an output is set by the microcomputer 1. Reference numeral 3 is a flip-flop that is set by the input of the interrupt signal 3a and is reset by a reset signal 4a which is a counter output (carry) described later. Reference numeral 4 is a counter, which is a counter set value depending on the set value of the parallel output port 2. When 2b is set and the output of the flip-flop 3 is 1, the counting operation is performed, and the reset signal 4a is output to the flip-flop 3 when the counting is completed. Reference numeral 5 denotes a parallel-serial conversion circuit, which loads the pattern setting value 2a from the parallel output port 2 when the output of the flip-flop 3 is 0, and loads the pattern setting value 2a when the output of the flip-flop 3 is 1. Output signal 5a
It is output as ₁ , 5a ₂ , ..., 5a _n .

Next, the operation of the interrupt processing circuit thus constructed will be described with reference to the flow chart shown in FIG. 2 and the timing chart shown in FIG. C
The PU 1 sets a predetermined signal pattern to be output at the time of interrupt processing and its length in the parallel output port 2 in advance. Then, the counter set value 2b is set in the counter 4 based on the set value of the length, and the pattern set value 2a based on the signal pattern set in the parallel output port 2 is loaded in the parallel-serial conversion circuit 5. Has been done.

In this state, when the interrupt signal 3a is input to the flip-flop 3, the pattern set value 2a loaded into the parallel-serial conversion circuit 5 is the output signal 5a _{1 corresponding} to the counter set value set in the counter 4. ，
5a ₂ , ..., 5a _n are output. Then, in the software interrupt processing routine, the signal pattern to be output next time and its length are set in the parallel output port 2. In this way, the signal pattern preset by the CPU can be output in a short time in synchronization with the interrupt input signal regardless of the state of the CPU.

Next, a specific embodiment will be described with reference to FIG. In this embodiment, a data write signal and a latch signal are output to an external circuit in synchronization with an external timing signal. In FIG. 4, 11 is a CPU that performs interrupt processing, 12 is a decoder that inputs the address signal 11b output from the CPU 11, 13 is an 8-bit latch that inputs data 11c output from the CPU 11 and outputs output data 13a, 14 Is also the data output from CPU11
An 8-bit latch that inputs 11c and outputs a CS pattern 14a and a WE pattern 14b, and 15 is an 8-bit latch that inputs the data 11c output from the CPU 11 and outputs a count set value 15a.

Reference numeral 16 is a WE pattern 14b from the latch 14.
Is a shift register for inputting the WE output signal 16a, and 17 is a shift register for inputting the CS pattern 14a from the latch 14 and outputting the CS output signal 17a. 18 is a 4-bit counter which inputs the count set value 15a from the latch 15 and outputs a carry output 18b, 19 is a D flip-flop which inputs an interrupt signal 19a and outputs an interrupt latch signal 19b, and 20 is the D flip-flop
A D flip-flop 21 receives an interrupt latch signal 19b of 19 and outputs a load signal 20a to the shift registers 16 and 17 and a counter 18, and 21 receives a carry output 18b of the counter 18 and outputs an RCO synchronization signal 21a. It is a D flip-flop that outputs to the D flip-flop 19.
In FIG. 4, 11a indicates a CPU write signal, 18a indicates a system clock, and 18c indicates a count value.

Next, the operation of the interrupt processing circuit thus constructed will be described with reference to the timing chart shown in FIG. In the interrupt processing in this embodiment, as shown in the timing chart, the output data 13a to be transferred to the latch 13 is transferred to the latch 14 by the WE pattern 14.
b and the CS pattern 14a, the pattern length (counter set value 15a) is set in the latch 15. The timing chart shown in FIG. 5 explains the operation when the interrupt signal is input twice. First, the latch 13
Transfer data 08H (hexadecimal number) to latch 14, pattern 66 to latch 14
H (CS = 0110, WE = 0110) and the interrupt signal (transfer enable) 19a is input while the pattern length 0EH is written in the latch 15. As a result, the signals of the respective parts are output, and by the interrupt processing of the CPU 11,
Transfer data 0AH in latch 13, pattern 72H in latch 14
(CS = 0111, WE = 0010), the pattern length 0EH is written in the latch 15. Furthermore, a mode in which a second interrupt is input with these values set is shown.

When the interrupt signal 19a is input, the counter 18 and the shift registers 16 and 17 are enabled, the counter 18 starts counting, and the shift register 1
6 and 17 output the set pattern as a CS output signal 17a and a WE output signal 16a in synchronization with the system clock. As described above, the CPU can send the write signal and the data of the set arbitrary pattern in synchronization with the interrupt input signal.

[0014]

As described above on the basis of the embodiments,
According to the present invention, the response signal from the input of the interrupt signal,
It is possible to output at high speed regardless of the state of the CPU.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing a basic embodiment of an interrupt processing circuit according to the present invention.

FIG. 2 is a flowchart for explaining the operation of the embodiment shown in FIG.

FIG. 3 is a timing chart for explaining the operation of the embodiment shown in FIG.

FIG. 4 is a circuit configuration diagram showing a specific embodiment of the present invention.

5 is a timing chart for explaining the operation of the embodiment shown in FIG.

FIG. 6 is a block configuration diagram showing a configuration example of a conventional interrupt processing circuit.

FIG. 7 is a flowchart for explaining the operation of the interrupt processing circuit shown in FIG.

FIG. 8 is a timing chart for explaining the operation of the interrupt processing circuit shown in FIG.

[Explanation of symbols]

 1 Microcomputer 2 Parallel output port 3 Flip-flop 4 Counter 5 Parallel-serial conversion circuit

Claims (1)

[Claims] 1. A microcomputer for performing interrupt processing, a parallel output port for setting an output by the microcomputer, a flip-flop set by an interrupt input signal, and a count value set by a set value of the parallel output port. , Counting operation is performed when the output of the flip-flop is active,
A counter that outputs a reset signal to the flip-flop at the end of counting and a value is loaded from the parallel output port when the output of the flip-flop is inactive, and the loaded value is sequentially when the output of the flip-flop is active. An interrupt processing circuit comprising a parallel-serial conversion circuit for outputting.