JPH05282246A - Microcomputer - Google Patents

Abstract

PURPOSE:To provide a microcomputer in which a system design can be easily attained by a simple bus adjusting function, the system can be constituted only of one kind of microcomputer, and the number of terminals can be reduced, in a microcomputer system in which the plural microcomputers are connected with the same bus, and data are shared. CONSTITUTION:Microcomputers 1, 8, and 13 are connected with a shared bus 6, and the constitution of each microcomputer is the same. The microcomputer 1 is constituted of a CPU 2, DMA 3, and shared bus control part 4. The microcomputer 1 is connected with a memory 5, and the CPU 2 is operated based on a command program written in the memory 5. Each microcomputer is connected like a ring through the signal lines of permission signals 18, 19, and 20 which permit the usage of the shared bus 6, and the permission signals are circulated among each microcomputer. Each microcomputer inputs the permission signal, starts the usage of the shared bus 6, and holds the permission signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to a microcomputer having a bus arbitration circuit for connecting a plurality of microcomputers to the same bus and sharing data.

[0002]

2. Description of the Related Art Conventional microcomputers (hereinafter referred to as microcomputers) include direct memory access devices (hereinafter referred to as DMA) and central processing units (hereinafter referred to as C).
PU), its memory and the memory space for the CPU to normally fetch instructions, and the bus for connecting DMA and the memory space mainly for storing the data accessed by the memory. There is a microcomputer suitable for high-speed data processing. A communication circuit built in the microcomputer and an external disk device are connected to the DMA, and data is transferred to various memories.

FIG. 5 is a block diagram showing an example of the conventional microcomputer as described above. The microcomputer has a plurality of microcomputers, and the plurality of microcomputers share the memory section accessed by DMA and share the same data. A configuration is shown in which data processing is performed by using the. As shown in FIG.
Is composed of a CPU 52 and a DM 53. The microcomputer 51 is connected to the memory 54, and the CPU 52 operates based on the instruction program written in the memory 54. Further, the microcomputer 51 is connected to the shared bus 55. The shared bus 55 is also connected to a shared memory 56 for reading / writing shared data.

The microcomputer 57 includes a CPU 58 and a DM 59.
It consists of and. The microcomputer 57 is connected to the memory 60, and the CPU 58 operates based on the instruction program written in the memory 60. Also, the microcomputer 57
It is connected to the shared bus 55. The microcomputer 61 is a CP
It consists of U62 and DM63. Microcomputer 61
Is connected to the memory 64, and the CPU 62 operates based on the instruction program written in the memory 64. The microcomputer 61 is also connected to the shared bus 55.

When using the shared bus 55, the microcomputer 57 outputs a bus request signal B65. Similarly, the microcomputer 61 outputs a bus request signal C66. The IR gate 67 inputs the bus request signal B65 and the bus request signal C66, calculates the logical sum of them, and outputs the bus request signal A68.

The microcomputer 51 inputs the bus request signal A68, and when the microcomputer 51 does not use the shared bus 55, "0" is used as the bus permission signal A69 for the inverter 70.
Output to. The inverter 70 inverts the bus permission signal A69 and outputs an ΝΑΝD gate 71 and an ΝΑΝD gate 72.
Output to. Further, the A / D gate 72 inputs the bus request signal B65, performs a logical product of the inverted bus permission signal A69 and the bus request signal B65, and further inverts it to output to the microcomputer 57 as a bus permission signal B73. To do. ΝΑ
The GD gate 71 logically ANDs the inverted bus permission signal A69, the inverted bus request signal B65 and the inverted bus request signal C66, and further inverts the logical product to output it as a bus permission signal C74 to the microcomputer 61.

The reference clock φ75 is based on the microcomputer 51, 5
It is input to 7,61. The microcomputers 51, 57, 61 operate in accordance with this reference clock φ75.

Next, the operation of the above-mentioned conventional microcomputer will be described with reference to the timing chart shown in FIG.
FIG. 6 is a timing chart showing the operation of each part in the conventional microcomputer shown in FIG. In this conventional example, the microcomputer 57 first starts access to the shared bus 55. The timing when the use request of the shared bus 55 is issued from the microcomputer 61 before the end of the bus cycle will be described.

As shown in FIG. 6, reference clock φ73
Is the basis of timings T1 to T11. At timing T1, when the DM 59 in the microcomputer 57 tries to access the shared bus 55, the microcomputer 57
Sets the bus request signal B65 to "1". This allows
The bus request signal A68, which is the output of the JR gate 67, becomes "1" and is input to the microcomputer 51. Timing T
2, the microcomputer 51 sets the bus permission signal A69 to "0" with respect to the bus request signal A68 when the microcomputer 51 does not access the shared bus 55. Bus permission signal A69
It is input to the inverter 70 and is output as "1".
The bus request signal B65 and the output of the inverter 70 are "1".
Therefore, at timing T2, the output of the ΑΑD gate 72 becomes "0" and the bus permission signal B73 becomes active.

The microcomputer 57 receives the active bus permission signal B73 and outputs the timing T3 one reference clock later.
Access to the shared bus 55 is started. In this conventional example, the address data multiplex is used, and an address is output to the shared bus 55 from timing T3, and data is input / output at timings T4, T5, and T6. Here, at timing T4, the microcomputer 6
When the DMA 63 in 1 tries to access the shared bus 55, the microcomputer 61 sets the bus request signal C66 to "1".
And activate. The JR gate 67 is already activated by the bus request signal B65, and the bus request signal A68 does not change at this point.

The signal obtained by inverting the bus permission signal A69 output from the microcomputer 51 by the inverter 70 becomes "1", the bus request signal C66 becomes "1", and the bus request signal B65 becomes "1". Therefore, the bus permission signal C74, which is the output of the ΝΑΝD gate Α71, becomes "1" and is not activated.

When the microcomputer 57 finishes using the shared bus 55 at the timing T6, the microcomputer 57 sets the bus request signal B65 to "0" and withdraws the request for using the shared bus 55. The microcomputer 61 uses the bus request signal C66
Is continuously output, the bus request signal A68 is "1".
The bus permission signal A69 continues to be active in response to this, and the output of the inverter 70 is "1".

When the bus request signal B65 becomes "0",
ΑΝD gate 71 becomes active, bus enable signal C
74 becomes "0" and becomes active. Bus permission signal C
Since 74 is "0", the microcomputer 61 is delayed by one reference clock.
Starts accessing the shared bus 55.

Addresses are output from timing T7, and data is input / output at timings T8, T9, and T10. When the microcomputer 61 completes the access to the memory at the timing T10, the bus request signal C66 is withdrawn. Then, the bus request signal C66 becomes "0",
Since the bus request signal A68 becomes “0” and there is no request to use the shared bus 55, the timing T after one reference clock is reached.
At 11, the bus permission signal A69 becomes "1", and the use of the shared bus 55 by the microcomputers 57 and 61 ends.

Further, when the microcomputer 51 accesses the shared bus 55, the bus permission signal A69 is not activated, and other microcomputers are controlled so as not to access the shared bus 55 to arbitrate the use of the bus. ..

[0016]

However, in the above-mentioned conventional microcomputer, since a plurality of microcomputers are connected, the priority order circuit must be used to arbitrate the bus. Therefore, a microcomputer assigned a low priority may not be able to gain control of the bus for a long time until the processing of all other microcomputers with a higher priority than itself ends, and the processing time of the microcomputer is reduced. There is a problem in that it is difficult to estimate and system design using multiple microcomputers becomes difficult.

When a plurality of microcomputers are connected as in the conventional microcomputer described above, one of the plurality of microcomputers has a built-in circuit for inputting a bus use request signal and outputting a bus use permission signal. Must. The other plurality of microcomputers must include a circuit that outputs a bus use request signal and inputs a bus use permission signal. Therefore, the above-mentioned conventional microcomputer has a problem that two types of microcomputers must be designed and manufactured, and the complexity of use increases and the economical burden is large.

Further, in the above-described conventional microcomputer, the number of parts increases because the external priority control circuit must be expanded in order to connect a plurality of microcomputers. Furthermore, even if the priority control circuit is built into the microcomputer,
There is a problem that the number of terminals required increases according to the number of external microcomputers to be connected.

The present invention has been made in view of the above problems, and in a microcomputer in which a plurality of microcomputers are connected to the same bus and share data, the system design is facilitated by a simple bus arbitration circuit. It is an object of the present invention to provide a microcomputer that can be configured with only one type of microcomputer and that can reduce the number of terminals.

[0020]

A micro-computer according to the present invention comprises a plurality of micro-computers, first storage means commonly used by the plurality of micro-computers, and the plurality of micro-computers. It has a plurality of second storage means individually used for each micro computer in the computer, and a bus for commonly connecting the plurality of micro computers and the first storage means. In the micro computer, the plurality of micro computers input / output a permission signal indicating a right of use of the bus, and when the self-use does not use the bus, the input permission signal is input to another micro computer. When the bus is used by itself, the permission signal is input and then held, and after the bus is used, the permission signal is output to another micro controller. Npyu - and having people each bus control means for outputting the data.

[0021]

In the microcomputer according to the present invention, in a microcomputer system in which a plurality of microcomputers are connected to the same bus, each of the plurality of microcomputers has a bus control means. The bus control unit is a unit that enables its own microcomputer to use a bus shared by each microcomputer. The bus control means in each microcomputer is connected in a ring shape, and inputs and outputs a permission signal indicating the right to use the bus to circulate it. When its own microcomputer uses the bus, the bus control means inputs and holds the permission signal, and outputs the permission signal to the bus control means in another microcomputer after using the bus. As a result, the control right of the bus in each microcomputer is determined by the order of connection of the permission signal connected in a ring shape, so if the use of the bus of another microcomputer is completed once, the bus control right must be obtained. You can Therefore, in the microcomputer according to the present invention, it becomes easy to estimate the processing time of the microcomputer, and since each microcomputer only needs to have the input terminal and the output terminal of the permission signal, it is necessary to change the number of terminals according to the number of connected microcomputers. In addition, a circuit for controlling the priority order becomes unnecessary. Furthermore, since the circuit configurations of the plurality of microcomputers may be the same, there is no need to use two types of microcomputers as in the conventional example, which is economically advantageous.

[0022]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a microcomputer according to the first embodiment of the present invention. The microcomputer according to the first embodiment has a plurality of microcomputers, the plurality of microcomputers share a memory section accessed by DMA, and perform data processing using the same data. It is a composition. Although not shown, each microcomputer has a built-in peripheral circuit such as a high-speed communication control circuit, which is connected to each DMA and connected to each D
Data is input / output to / from the shared memory 7 via Mα.

The microcomputer 1 is composed of a CPU 2, a DM3 and a shared bus controller 4. The microcomputer 1 is connected to the memory 5, and the CPU 2 operates based on the instruction program written in the memory 5. In addition, microcomputer 1
Are connected to the shared bus 6. The shared bus 6 is also connected to a shared memory 7 for reading / writing shared data.

The microcomputer 8 comprises a CPU 9, a DMA 10 and a shared bus controller 11. The microcomputer 8 is connected to the memory 12, and the CPU 9 operates based on the instruction program written in the memory 12. Further, the microcomputer 8 is connected to the shared bus 6.

The microcomputer 13 includes a CPU 14 and a DM15.
And the shared bus control unit 16. Microcomputer 1
3 is connected to the memory 17 and the CPU 14
It operates based on the instruction program written in. The microcomputer 13 is also connected to the shared bus 6.

Permission signal A18 for permitting bus access
Is input to the microcomputer 1, and the microcomputer 1 sends the permission signal B
19 is output. Permit signal C2 for permitting bus access
0 is input to the microcomputer 8, and the microcomputer 8 outputs the permission signal A18. Permission signal B that permits bus access
19 is input to the microcomputer 13, and the microcomputer 13 outputs the permission signal C20.

The reference clock φ21 is the microcomputer 1, 8,
13 is input. In accordance with this reference Kuroku 21
The microcomputers 1, 8 and 13 operate. Reset signal 22
Is input to the microcomputers 1, 8 and 13 to initialize each microcomputer at the same time.

Further, the structure of the shared bus control units 4, 11, 16 in the microcomputers 1, 8, 13 shown in FIG. 1 will be described with reference to FIG. FIG. 2 is a circuit diagram showing in detail the structure of the shared bus control units 4, 11, 16 in the microcomputer shown in FIG. The shared bus control units 4, 11 and 16 have the same structure.

The permission signal A18 input via the permission signal input terminal 31 is input to the D latch 32 synchronized with the falling edge of the reference clock φ21. The output of the D latch 32 is input to the AND gates 33 and 34. When the DMA 3 built in the microcomputer 1 wants to use the shared bus 6, it outputs a REQ signal 35 and sets a flip-flop (hereinafter referred to as F / F) 36. The F / F 36 operates in synchronization with the fall of the reference clock φ21. F
The output signal of / F36 is input to the A / D gate A33. The output of the A / D gate A33 is the bus start signal 3
7 is sent to DMA3. DMA3 is shared bus 6
When the use of is finished, the end signal 38 is output and the F / F36
To reset. The start signal 40 is output from the CPU 2 in the microcomputer 1. ΟR Gate 39 is ΑΝ
Output of D gate 34, end signal 38 and start signal 40
Input and and take the logical sum. The output of the ΟR gate 39 is input to the D latch 41 synchronized with the rise of the reference clock φ21. The output of the D latch 41 is output as the permission signal B19 via the permission signal output terminal 42.

Next, the operation of the microcomputer according to the first embodiment constructed as described above will be described.

FIG. 3 is a timing chart showing the operation of each part in the microcomputer according to the first embodiment shown in FIGS. As shown in FIG. 3, the reference clock φ2
1 is the basis of timings T1 to T10.

First, the case where there is no use request from the respective microcomputers 1, 8, 13 to the shared bus 6 will be described. The permission signal A18 changes to the reference clock φ21 at timing T1.
When it becomes "1" at the rising edge of, the D-latch 32, to which the enabling signal Α18 is input, sets its output to "1" at the rising edge of the reference clock φ21 at the timing T2. Here, since the RQ signal 35 is not output from the DMA3, the output of the F / F36 becomes "0", and the AD gate 3
The output of 4 becomes "1". The output of the ΟR gate 39 is Α
It is set to "1" by the output of the ND gate 34. The output of the ΟR gate 39 is latched by the D latch 41 at the rising edge of the reference clock φ21 at the timing T2 and is output from the enable signal output terminal 42 as the enable signal B19.

Therefore, when there is no request to use the shared bus 6, the permission signal A input from the permission signal input terminal 31 is input.
18 is output as a permission signal B19 from the permission signal output terminal 42 after one reference clock. The shared bus control units 11 and 16 in the microcomputers 8 and 9 operate in the same manner as described above.

At timing T2, the permission signal B19 output from the microcomputer 1 is input to the shared bus control unit 16 in the microcomputer 13 and is output as the permission signal C20 at timing T3 one clock later. Further, the permission signal C20 is input to the microcomputer 8 and is output from the microcomputer 8 as a permission signal A18 at timing T4 one clock later. Here, when the RQ signal 35 is not active, the permission signal A18 is the permission signal B.
It is output from the microcomputer 1 as 19. That is, unless the shared bus 6 is used, a 1-level permission signal circulates between the microcomputers with a length of 1 reference clock.

Next, a case where the microcomputer 1 accesses the shared bus 6 will be described. When DMA3 tries to access the shared bus 6, DMA3 outputs the RQ signal 35 at timing T3 and sets the F / F36. The permission signal circulates between the microcomputers, and the permission signal A1
8 becomes active, is input from the enable signal input terminal 31 at timing T4, and is synchronized with the rising of the reference clock φ21 by the D latch 32 at timing T5. Since the output of the F / F 36 becomes "1" at the timing T4 and the output of the D latch 32 becomes "1" at the timing T5, the output of the A / D gate A33 is:
At the timing T5, the reference clock .phi.21 rises to "1" and the bus start signal 37 becomes active. When the bus start signal 37 is input, DΜΑ3 outputs an address to the shared bus 6 when the reference clock φ21 is "1" at timing T5, and starts access to the shared bus 6.

The microcomputer according to the first embodiment is address data multiplex, outputs an address at timing T5, and outputs timings T6 and T6.
At 7 and T8, data is input / output to / from the shared memory 7.

Since the output of the F / F 36 is "1" and the output of the A / D gate B34 is "0", the permission signal B19 remains "0". Since the enable signals B19 and C20 do not become "1", the other microcomputers 8 and 13 output the bus start signal 37 which gives the start timing for accessing the shared bus 6 to the DΜΑ10 and 15. Therefore, the shared bus 6 is not accessed.

When the DM A3 in the microcomputer 1 finishes the data input / output at the timing T8, the end signal 3
8 is output. The end signal 38 resets the F / F 36 to prepare for the next bus use request. The end signal 38 is
It is input to the D latch 41 at timing T8 via the IR gate 39, synchronized with the rise of the reference clock φ21, and output from the permission signal output terminal 42 as the permission signal B19. Since the permission signal B19 is output, the other microcomputers 8 and 16 can access the shared bus 6.

In the microcomputer according to the first embodiment, since the enable signal needs to be circulated between the microcomputers, only one microcomputer outputs the enable signal after the initialization of each microcomputer by the reset signal 22. To do so. Figure 1
In the first embodiment shown in FIG. 3, the memory 5 stores a program described to execute the instruction for outputting the start signal 40 after initialization of the microcomputer 1. Microcomputer 1
The CPU 2 at executes the instruction stored in the memory 5 after initialization by the reset signal 22 and outputs the start signal 40. The start signal 40 is the signal from the gate 3
9 is input to the D latch 41 and the reference clock φ2
Synchronized with the rising edge of 1, the permission signal output terminal 42 outputs the permission signal B19. Since the permission signal B19 is output, the circulation of the permission signal starts.

As described above, in the microcomputer according to the first embodiment, the microcomputer that outputs the first permission signal after initialization is selected by software.

Next, a microcomputer according to the second embodiment of the present invention will be described. FIG. 4 is a circuit diagram showing a shared bus control unit in the microcomputer according to the second embodiment of the present invention. In FIG. 4, the same components as those of the shared bus control unit according to the first embodiment shown in FIG.

In the shared bus control unit in the microcomputer according to the second embodiment shown in FIG. 1, the components different from the shared bus control unit according to the first embodiment shown in FIG.
The part in which the start signal 40 input to the gate 39 is reduced and the part in which the reset detection circuit 43 is added. Therefore, the method of generating the start signal is different from that of the first embodiment.

In the microcomputer according to the present invention, since it is necessary to circulate the permission signal between the microcomputers, the reset signal 2
After initialization of each microcomputer by 2, only one microcomputer outputs the permission signal.

The reset detection circuit 43 uses the reset signal 2
When 2 is input, a signal having one reference clock width is output after the initialization of the microcomputer 1. In addition, the microcomputer 1 has a terminal 44
Is provided. The reset detection circuit 43 has a terminal 44.
If the level of the signal input through is 1, it operates. If the level of the signal is "0", it does not operate.

A plurality of connected microcomputers have the same configuration as described above, and only one of the plurality of connected microcomputers sets the signal level of the terminal 44 to "1", and corresponds to the terminal 44 in the other microcomputers. The signal level of is set to "0". If the signal level at the terminal 44 is "1", the output of the reset signal detection circuit 43 becomes "1" for one reference clock width after initialization by the reset signal 22. The output of the reset signal detection circuit 43 is the gate 3
Reference clock φ21 input to the D-latch 41 via 9
Is synchronized with the rising edge of, and is output from the permission signal output terminal 42 as the permission signal B19. In other microcomputers, the signal level of the portion corresponding to the terminal 44 is "0", so the permission signal is not output.

As described above, in the second embodiment, the reset signal detection circuit and the terminal are provided, and the microcomputer that outputs the first enable signal after initialization is selected according to the signal level input from the terminal. There is.

[0048]

As described above, according to the microcomputer of the present invention, in a microcomputer system in which a plurality of microcomputers are connected to the same bus, the bus control right of each microcomputer is a permission to connect in a ring shape. Since the signal connection order is determined, the bus control right can always be obtained if the use of the bus of another microcomputer is completed once. Therefore, in the microcomputer according to the present invention, the processing time of the microcomputer can be easily estimated, and the system design using a plurality of microcomputers can be facilitated.

Further, in the microcomputer according to the present invention, the signal for permitting the control right of the bus is connected between the plurality of microcomputers in a ring shape, so that each microcomputer has only the input terminal and the output terminal of the permission signal. .. Therefore, it is not necessary to change the number of terminals depending on the number of connected microcomputers. Further, a circuit for controlling the priority order is not required as compared with the conventional example. Further, since the circuit configurations of the plurality of microcomputers are the same, it is not necessary to use two types of microcomputers as in the conventional example, which is economically advantageous.

[Brief description of drawings]

FIG. 1 is a block diagram showing a microcomputer according to a first embodiment of the present invention.

2 is a circuit diagram showing in detail the structure of a shared bus control unit in the microcomputer shown in FIG.

FIG. 3 is a timing chart showing the operation of each part in the microcomputer according to the first embodiment shown in FIGS. 1 and 2.

FIG. 4 is a circuit diagram showing a shared bus control unit in a microcomputer according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing an example of a conventional microcomputer.

6 is a timing chart showing the operation of each part in the conventional microcomputer shown in FIG.

[Explanation of symbols]

 1,8,16; Microcomputer 2,9,14; CPU 3,10,15; DMA 4,11,16; Shared bus controller 5,12,17; Memory 6; Shared bus 7; Shared memory

Claims (1)

[Claims] 1. A plurality of micro-computers, a first storage means commonly used by the plurality of micro-computers, and individual micro-computers in the plurality of micro-computers, respectively. In a micro computer having a plurality of second storage means used individually and a bus commonly connecting the plurality of micro computers and the first storage means, the plurality of micro computers are , Inputting and outputting a permission signal indicating the right to use the bus, outputting the input permission signal to another microcomputer when the bus is not used by itself, and when the bus is used by itself, Each has a bus control means for inputting and holding the permission signal and for outputting the permission signal to another microcomputer after use of the bus. Characteristic microcomputer.