JPH05282232A - Device control mechanism - Google Patents

Abstract

PURPOSE:To easily manage the change of control program information, and to easily cope with a device for a repair. CONSTITUTION:The control program information corresponding to an input and output interface LSI 5, and each version of a peripheral circuit system 8 set in a version code memory 6, is stored in an ROM 2 of a control part 1. A CPU 3 reads the input and output interface LSI 5 and the version code of the peripheral circuit system 8 from the version code memory 6, and decides the control program information to be used for a processing according to the content.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a device control mechanism, and more particularly to a control method of the device control mechanism for controlling peripheral circuit systems and the like.

[0002]

2. Description of the Related Art Conventionally, in this type of device control mechanism,
As shown in FIG. 4, the control unit 1 for controlling the peripheral circuit system 8 is used as a ROM (read only memory) 2 for storing control program information, a CPU (microprocessor) 3, and as an external storage memory during control. Input / output interface LSI 5 for exchanging data between RAM (random access memory) 4 and peripheral circuit system 8.
It consists of and. Here, the peripheral circuits 9 to 11 exist in the peripheral circuit system 8.

The CPU 3 is an input / output interface LSI
By accessing the respective designated addresses of No. 5, the peripheral circuits 9 to 11 in the designated peripheral circuit system 8 are accessed.
The state of is being detected. Further, the CPU 3 performs feedback control or sequential control for the peripheral circuits 9 to 11 by transferring data to another address based on the detection output.

When making changes such as addition or improvement of functions to the device having the above-mentioned configuration, for example, when making changes such as revision of the input / output interface LSI 5, the peripheral circuit system 8 is added or changed. Therefore, it is necessary to add or change the designated address of the input / output interface LSI 5, or change the data matching or waiting time as a signal detecting method.

Therefore, the R storing the control program information
OM2 must also be modified to accommodate the additions and changes. In this case, in the ROM 2, compatibility is lost between the program of the ROM 2 before the change and the program of the ROM 2 after the change such as addition or improvement of the function of the device.

On the other hand, even if the input / output interface LSI 5 and the peripheral circuit system 8 are not changed, the ROM 2
In some cases, it is necessary to improve the program in the ROM 2 due to a bug in the program itself.

In such a conventional device control mechanism, the longer the production span in producing the device, the more the input / output interface LSI according to the change of the peripheral circuit system 8.
Many changes are made to the program of the ROM 2 in accordance with the revision of No. 5 and due to bugs in the program itself.

Therefore, the program of the ROM 2 must be changed for each circuit system along with the change of the peripheral circuit system 8 and the input / output interface LSI 5.
Since the compatibility of the OM2 program itself for each device version is lost, there is a problem that the change management of the program of the ROM2 is doubled. In particular, for a device requested to be repaired by the user, the version of the device must be supported, which makes adaptation very troublesome.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in order to eliminate the above-mentioned problems of the conventional one, and can easily manage change of control program information, and can be easily applied to a repair device. It is an object of the present invention to provide a device control mechanism that can be used.

[0010]

A device control mechanism according to the present invention is a device control mechanism for controlling a peripheral circuit connected via an interface means, and corresponds to each version of a plurality of interface means indicating a revision of the interface means. Storage means for storing a program and a program corresponding to each version of a plurality of peripheral circuits indicating a change of the peripheral circuit, and holding for holding at least one of a current version of the interface means and a current version of the peripheral circuit Means and control means for controlling the operation by reading a corresponding program from the storage means in accordance with the content of the holding means are provided.

[0011]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, an apparatus control mechanism according to an embodiment of the present invention is an input / output interface LSI of a control unit 1.
5, a version code memory 6 is provided, and a version code can be set in the version code memory 6 from a version code setting switch 7. The configuration is the same as the conventional example shown in FIG. The same components are designated by the same reference numerals. The operation of the same constituent element is similar to the operation of the conventional example.

FIG. 2 is a diagram showing a method of setting the version code in the version code memory 6 of FIG. In the figure, the version code memory 6 provided in the input / output interface LSI 5 is composed of 8 bits, and its contents can be read by the CPU 3. The version code of the I / O interface LSI 5 is set in the upper 4 bits of the version code memory 6, and the lower 4 bits are set.
The version code of the peripheral circuit system 8 set by the version code setting switch 7 is fixedly set to the bit in terms of hardware.

As a result, the CPU 3 of the control unit 1 can grasp the version of the input / output interface LSI 5 and the peripheral circuit system 8 in detail from the contents of the version code memory 6.

The ROM 2 of the control unit 1 has an input / output interface LS set in the version code memory 6.
The control program information corresponding to the version of I5 and the peripheral circuit system 8 is stored. Ie ROM
Initialized data of the input / output interface LSI 5 and detection means and processing means for signals obtained from the peripheral circuit system 8 are stored in advance in the form of a data table or a branch processing routine corresponding to each version.

FIG. 3 is a flow chart showing the operation of one embodiment of the present invention. The operation of the embodiment of the present invention will be described with reference to FIGS.

When the power is turned on (step 2 in FIG. 3)
0), the CPU 3 sets the mode and then checks the data stored in the ROM 2 and the memory in the RAM 4 (steps 21 to 23 in FIG. 3).

Thereafter, the CPU 3 reads the version codes of the input / output interface LSI 5 and the peripheral circuit system 8 from the version code memory 6 (step 2 in FIG. 3).
4) Set those version codes as flag data in the RAM register (not shown) in the CPU 3 (step 25 in FIG. 3). Therefore, the CPU 3 will be
Control program information used for processing is determined according to the contents of the AM register.

Further, the CPU 3 uses the flag data set in the RAM register to input / output interface L
The version of SI5 is determined (step 26 in FIG. 3), and the LS for the input / output interface is selected from the initialization data tables 1 to N of the ROM 2 according to the determination result.
Select the I5 initialization data table (Fig. 3
Step 27). CPU3 is an input / output interface LSI based on the selected initialization data table.
The control memory 5 (not shown) is initialized (step 28 in FIG. 3).

Thereafter, for example, when detecting the states of the peripheral circuits 9 to 11 incorporated in the input / output interface LSI 5, the CPU 3 determines the version of the peripheral circuit system 8 based on the flag data set in the RAM register (FIG. 3). Step 29). According to the result of the determination, the CPU 3 selects and executes the detection memory address of the input / output interface LSI 5 and the detection means used for the detection from the detection means 1 to N (step 30 in FIG. 3) and executes the program processing.

Also, when the peripheral circuits 9 to 11 are processed, the CPU 3 determines the version of the peripheral circuit system 8 based on the flag data set in the RAM register (step 31 in FIG. 3), and inputs the result according to the determination result. The processing means used for the processing is selected and executed from the processing setting memory address of the output interface LSI 5 and the processing means 1 to N (step 32 in FIG. 3) to perform the program processing.

By the method as described above, the CPU 3 performs feedback control or sequential control on the input / output interface LSI 5 and the peripheral circuit system 8.
In addition, when judging the version by the CPU 3, RA
The flag data set in the M register is used,
The version code may be read directly from the version code memory 6 to determine the version.

Thus, the LS for the input / output interface
The control program information corresponding to each version of I5 and the peripheral circuit system 8 is stored in the ROM 2 and corresponds to the version code set in the version code memory 6 when the CPU 3 controls the input / output interface LSI 5 and the peripheral circuit system 8. By reading the control program information to be read from the ROM 2 and operating the control program information, the program stored in the ROM 2 can be modified by a detailed version upgrade in the manufacturing process of the device or the LS for the input / output interface
It is possible to make the program of the ROM 2 for the change due to the version upgrade of I5 and the change of the peripheral circuit system 8 compatible before and after the change. That is, among the programs in the ROM 2, only the control program information corresponding to the changes in the input / output interface LSI 5 and the peripheral circuit system 8 is stored in correspondence with the version, so that the compatibility of the programs can be maintained.

Therefore, it is not necessary to manage different programs for each change of the peripheral circuit system 8 and to correct different programs in the same way at the time of version upgrade, thus reducing the workload of the programmer who develops the programs. can do. As a result, the control program information can be changed more surely, and the version of the ROM 2 storing the control program information can be surely and simply upgraded even when the device manufactured in the initial stage of manufacturing is repaired. You can Therefore, the change management of the control program information can be facilitated, and the repair device can be easily adapted to the version of the device.

[0025]

As described above, according to the present invention, the program corresponding to each version of the plurality of interface means indicating the revision of the interface means and each version of the plurality of peripheral circuits indicating the change of the peripheral circuit are supported. The programs are stored respectively, and the program corresponding to at least one of the current version of the interface means and the current version of the peripheral circuit that is held is read out and controlled to operate, thereby managing the change of the control program information. There is an effect that it can be made easy and can be easily adapted to a repair device.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a method for setting a version code in a version code memory shown in FIG.

FIG. 3 is a flowchart showing the operation of one embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1 Controller 2 ROM 3 CPU 4 RAM 5 I / O Interface LSI 6 Version Code Memory 7 Version Code Setting Switch 8 Peripheral Circuit System 9-11 Peripheral Circuit

Claims (2)

[Claims] 1. A device control mechanism for controlling a peripheral circuit connected via interface means, wherein a program corresponding to each version of a plurality of interface means indicating a revision of the interface means and a change of the peripheral circuit are provided. Storage means for storing a program corresponding to each version of the plurality of peripheral circuits shown, holding means for holding at least one of the current version of the interface means and the current version of the peripheral circuit, and the contents of the holding means And a control means for controlling to operate by reading a corresponding program from the storage means according to the above. 2. The apparatus control mechanism according to claim 1, further comprising setting means for setting the current version of the peripheral circuit in the holding means.