JPH05276152A - Synchronization hold circuit - Google Patents
Synchronization hold circuitInfo
- Publication number
- JPH05276152A JPH05276152A JP4071053A JP7105392A JPH05276152A JP H05276152 A JPH05276152 A JP H05276152A JP 4071053 A JP4071053 A JP 4071053A JP 7105392 A JP7105392 A JP 7105392A JP H05276152 A JPH05276152 A JP H05276152A
- Authority
- JP
- Japan
- Prior art keywords
- frame
- signal
- synchronization
- timing
- demodulator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Time-Division Multiplex Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は同期保持回路に関し、特
に無線回線を介してディジタル信号の伝送を行う場合
に、復調器における同期保持を確保する同期保持回路に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync holding circuit, and more particularly to a sync holding circuit for ensuring sync holding in a demodulator when a digital signal is transmitted via a wireless line.
【０００２】[0002]
【従来の技術】従来、無線回線を介して行なうディジタ
ル無線伝送において、妨害もしくは干渉が発生して無線
回線の品質が劣化した場合には、復調器において受信信
号の中から正確にフレーム信号タイミングを検出するこ
とが困難となり、そのためにフレーム同期はずれが発生
することが生ずる。2. Description of the Related Art Conventionally, in digital radio transmission performed via a radio line, when interference or interference occurs and the quality of the radio line deteriorates, a demodulator accurately determines a frame signal timing from received signals. It becomes difficult to detect the frame, which may cause out of frame synchronization.
【０００３】一般に、このようなディジタル信号の伝送
を行う場合の同期プロセスは、大別すれば次の３つの段
階に分類できる。 （１）フレーム同期捕捉段階 受信信号の先頭部に含まれる、フレームタイミング検出
用のプリアンブル信号号から、あらかじめ規定された時
間長のフレーム信号が検出された場合に、フレーム同期
捕捉が確立したと判定する。 （２）フレーム同期保持段階 （１）項によるフレーム同期捕捉が完了した後は、受信
信号のフレーム信号に復調器のフレーム信号タイミング
を追従制御させて、同期保持を確保する。 （３）受信終了段階 受信信号の中のエンド・オブ・メッセージ（受信終了を
示すコード）を検出した場合には、同期保持を解除す
る。Generally, the synchronization process for transmitting such a digital signal can be roughly classified into the following three stages. (1) Frame synchronization acquisition stage When a frame signal with a predetermined time length is detected from the preamble signal for frame timing detection included in the head of the received signal, it is determined that frame synchronization acquisition has been established. To do. (2) Frame synchronization holding step After the frame synchronization acquisition according to the item (1) is completed, the frame signal timing of the demodulator is controlled to follow the frame signal of the received signal to secure the synchronization holding. (3) Reception end stage When the end of message (code indicating the end of reception) in the received signal is detected, the synchronization hold is released.
【０００４】[0004]
【発明が解決しようとする課題】上述した従来の同期保
持回路では、妨害もしくは干渉が発生して無線回線の品
質が劣化した場合には、フレーム同期保持段階での同期
保持はずれが生じ、データ伝送の障害となってしまうと
いう問題点があった。In the above-mentioned conventional synchronization holding circuit, when interference or interference occurs and the quality of the wireless line is deteriorated, the synchronization holding is lost at the frame synchronization holding stage, resulting in data transmission. There was a problem that it would become an obstacle to.
【０００５】本発明の目的は上述した問題点を解決し、
無線回線の品質が劣化しても確実な同期保持を確保しう
る同期保持回路を提供することにある。The object of the present invention is to solve the above-mentioned problems,
An object of the present invention is to provide a synchronization holding circuit capable of ensuring reliable synchronization holding even if the quality of a wireless line deteriorates.
【０００６】[0006]
【課題を解決するための手段】本発明の同期保持方式
は、無線回線を介してディジタル信号の伝送を行なう場
合に、復調器における同期保持を確保する同期保持回路
において、受信信号の含むプリアンブル信号からフレー
ムタイミングを検出した後は、復調器内部で固定タイミ
ングのフレームタイミング信号を発生してフレーム同期
を保持する構成を有する。According to the synchronization holding system of the present invention, a preamble signal included in a received signal is included in a synchronization holding circuit for ensuring synchronization holding in a demodulator when a digital signal is transmitted via a wireless line. After the frame timing is detected from the frame demodulator, a frame timing signal having a fixed timing is generated inside the demodulator to maintain the frame synchronization.
【０００７】[0007]
【実施例】次に、本発明について図面を参照して説明す
る。図１は本発明の一実施例のブロック図である。図１
に示す実施例は、復調器におけるフレーム同期捕捉と、
同期保持を断続，確保する部分を示している。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. Figure 1
The embodiment shown in FIG.
It shows the part that keeps the synchronization hold intermittently.
【０００８】図１に示す実施例は、受信信号からフレー
ム信号を検出する検波器１と、フレーム信号からフレー
ムタイミングを検出するフレームタイミング検出回路２
と、フレーム同期確立後は固定のフレームタイミング信
号を発生するフレームタイミング信号発生回路３と、フ
レームタイミング信号発生回路３に対する固定タイミン
グのタイミング信号を供給する基準信号発生回路４とを
備えて成る。In the embodiment shown in FIG. 1, a detector 1 for detecting a frame signal from a received signal and a frame timing detection circuit 2 for detecting a frame timing from the frame signal.
A frame timing signal generating circuit 3 for generating a fixed frame timing signal after the frame synchronization is established, and a reference signal generating circuit 4 for supplying a timing signal with a fixed timing to the frame timing signal generating circuit 3.
【０００９】次に、本実施例の動作について説明する。
受信信号を入力した検波器１から出力されるフレーム信
号のフレーム時間幅をフレームタイミング検出回路２に
よって計測し、このフレーム時間幅が連続して３回以上
規定時間を満足する場合には、フレーム同期が確立した
と判定して同期捕捉処理を完了する。Next, the operation of this embodiment will be described.
The frame time width of the frame signal output from the detector 1 which receives the received signal is measured by the frame timing detection circuit 2, and when the frame time width continuously satisfies the specified time three times or more, the frame synchronization is performed. Then, the synchronization acquisition processing is completed.
【００１０】以後は、復調器内部に設けた高安定の基準
信号発生器４から固定のタイミング信号を送出し、この
タイミング信号でフレームタイミング信号発生回路３を
駆動して固定タイミングの固定フレームタイミング信号
を出力し、これによって通信回線の状態に依存しないフ
レーム同期保持段階を確立する。After that, a fixed timing signal is sent from the highly stable reference signal generator 4 provided inside the demodulator, and the frame timing signal generating circuit 3 is driven by this timing signal to fix the fixed frame timing signal. , Which establishes a frame synchronization holding stage that does not depend on the state of the communication line.
【００１１】なお、受信信号の中のエンド・オブ・メッ
セージ検出にもとづいて受信終了することは従来と同様
であり、このあと、また上述した同期保持が受信信号の
再入力とともに繰り返えされる。It is to be noted that the reception is terminated based on the detection of the end of message in the received signal as in the conventional case, and thereafter, the above-mentioned synchronization holding is repeated with the re-input of the received signal.
【００１２】[0012]
【発明の効果】以上説明したように本発明は、プリアン
ブル信号を検出してフレーム同期が確立した後は、受信
信号のフレーム信号に受信側復調器のフレームタイミン
グを追従させる方式に代えて、内部に設けた基準信号発
生器で発生する固定タイミングの固定フレームタイミン
グ信号によりフレーム同期を保持することにより、受信
信号が妨害もしくは干渉を受けて無線回線の品質が劣化
し、フレームタイミングが乱れた場合でも、固定フレー
ムタイミング信号により同期が安定して保持され、フレ
ーム同期はずれを根本的に回避できるという効果があ
る。As described above, according to the present invention, after the preamble signal is detected and the frame synchronization is established, the frame timing of the receiving side demodulator is made to follow the frame timing of the receiving side signal instead of the internal method. Even if the frame timing is disturbed by maintaining the frame synchronization by the fixed frame timing signal of the fixed timing generated by the reference signal generator provided in The synchronization is stably maintained by the fixed frame timing signal, and the frame synchronization loss can be basically avoided.
【図１】本発明の一実施例のブロック図である。FIG. 1 is a block diagram of an embodiment of the present invention.
１ 検波器 ２ フレームタイミング検出回路 ３ フレームタイミング信号発生回路 ４ 基準信号発生回路 1 detector 2 frame timing detection circuit 3 frame timing signal generation circuit 4 reference signal generation circuit
Claims (1)
を行なう場合に、復調器における同期保持を確保する同
期保持回路において、受信信号の含むプリアンブル信号
からフレームタイミングを検出した後は、復調器内部で
固定タイミングのフレームタイミング信号を発生してフ
レーム同期を保持することを特徴とする同期保持回路。1. When a digital signal is transmitted via a wireless line, a sync hold circuit for ensuring sync hold in a demodulator, after detecting a frame timing from a preamble signal included in a received signal, the demodulator internal A synchronization holding circuit for generating a frame timing signal having a fixed timing and holding the frame synchronization.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4071053A JPH05276152A (en) | 1992-03-27 | 1992-03-27 | Synchronization hold circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4071053A JPH05276152A (en) | 1992-03-27 | 1992-03-27 | Synchronization hold circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05276152A true JPH05276152A (en) | 1993-10-22 |
Family
ID=13449398
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4071053A Pending JPH05276152A (en) | 1992-03-27 | 1992-03-27 | Synchronization hold circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05276152A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07288501A (en) * | 1994-04-15 | 1995-10-31 | Nec Corp | Voice transmission system and voice transmitter in mobile satellite communication system |
| US6526107B1 (en) | 1997-11-19 | 2003-02-25 | Kabushiki Kaisha Kenwood | Synchronization acquiring circuit |
| WO2011101925A1 (en) * | 2010-02-16 | 2011-08-25 | パナソニック電工株式会社 | Receiver circuit and receiver apparatus |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62278839A (en) * | 1986-05-28 | 1987-12-03 | Sharp Corp | Display device |
| JPH03254242A (en) * | 1990-03-02 | 1991-11-13 | Nippon Telegr & Teleph Corp <Ntt> | Synchronizing circuit |
-
1992
- 1992-03-27 JP JP4071053A patent/JPH05276152A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62278839A (en) * | 1986-05-28 | 1987-12-03 | Sharp Corp | Display device |
| JPH03254242A (en) * | 1990-03-02 | 1991-11-13 | Nippon Telegr & Teleph Corp <Ntt> | Synchronizing circuit |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07288501A (en) * | 1994-04-15 | 1995-10-31 | Nec Corp | Voice transmission system and voice transmitter in mobile satellite communication system |
| US6526107B1 (en) | 1997-11-19 | 2003-02-25 | Kabushiki Kaisha Kenwood | Synchronization acquiring circuit |
| WO2011101925A1 (en) * | 2010-02-16 | 2011-08-25 | パナソニック電工株式会社 | Receiver circuit and receiver apparatus |
| JP2011171817A (en) * | 2010-02-16 | 2011-09-01 | Panasonic Electric Works Co Ltd | Reception circuit and receiver apparatus |
| US8891688B2 (en) | 2010-02-16 | 2014-11-18 | Panasonic Corporation | Receiver circuit and receiver apparatus |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19970826 |