JPH05267394A - Mounting of semiconductor element - Google Patents
Mounting of semiconductor elementInfo
- Publication number
- JPH05267394A JPH05267394A JP6382892A JP6382892A JPH05267394A JP H05267394 A JPH05267394 A JP H05267394A JP 6382892 A JP6382892 A JP 6382892A JP 6382892 A JP6382892 A JP 6382892A JP H05267394 A JPH05267394 A JP H05267394A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- mounting
- bumps
- bump
- recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＩＣチップ等の半導体
素子の表面に突出して形成されたバンプを実装基板上の
電極端子に直接接続（フェースダウンボンディング）し
て半導体素子を実装用基板上に実装する方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to mounting a semiconductor element on a mounting substrate by directly connecting (face down bonding) a bump formed on the surface of a semiconductor element such as an IC chip to an electrode terminal on the mounting substrate. On how to implement.
【０００２】[0002]
【従来の技術】ＩＣ等の半導体素子を基板上に直接実装
する場合に、半導体素子の電極パッド上にはんだ等の低
融点材料による凸状のバンプを形成し、このバンプを基
板上に形成されている電極端子上に乗せて溶融固化する
ことにより、半導体素子を実装基板に直接接続すること
が、従来より行われていた。2. Description of the Related Art When a semiconductor element such as an IC is directly mounted on a substrate, a convex bump made of a low melting point material such as solder is formed on an electrode pad of the semiconductor element, and the bump is formed on the substrate. It has been conventionally practiced to directly connect a semiconductor element to a mounting substrate by placing it on an existing electrode terminal and melting and solidifying it.
【０００３】[0003]
【発明が解決しようとする課題】基板上の電極端子は、
従来、平坦に形成されていた。このため、半導体素子上
に形成する全てのバンプは、その高さが同一になるよう
に高い精度が要求された。また、素子上のバンプを基板
上の電極端子に直接接続していたため、バンプとして使
用できる材料は、電極端子より融点の低い材料に限られ
ていた。さらに、一度に接続するバンプの数が多いため
に、電極端子との接触不良が生じ易く、電気的接続の信
頼性にも問題があった。The electrode terminals on the substrate are
Conventionally, it was formed flat. Therefore, all the bumps formed on the semiconductor element are required to have high accuracy so that the heights thereof are the same. Moreover, since the bumps on the element are directly connected to the electrode terminals on the substrate, the material that can be used as the bumps is limited to the material having a lower melting point than the electrode terminals. Further, since the number of bumps connected at one time is large, poor contact with the electrode terminals is likely to occur and there is a problem in reliability of electrical connection.
【０００４】そこで、本発明はこのような問題を解決
し、高さにばらつきがあるバンプでも確実に電極端子と
接続でき、かつバンプ形成材料の選択の幅の広い半導体
素子の実装方法を提供することを目的とする。Therefore, the present invention solves such a problem, and provides a method of mounting a semiconductor element in which bumps having different heights can be reliably connected to the electrode terminals and the bump forming material can be selected widely. The purpose is to
【０００５】[0005]
【課題を解決するための手段】上記課題を解決するため
に、本発明の半導体素子の実装方法は、実装基板の表面
には底部に電極端子を有していてバンプを受容する凹部
が形成されており、凹部に弾力性のある導電性粒子と接
着剤を入れた後に、半導体素子を実装基板に押し付け
て、バンプを凹部に挿入した状態で、凹部内の接着剤を
固化させる。In order to solve the above-mentioned problems, in the method of mounting a semiconductor element according to the present invention, a concave portion having an electrode terminal at the bottom and a bump is formed on the surface of the mounting substrate. That is, after the elastic conductive particles and the adhesive are put in the recess, the semiconductor element is pressed against the mounting substrate, and the adhesive in the recess is solidified while the bump is inserted in the recess.
【０００６】[0006]
【作用】本発明の半導体素子の実装方法によれば、半導
体素子を実装基板に押し付けて、バンプを凹部に挿入す
る。このため、半導体素子上に形成されたバンプの高さ
にばらつきあっても、凹部内の導電性粒子が圧縮されて
変形することによってこのばらつきを吸収し、全てのバ
ンプがそれぞれの凹部に十分な深さまで挿入される。そ
して、この状態で接着剤を固化させることによって、半
導体素子を基板上に固定すると共に、バンプの挿入で変
形した導電性粒子の形状を保持させる。According to the semiconductor element mounting method of the present invention, the semiconductor element is pressed against the mounting substrate and the bumps are inserted into the recesses. Therefore, even if the heights of the bumps formed on the semiconductor element are varied, the conductive particles in the recesses are compressed and deformed to absorb the variations, and all the bumps are sufficiently distributed in the respective recesses. It is inserted to the depth. Then, by solidifying the adhesive in this state, the semiconductor element is fixed on the substrate and the shape of the conductive particles deformed by the insertion of the bump is maintained.
【０００７】このような実装方法を用いることによっ
て、半導体素子のバンプと実装基板の電極端子とは、導
電性粒子を介して電気的に接続される。By using such a mounting method, the bumps of the semiconductor element and the electrode terminals of the mounting substrate are electrically connected via conductive particles.
【０００８】[0008]
【実施例】以下、本発明の一実施例について、図１およ
び図２を参照して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.
【０００９】図１は実装基板に半導体素子を実装させる
前の状態を示しており、図２は実装後の状態を示してい
る。FIG. 1 shows a state before the semiconductor element is mounted on the mounting board, and FIG. 2 shows a state after the mounting.
【００１０】半導体素子１にはその表面から突出して複
数のバンプ２が形成されている。他方、半導体素子１が
装着される基板３には、半導体素子１上のバンプ２に対
応して複数の凹部４が形成されている。この凹部４内に
は選択的にメッキを施すなどして電極端子５が形成され
ている。さらに、この凹部４内には、微細で柔軟なプラ
スチックボール表面にＡｕなどの金属メッキを施した直
径５μｍ程度の導電性粒子６と、例えばエポキシ系樹脂
のような熱硬化性樹脂７とからなる導電性樹脂８が注入
されている。この導電性樹脂８は十分な導電性を得るよ
うに導電性粒子６と熱硬化性樹脂７との比率が工夫され
ている。例えば、熱硬化性樹脂７に対する導電性粒子６
の添加量を７．５ｖｏｌ％以上にすることによって、良
好な接続特性を持たせるなどの工夫である。A plurality of bumps 2 are formed on the semiconductor element 1 so as to project from the surface thereof. On the other hand, the substrate 3 on which the semiconductor element 1 is mounted is formed with a plurality of recesses 4 corresponding to the bumps 2 on the semiconductor element 1. Electrode terminals 5 are formed in the recesses 4 by selective plating or the like. Further, in the concave portion 4, there are formed conductive particles 6 having a diameter of about 5 μm in which a fine and flexible plastic ball surface is plated with a metal such as Au, and a thermosetting resin 7 such as an epoxy resin. The conductive resin 8 is injected. The ratio of the conductive particles 6 to the thermosetting resin 7 is devised so that the conductive resin 8 has sufficient conductivity. For example, the conductive particles 6 for the thermosetting resin 7
The amount of addition of 7.5 vol% or more is a device for providing good connection characteristics.
【００１１】このように形成された基板３に対して、半
導体素子１上の全てのバンプ２が対応する凹部４に挿入
できるよう位置合せを行う。次に、半導体素子１を基板
３に押圧し、一定の深さまで半導体素子１上の全てのバ
ンプ２を対応する各凹部４に挿入する。この状態を図２
の断面図に示す。このように圧力を掛けることによっ
て、バンプ２の頂部が凹部４内の導電性樹脂８の表面部
に到達した後も、バンプ２を対応する凹部４内にさらに
挿入させることができる。これは、導電性粒子６が圧力
によって容易に変形するからである。そして、一定の深
さまでバンプ２を挿入した状態で熱を加えて、熱硬化性
樹脂７を硬化させる。この熱硬化性樹脂７の硬化によっ
て、挿入されたバンプ２が電極端子５の凹部４内に固定
され、変形した導電性粒子６がそのままの形状で固化さ
れる。The substrate 3 thus formed is aligned so that all the bumps 2 on the semiconductor element 1 can be inserted into the corresponding recesses 4. Next, the semiconductor element 1 is pressed against the substrate 3 and all the bumps 2 on the semiconductor element 1 are inserted into the corresponding recesses 4 to a certain depth. This state is shown in Figure 2.
Is shown in the sectional view of FIG. By applying the pressure in this way, even after the top of the bump 2 reaches the surface of the conductive resin 8 in the recess 4, the bump 2 can be further inserted into the corresponding recess 4. This is because the conductive particles 6 are easily deformed by the pressure. Then, heat is applied with the bumps 2 inserted to a certain depth to cure the thermosetting resin 7. By the hardening of the thermosetting resin 7, the inserted bump 2 is fixed in the recess 4 of the electrode terminal 5, and the deformed conductive particles 6 are solidified in the same shape.
【００１２】上述したように導電性樹脂８は十分な接続
特性を有するので、半導体素子１のバンプ２は、導電性
樹脂８を介して、対応する電極端子５と電気的に接続さ
れる。また、バンプ２の製造精度が悪いために高さにば
らつきがある場合でも、他のバンプに比べて高いバンプ
は、より深く導電性樹脂８内に埋没するので、全てのバ
ンプを凹部内の導電性樹脂８の表面部に到達させること
ができる。このため、バンプ２の製造精度が悪くても、
全てのバンプを確実に電気的に接続することができる。
さらに、本実施例は熱硬化性樹脂７を用いて、基板３上
に半導体素子１を装着しているので、バンプ２を溶融し
て接続させる必要がない。このため、従来のようにバン
プ２を電極端子５より融点温度の低い金属材料で作製す
る必要がなくなった。この結果、従来からのバンプ２の
材料であるＰｂ−Ｓｎなどの他にも、Ａｕ、Ａｇ、Ｃ
ｕ、Ａｌなどの金属が利用できるようになった。Since the conductive resin 8 has sufficient connection characteristics as described above, the bump 2 of the semiconductor element 1 is electrically connected to the corresponding electrode terminal 5 via the conductive resin 8. Further, even if the bumps 2 have different heights due to poor manufacturing accuracy, the bumps higher than other bumps are buried deeper in the conductive resin 8, so that all the bumps are electrically conductive in the recesses. It is possible to reach the surface of the resin 8. Therefore, even if the manufacturing accuracy of the bump 2 is poor,
All bumps can be reliably electrically connected.
Further, in this embodiment, since the semiconductor element 1 is mounted on the substrate 3 using the thermosetting resin 7, it is not necessary to melt and connect the bumps 2. Therefore, it is not necessary to form the bump 2 from a metal material having a melting point lower than that of the electrode terminal 5 as in the conventional case. As a result, in addition to the conventional material of the bump 2, such as Pb-Sn, Au, Ag, C
Metals such as u and Al are now available.
【００１３】なお、本実施例では、接着剤として熱硬化
性樹脂７を用いたが、紫外線・電子線硬化形接着剤など
の他の接着剤を用いてもよい。Although the thermosetting resin 7 is used as the adhesive in this embodiment, other adhesives such as an ultraviolet / electron beam curable adhesive may be used.
【００１４】[0014]
【発明の効果】本発明の半導体素子の実装方法であれ
ば、半導体素子上に形成されるバンプの製造精度の幅を
大きく取ることができ、バンプ形成の生産性を改善する
ことができる。また、バンプと電極端子の電気的接続を
確実に行うことができるので、接続の信頼性が向上す
る。さらに、バンプ形成材料の選択の幅が広くなり、実
装コストを低減させることができる。According to the semiconductor element mounting method of the present invention, the range of manufacturing accuracy of the bumps formed on the semiconductor element can be widened, and the productivity of bump formation can be improved. Further, since the bump and the electrode terminal can be reliably electrically connected, the reliability of the connection is improved. Further, the range of selection of the bump forming material is widened, and the mounting cost can be reduced.
【図１】本発明の一実施例の構造を示す断面図である。FIG. 1 is a sectional view showing the structure of an embodiment of the present invention.
【図２】本発明の一実施例の構造を示す断面図である。FIG. 2 is a sectional view showing the structure of an embodiment of the present invention.
１…半導体素子、２…バンプ、３…基板、４…凹部、５
…電極端子、６…導電性粒子、７…熱硬化性樹脂、８…
導電性樹脂。1 ... Semiconductor element, 2 ... Bump, 3 ... Substrate, 4 ... Recess, 5
... Electrode terminals, 6 ... Conductive particles, 7 ... Thermosetting resin, 8 ...
Conductive resin.
Claims (3)
実装基板上の電極端子に直接接続して前記半導体素子を
前記実装基板上に実装する方法において、 前記実装基板の表面には、底部に電極端子を有していて
前記バンプを受容する凹部が形成されており、 前記凹部に弾力性のある導電性粒子と接着剤を注入した
後に、前記半導体素子を前記実装基板に押し付けて、前
記バンプを前記凹部に挿入した状態で、前記凹部内の接
着剤を固化させることを特徴とする半導体素子の実装方
法。1. A method of mounting the semiconductor element on the mounting board by directly connecting bumps formed on the surface of the semiconductor element to electrode terminals on the mounting board, wherein a bottom portion is provided on the surface of the mounting board. A recess having an electrode terminal for receiving the bump is formed, and after injecting elastic conductive particles and an adhesive into the recess, the semiconductor element is pressed against the mounting substrate to form the bump. A method for mounting a semiconductor element, wherein the adhesive in the recess is solidified in a state in which is inserted into the recess.
ール表面に金属メッキを施した粒子であることを特徴と
する請求項１記載の半導体素子の実装方法。2. The method of mounting a semiconductor element according to claim 1, wherein the conductive particles are particles in which a soft plastic ball surface is plated with metal.
特徴とする請求項１または請求項２記載の半導体素子の
実装方法。3. The method for mounting a semiconductor element according to claim 1, wherein the adhesive is a thermosetting resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6382892A JPH05267394A (en) | 1992-03-19 | 1992-03-19 | Mounting of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6382892A JPH05267394A (en) | 1992-03-19 | 1992-03-19 | Mounting of semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05267394A true JPH05267394A (en) | 1993-10-15 |
Family
ID=13240613
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6382892A Pending JPH05267394A (en) | 1992-03-19 | 1992-03-19 | Mounting of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05267394A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997047031A1 (en) * | 1996-06-07 | 1997-12-11 | Matsushita Electric Industrial Co., Ltd. | Method for mounting semiconductor chip |
| JP2009105209A (en) * | 2007-10-23 | 2009-05-14 | Nec Corp | Electronic device and method of manufacturing the same |
| WO2011148445A1 (en) * | 2010-05-27 | 2011-12-01 | パナソニック株式会社 | Semiconductor device and process for production thereof |
| WO2015087918A1 (en) * | 2013-12-10 | 2015-06-18 | オリンパス株式会社 | Solid-state imaging device, imaging device, solid-state imaging device manufacturing method |
| US20230063954A1 (en) * | 2021-08-25 | 2023-03-02 | Micron Technology, Inc. | Conductive buffer layers for semiconductor die assemblies and associated systems and methods |
-
1992
- 1992-03-19 JP JP6382892A patent/JPH05267394A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997047031A1 (en) * | 1996-06-07 | 1997-12-11 | Matsushita Electric Industrial Co., Ltd. | Method for mounting semiconductor chip |
| US6051093A (en) * | 1996-06-07 | 2000-04-18 | Matsushita Electric Industrial Co., Ltd. | Mounting method of semiconductor element |
| US6531022B1 (en) | 1996-06-07 | 2003-03-11 | Matsushita Electric Industrial Co., Ltd. | Mounting method of semiconductor element |
| KR100457609B1 (en) * | 1996-06-07 | 2005-01-15 | 마쯔시다덴기산교 가부시키가이샤 | Method for mounting semiconductor chip |
| JP2009105209A (en) * | 2007-10-23 | 2009-05-14 | Nec Corp | Electronic device and method of manufacturing the same |
| WO2011148445A1 (en) * | 2010-05-27 | 2011-12-01 | パナソニック株式会社 | Semiconductor device and process for production thereof |
| WO2015087918A1 (en) * | 2013-12-10 | 2015-06-18 | オリンパス株式会社 | Solid-state imaging device, imaging device, solid-state imaging device manufacturing method |
| JP2015115420A (en) * | 2013-12-10 | 2015-06-22 | オリンパス株式会社 | Solid-state imaging device, imaging device, and method of manufacturing solid-state imaging device |
| US20230063954A1 (en) * | 2021-08-25 | 2023-03-02 | Micron Technology, Inc. | Conductive buffer layers for semiconductor die assemblies and associated systems and methods |
| TWI828232B (en) * | 2021-08-25 | 2024-01-01 | 美商美光科技公司 | Semiconductor dies, semiconductor die assemblies, and methods for forming the same |
| US11862591B2 (en) * | 2021-08-25 | 2024-01-02 | Micron Technology, Inc. | Conductive buffer layers for semiconductor die assemblies and associated systems and methods |
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