JPH05264753A - Delay time measuring device - Google Patents

Abstract

PURPOSE:To perform an accurately measurement constantly with a high resolution without being affected by drift, etc., since the delay time of an element to be measured is measured by utilizing a deviation of phase between two pulses which are generated accurately by a two pulse PLL circuits. CONSTITUTION:First and second pulse generation means 46 and 48 which are PLL circuits generate pulses which are different in number for each period of a reference pulse signal and where equal-numbered pulse phases within one period deviate gradually. The pulse from a first pulse generator is delayed by a delay element 50 to be delayed. Equal-numbered two pulses within the same period of the reference pulse signal are extracted by pulse extraction means 42, 44, 52, 54, and 56 by the delay element to be measured and the second pulse generation means, the phase difference of these pulses is detected by a phase difference detection means, and then a pulse set with the minimum phase difference is searched for, thus measuring the amount of delay in the delay means to be measured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay time measuring device for measuring a minute delay time.

[0002]

Prior Art and Problems to be Solved by the Invention FIG.
Shows an example of a conventional delay time measuring device. In this device, the pulse generator 10 generates repetitive pulses and supplies them to the delay element 12 to be measured and the ramp generator 14. The ramp generator 14 is a circuit typically including a Miller integrating circuit having an operational amplifier, and the pulse generator 10
When it receives a pulse from, it begins to generate, for example, a negative ramp voltage at its output. This ramp voltage is supplied to the non-inverting input terminal of the comparator 16 and compared with the output voltage of the potentiometer 18 supplied to the inverting input terminal. When the output ramp voltage of the ramp generator 14 and the output voltage of the potentiometer 18 match, the comparator 16 outputs D
An output pulse is supplied to the clock input terminal of the flip-flop circuit 20 and the ramp voltage is reset to 0 volt. The measured delay element 12 delays the pulse from the pulse generator 10 for a predetermined time and then supplies the pulse to the D input terminal of the D flip-flop circuit 20. When the output voltage of the potentiometer 18 is increased in the negative direction, the generation timing of the output pulse of the comparator 16 is gradually delayed, and the comparator 16 is placed within the window of the pulse supplied to the D input terminal of the D flip-flop circuit 20. , The D flip-flop circuit 20 produces an output pulse at the Q output terminal. The delay time of the measured delay element can be measured from the output voltage of the potentiometer 18 at the time of generation of this output pulse. In such a delay time measuring device, highly accurate linearity is required for the lamp voltage in order to accurately measure a minute delay time. However, the ramp generator cannot maintain its linearity because of drift due to the temperature of the operational amplifier. In addition, in order to make the ramp angle of the lamp voltage accurate, the resistors and the capacitors need to be highly accurately or carefully calibrated.

Therefore, an object of the present invention is to provide a delay time measuring device for accurately measuring a minute delay time.
Another object of the present invention is to provide a delay time measuring device that does not cause an error due to the influence of drift or the like.

[0004]

In the delay time measuring apparatus of the present invention, the first pulse generating means is synchronized with the reference pulse signal and generates the first predetermined number of pulses in each cycle of the reference pulse signal. The second pulse generating means generates a second predetermined number of pulses, which is smaller than the first predetermined number, for each cycle of the reference pulse signal in synchronization with the reference pulse signal. Since the number of pulses from the first and second pulse generating means in one cycle of the reference pulse signal is different, the phase of the same pulse in that cycle gradually shifts. The pulse from the first pulse generator is delayed by the delay element under test. From the delay element to be measured and the second pulse generating means, the same two pulses within the same cycle of the reference pulse signal are extracted by the pulse extracting means, and the phase difference between these pulses is detected by the phase difference detecting means, The delay amount of the delay unit under test is measured by searching for a set of pulses having the smallest phase difference.

[0005]

1 is a block diagram showing a delay time measuring apparatus of the present invention, and FIG. 2 is a timing diagram for explaining the operation of the apparatus of the present invention. In FIG. 1, the reference pulse generator 22 supplies the reference pulse signal R having the period T to one input terminal of each of the phase detectors 24 and 26. Each of the phase detectors 24 and 26 outputs a voltage corresponding to the phase difference between the two input signals input to the one and the other input terminals. The output voltages of the phase detectors 24 and 26 are averaged by low pass filters (LPFs) 28 and 30, respectively, and then supplied to voltage controlled oscillators (VCOs) 32 and 34. The voltage controlled oscillators 32 and 34 generate pulse signals having a frequency determined by the output voltages of the LPFs 28 and 30 supplied to the input terminals, respectively. Dividers 36 and 38
Is a counter circuit which outputs pulse signals A and B for every n output pulses of the VCO 32 and for every (n-1) output pulses of the VCO 34, respectively. The pulse signal A is supplied to the other input terminal of the phase detector 24, passes through the delay element 40, becomes a pulse signal C, and is supplied to the load terminal of the counter circuit. The delay time of the delay element 40 will be described later. The pulse signal B is the phase detector 2
It is supplied to the other input terminal of 6 and directly to the load terminal of the counter circuit 44.

Phase detector 24, LPF 28, VCO 32
The frequency divider 36 constitutes the first phase lock circuit 46, the output pulse signal D of the VCO 32 is synchronized with the reference pulse signal R, and n (6 in FIG. 2) during the period T. Including pulse. The pulse width of the pulse signal A is equal to one cycle of the pulse signal D. In addition, the phase detector 26, LPF3
0, the VCO 34, and the frequency divider 38 constitute a second phase lock circuit 48, and the output pulse signal E of the VCO 34 is synchronized with the reference pulse signal R and (n-1) (in the figure) during the period T (see FIG. 2 includes 5 pulses). The pulse width of the pulse signal B is equal to one cycle of the pulse signal E. The phase detector 24, the LPF 28 and the frequency divider 36 are respectively the phase detector 2
6, preferably the same as LPF 30 and VCO 38. In FIG. 2, the pulse numbers of the pulse signals D and E whose leading edges match the reference pulse signal R are 0,
The number of the pulse following this is shown in each pulse. In the following description, each pulse is identified by this number. Also,
This number is generally represented by m.

The output pulse signal D of the VCO 32 is supplied to the delay element 50 to be measured and delayed by the delay time which is the object to be measured.
2 and one input terminal of the AND circuit 54. The output pulse signal E of the VCO 34 is supplied to the clock terminal of the counter circuit 44 and one input terminal of the AND circuit 56. As described above, the pulse signals C and B are supplied to the load terminals of the counter circuits 42 and 44, and the common digital signals are supplied to the preset terminals from the register 52 such as a latch circuit controlled by the CPU 68 described later. The value k is supplied. Counter circuits 42 and 44
Is loaded with the digital value k when the first pulse of the pulse signals E and F, respectively, is supplied to the clock terminal when the pulse signals B and C are respectively at high level. Here, it is assumed that the counter circuits 42 and 44 are down-counter circuits, count down from k, and operate to generate an output pulse when the count reaches 0. Further, since the counter circuits 42 and 44 are loaded with the value k at the first pulse, the relationship between m and k is m =
k + 1.

The counter circuits 42 and 44 supply an output pulse to the other input terminals of the AND circuits 54 and 56, respectively, when the count value reaches 0 from the value k. At this time, each of the AND circuits 54 and 56 simultaneously receives a pulse at two input terminals and passes the (k + 1) th pulse of the pulse signals F and E, respectively. Phase detector 58
Generates a voltage corresponding to the phase difference of the (k + 1) th pulse of the pulse signals F and E at the output ends of the AND circuits 54 and 56. This phase difference voltage is generated over several cycles of the reference pulse signal R, supplied to the LPF 60, and averaged. This averaging reduces the error in the phase difference voltage due to the time lag of the pulse for each cycle.

The analog / digital converter (AD
C) 62, bus 64, memory 66, central processing unit (CPU) 68, and display 70 are components for performing automatic measurement. ADC 62 for a particular value k
Converts the phase difference voltage averaged by the LPF 60 into a digital value and supplies the digital value to the bus 64. The CPU 68 obtains an average value of the phase difference voltage over a predetermined number of cycles of the reference pulse signal R, for example, 50 cycles, and then stores this value in the k-th address of the memory 66 which is a random access memory, and Change k. This operation is repeated, and the phase difference voltage for each value k of 0 to (n-3) is stored in the memory 66. The display 70 forms the bus 64 and is controlled by the CPU 68, and finally displays the measurement result of the delay time.

The operation of the delay time measuring apparatus of the present invention will be described in more detail with reference to FIG. The output pulse signals A and B of the first and second phase lock circuits 46 and 48 are phase locked to a common reference pulse signal R. As described above, the pulse signals D and E are the periods T of the reference pulse signal R.
, Between n and (n-1) pulses, respectively. In FIG. 2, n = 6 is selected to simplify the description. Although the phase difference between the pulse signals D and E 0th pulse is 0, the phase difference Δ1 occurs at the leading edge of the 1st pulse because the number of pulses in the period T is different. Δ1 is
The minimum delay time Δmin measurable by the device of the present invention,
It is expressed by the following formula. Δ1 = Δmin = {T / (n−1)} − T / n = T / n (n−1) (1) For example, the frequency of the reference pulse signal R is 100 kHz (T
= 10 μs), and n can be selected to 2000.
Obtaining Δmin at this time is as follows. Δmin = 10 × 10 * (-6) / 2000 (2000-1) ≈10 × 10 * (-6) /4×10*6=2.5 ps (where N * n is N to the nth power) The phase difference Δ2 of the second pulse is expressed by the following equation. Δ2 = {2T / (n-1)}-2T / n = 2T / n (n-1) (2) Similarly, the phase difference Δm of the m-th pulse is represented by the following general formula. Δm = mT / n (n−1) (3) Then, the measurable maximum delay time Δmax is expressed by the following equation. Δmax = (n−2) T / n (n−1) (4)

As described above, the pulse signal C is transmitted to the delay element 4
It is delayed with respect to the pulse B by 0. This is because the pulse signal E is delayed by Δx by the delay element under test 50, and if not delayed, the counter circuit 42 is loaded with the 0th pulse of the pulse signal F and the counter circuit 44 is This is because the first pulse of the pulse signal E is loaded and the phase difference between the pulses of the same number cannot be obtained. Therefore, in order to prevent the counter circuit 42 from being loaded with the 0th pulse, the delay time of the delay element 40 may be selected to T / n which is the maximum value of the delay time of the pulse signal F.

The CPU 68 causes the register 52 to store k = 0,
When 1, 2, 3, ... (N-3) are sequentially set, as described above, the digital value corresponding to the phase difference between the pulses having the same number in the pulse signals E and F is stored in the memory 66. ..
When the storage operation is completed, the CPU 68 examines each address of the memory 66 to find the digital value having the smallest absolute value. If the digital value stored at the k'th address is the minimum value, the pulse signal D
And the phase difference of the k '+ 1st pulse of E will be the minimum. In FIG. 2, since the phase difference of the third pulse is almost 0, the value of the second address is the minimum. From this, the CPU 68 uses the formula (3) to calculate Δ as follows.
Find x. Δx = (k ′ + 1) T / n (n−1) The CPU 68 displays this measurement result in an appropriate digital display 7
Display at 0.

The preferred embodiment of the present invention has been described above, but it will be apparent to those skilled in the art that various modifications can be made. For example, although the difference in the denominator value of the frequency division ratio of the frequency divider is set to 1 in the above description, the difference may be further increased if the decrease in resolution is not a problem.

[0014]

[Effect] In the present invention, the delay time of the device under test is measured by utilizing the phase shift between the two pulses accurately generated by the two phase-locked loop circuits, so that it is not affected by drift or the like. , Can always make accurate measurements. Further, high resolution measurement is possible, and as described above, for example, when the frequency of the reference pulse signal R is selected to be 100 kHz and n is 2000, a measurement resolution of 2.5 ps can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a delay time measuring device of the present invention.

FIG. 2 is a timing diagram for explaining the operation of the apparatus of FIG.

FIG. 3 is a block diagram showing an example of a conventional delay time measuring device.

[Explanation of symbols]

 46 pulse generating means 48 second pulse generating means 50 delay element under test 42, 44, 52, 54, 56 pulse extracting means 58, 60 phase difference detecting means

Claims (1)

[Claims] 1. A first pulse generating means for generating a first predetermined number of pulses for each cycle of a reference pulse signal, and a second predetermined number of pulses smaller than the first predetermined number for each cycle of the reference pulse signal. Second pulse generating means, a delay element to be measured to which the pulse from the first pulse generating means is supplied, and a pulse of the reference pulse signal of the delay element to be measured and the pulse from the second pulse generating means. The phase difference detecting means for detecting the same two pulses within one cycle and the phase difference detecting means for detecting the phase difference between the two same pulses extracted by the pulse extracting means; A delay time measuring device for measuring the delay time of the measured delay means by searching for the same pulse at the minimum.