JPH05259841A - Voltage comparator circuit - Google Patents

Abstract

PURPOSE:To obtain the voltage comparator circuit whose hysteresis width is optionally set by using a high speed MOS transistor(TR). CONSTITUTION:Each load of Q11, Q12 being components of a differential amplifier uses a pMOS, a W length of Q13, Q14 and a W length of a Q15 of one load are selected to be 1:n and a W length of Q16, Q17 and a W length of a Q18 of other load are selected to be 1:n, and the Q15, Q18 having a W length being a multiple of (n) are used for output elements. For example, in the case of V1>V2, the Q11 is turned on, a drain current of the Q14 equal to a drain current of Q13 flows to a drain of the Q19 and the mirror current flows to the drain of the Q20. On the other hand, the Q12 is turned off, the collector of the Q12 is set to H by a drain of the Q15, the Q16 is turned off and no current flows to the drain of the Q17 and then, the drain of the Q20 is set to L and a V0 is inverted to an H by an INV.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a voltage comparison circuit.

[0002]

2. Description of the Related Art A conventional voltage comparison circuit is constructed as shown in FIG.

The circuit shown in this figure includes transistors Q41 ...
It is composed of Q45 and a constant current source i. The transistors Q41 and Q42 are npn-type transistors,
A differential input element is configured, and an input voltage I
N1 and IN2 are input, the emitters of both transistors Q41 and Q42 are grounded through a constant current source i, and the transistors Q41 and Q42 are connected to the high potential power source line through the collector → emitter of transistors Q43 and Q44, respectively. ing. The transistors Q43 and Q44 are lateral pnp type transistors, and the effective collector length thereof is divided into 1: n. These transistors Q43,
The collector of the effective length "1" of Q44 is commonly connected to each base, and the collector of the effective length "n" of transistor Q43 is connected to the collector of the effective length "1" of transistor Q44, which is effective of transistor Q44. Long "n"
Is connected to the collector of the effective length "1" of the transistor Q43. Transistor Q45 forms an output driver element whose base is connected to the collector of transistor Q41. The emitter is connected to the high potential power supply line, and the load L is connected to the collector serving as the output terminal.

In the above structure, when V1> V2 (hereinafter, this state is referred to as mode I), the transistor Q41 is turned on and the transistor Q42 is turned off. Therefore, the base potential of the transistor Q45 becomes "L", and the transistor Q45 is turned on. Therefore, the output signal V
0 becomes "H".

The operating currents of the transistors Q41 and Q42 when operating in the mode I are nI and I, respectively.
From this, the input voltage and the transistors Q1 and Q
The following equations hold for 2 and.

V1 = VBE41−VBE42 + V2 ΔV = V1 −V2 ΔV = (kT / q) ln (nI / Is) − (kT / q) ln (I / Is) where kT / q is a thermal voltage, and It is a value of about 26 mV. Further, Is is a reverse saturation current, VBE41 is a base-emitter voltage of the transistor Q41, and VBE42 is a base-emitter voltage of the transistor Q42. When the equation is transformed into a simple equation, ΔV = (kT / q) lnn is obtained.

When this is illustrated, a solid line as shown in FIG. 5 is obtained.

When V1 <V2 (hereinafter, this state is referred to as mode II), the transistor Q41 is turned off and the transistor Q42 is turned on. Therefore, transistor Q45
The base potential of the transistor becomes "H", and the transistor Q45 is turned off. Therefore, the output signal V0 becomes "L".

In the case of this mode II as well, the equation is obtained by the same calculation as the above equation. This is shown by the broken line in FIG.

Therefore, the hysteresis width VHYS can be expressed as follows: VHYS = 2ΔV = 2 (kT / q) lnn with respect to ΔV, and the hysteresis width is determined by 1: n.

Therefore, according to the conventional circuit using the lateral pnp type transistor, a desired hysteresis width can be set by freely selecting the ratio of 1: n.

[0012]

However, the response speed of the circuit as a whole is governed by the slow operation speed of the pnp type transistor, and it is becoming impossible to satisfy the ever-increasing demand for higher speed. Therefore, in reality, there is a limit to the realization of a circuit device in which a high-speed voltage comparison circuit must be incorporated.

The present invention has been made in view of the above problems of the prior art, and an object of the present invention is to provide a voltage comparison circuit with an improved operation speed.

[0014]

A voltage comparison circuit of the present invention differentially amplifies first and second input signals, and a differential amplifier having its first and second output terminals, and this differential amplifier. A first MOS transistor in which the low potential side terminal of the current path is connected to the first output terminal of the amplifier, and the low potential side terminal and the gate are commonly connected, and a current path of the first MOS transistor N of the second MOS transistor whose current output terminal is connected to the input terminal of the current mirror circuit and which is designed to output a current that is one time the current flowing through It has a gate width twice as large and outputs a current n times as large as the current flowing through the current path of the first MOS transistor, and its current output terminal is connected to the second output terminal of the differential amplifier. Third MOS transistor And Njisuta, fourth of said differential second low-potential-side terminal of the current path to the output terminal of the amplifier is connected and the the low potential side terminal and the gate are connected in common
And a fifth MOS transistor whose current output end is connected to the output terminal of the current mirror circuit. And has a gate width n times larger than that of the fourth MOS transistor, and outputs a current n times the current flowing through the current path of the fourth MOS transistor. A sixth M connected to the first output terminal of the amplifier
An OS transistor, a seventh MOS transistor that constitutes an input element of the current mirror circuit, and a high-potential side terminal in the current path thereof is an input terminal of the current mirror circuit, and an output element of the current mirror circuit. The eighth MOS transistor, which is connected to a high-potential-side terminal in the current path and functions as an output terminal of the current mirror circuit, provides the first,
The voltage of the second input signal is compared.

In the above structure, for example, the first to sixth M
The OS transistor is composed of pMOS, and the seventh,
The eight MOS transistors can be configured by nMOS.

Alternatively, the first to sixth MOS transistors can be constructed by nMOS and the seventh and eighth MOS transistors can be constructed by pMOS.

[0017]

According to the present invention, since the hysteresis width is determined by the gate widths of the first to sixth MOS transistors, the hysteresis width is arbitrarily set by the MOS transistor faster than the pnp type transistor. The voltage comparison circuit can be formed, which is extremely advantageous for speeding up.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a circuit configuration of a voltage comparison circuit according to an embodiment of the present invention.

The circuit of this embodiment has transistors Q11 to Q11.
It is composed of 20, a current source i, and an inverter INV.

Transistors Q11 and Q12 are npn-type transistors and form an input element. The bases of these transistors Q11 and Q12 have a voltage V, respectively.
1 and V2 are input.

The transistors Q13 to Q18 are pMOS transistors, the transistors Q13 to Q15 form a load circuit of the transistor Q11, and the transistors Q16 to Q18 form a load circuit of the transistor Q12.

The transistor Q13 constitutes a first MOS transistor, the source of which is connected to the high potential power source line, and the drain of the transistor Q13 is connected to the collector of the transistor Q12.

The transistor Q14 constitutes a second MOS transistor, the source of which is connected to the high potential power supply line, and the drain of the transistor Q14 is connected to the input terminal of a current mirror circuit (transistors Q19, Q20) described later. Has been done. The gate of the transistor Q14 is commonly connected to the gate of the transistor Q13.

The transistor Q15 constitutes a third MOS transistor, the source of which is connected to the high potential power source line, and the drain of the transistor Q15 is connected to the collector of the transistor Q12 of the differential amplifier. This transistor Q15 also has a W length n times that of the transistor Q13, and its gate is commonly connected to the gate of the transistor Q13 so that the drain current of the transistor Q13 is n.
Double the current is flowing to its drain.

The transistor Q16 constitutes a fourth MOS transistor, the source of which is connected to the high potential power supply line, and the drain of the transistor Q16 is connected to the collector of the transistor Q11.

The transistor Q17 constitutes a fifth MOS transistor, the source of which is connected to the high potential power supply line, and the drain of the transistor Q17 is connected to the output terminal of the current mirror circuit (transistors Q19 and Q20) described later. Has been done. The gate of the transistor Q17 is commonly connected to the gate of the transistor Q16.

The transistor Q18 constitutes a sixth MOS transistor, the source of which is connected to the high potential power source line, and the drain of the transistor Q18 is connected to the collector of the transistor Q11 of the differential amplifier. This transistor Q18 also has a W length n times that of the transistor Q16, and its gate is commonly connected to the gate of the transistor Q16, so that the drain current n of this transistor Q16 is n.
Double the current is flowing to its drain.

The transistor Q19 is composed of an nMOS and constitutes a seventh MOS transistor, the source of which is connected to the ground which is the low potential side power supply line, and the drain and the gate of which are commonly connected to form the current mirror circuit. Forming an input element of. The common connection point between the drain and gate of the transistor Q19 serves as the input terminal of the current mirror circuit.

The transistor Q20 is composed of an nMOS and constitutes an eighth MOS transistor, the source of which is connected to ground and the gate of which is commonly connected to the gate of the transistor Q19 to form the output element of the current mirror circuit. is doing. The drain of the transistor Q20 serves as the output terminal of the current mirror circuit, and the load L is connected via the inverter INV.

Next, the logic will be described.

First, in the mode I (V1> V2), the transistor Q11 is turned on. Therefore, the transistor Q14 which has a drain current of the transistor Q13 becomes one time.
Drain current flows to the drain of transistor Q19,
The mirror current flows through the drain of the transistor Q20.

On the other hand, the transistor Q12 is turned off, and since the drain of the transistor Q12 is connected to the drain of the transistor Q15, it becomes "H" (high level), the transistor Q16 is turned off, and the drain of the transistor Q17 has a current. Does not flow.

Therefore, the drain of the transistor Q20 becomes "L", which is inverted by the inverter INV and the output signal V0 becomes "H".

Next, in the mode II (V1 <V2), the transistor Q12 is turned on. Therefore, the transistor Q17, which has a drain current of the transistor Q16, becomes one time.
Drain current flows to the drain side of the transistor Q20.

On the other hand, the transistor Q11 is turned off, and the drain of the transistor Q11 is "H" (high level) because it is connected to the drain of the transistor Q18, the transistor Q13 is turned off, and the drain of the transistor Q14 has a current. Does not flow. Therefore, the drain current of the transistor Q19 disappears, and the drain current of the transistor Q20 does not flow.

Therefore, the drain of the transistor Q20 becomes "H", which is inverted by the inverter INV and the output signal V0 becomes "L".

As is clear from the above, the circuit of this embodiment can obtain the same logic as the circuit of FIG. 4 described above. Depending on the ratio of the W lengths of the transistor Q13 or Q16 and the transistor Q15 or Q18, the above equations (1) to (3) are established at the time of operation as the mode I and the mode II, and the equation is finally established. Therefore, according to the circuit of this embodiment, a desired hysteresis width can be set by freely selecting the ratio of 1: n.

Moreover, since the operation is achieved by the MOS transistor, high-speed response can be obtained.

FIG. 2 shows a comparison of the simulation results of the delay of the V0 potential with respect to the V1 potential at the rise of V1 between the circuit of the present invention and the conventional circuit. Here, V2 = 2V was used as the reference voltage, and the time from when V1 exceeded 2V to when V0 rose to 5V was measured.

As shown in this figure, in the conventional circuit, V1
It took 3.8 .mu.s from the rise of V.sub.0 to the rise of V.sub.0, while it was shortened to 25 ns in the circuit of the invention.

FIG. 3 shows V of the circuit of the present invention and the conventional circuit.
1 shows a comparison of simulation results of the delay of the V0 potential with respect to the V1 potential at the fall. Also in this case, V2 = 2V is used as the reference voltage, and the time from when V1 drops below 2V to when V0 drops to 0V is measured.

As shown in this figure, in the conventional circuit, V1
It took 4.7 .mu.s from the fall of V0 to the fall of V0, while it was shortened to 30 ns in the circuit of the present invention.

As is clear from these results, the circuit of the present invention can improve the response speed.

In the above embodiment, the first to sixth MOS transistors Q13 to Q18 are constituted by pMOS,
The eighth MOS transistors Q19 and Q20 are composed of nMOS, but conversely, the first to sixth MOS transistors Q13 to Q18 are composed of nMOS, and the seventh and eighth MOS transistors are formed.
The transistors Q19 and Q20 can also be formed by pMOS.

[0046]

As described above, according to the present invention, the hysteresis width is determined by the gate widths of the first to sixth MOS transistors. Therefore, the speed of the MOS transistor is higher than that of the pnp type transistor. As a result, a voltage comparison circuit having a hysteresis width arbitrarily set can be formed, which is extremely advantageous for speeding up.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a voltage comparison circuit according to an embodiment of the present invention.

FIG. 2 is a characteristic curve diagram showing the results of simulating the delay of the output potential with respect to the input potential at the rise of the input potential between the circuit of the present invention and the conventional circuit in comparison.

FIG. 3 is a characteristic curve diagram showing the results of simulating the delay of the output potential with respect to the input potential when the input potential of the circuit of the present invention and the conventional circuit fall, for comparison.

FIG. 4 is a circuit diagram of a conventional voltage comparison circuit.

5 is an explanatory diagram of the operation of the voltage comparison circuit shown in FIG.

[Explanation of symbols]

Q11, Q12 npn-type transistor constituting differential amplifier Q13 first MOS transistor composed of pMOS Q14 second MOS transistor composed of pMOS Q15 third MOS transistor composed of pMOS fourth MOS transistor composed of pMOS Q17 pMOS 5th MOS transistor Q18 consisting of pMOS 6th MOS transistor consisting of pMOS Q19 7th MOS transistor consisting of nMOS Q20 8th MOS transistor L consisting of nMOS
load

Claims (3)

[Claims] 1. A differential amplifier which differentially amplifies first and second input signals and has first and second output terminals thereof, and a first output terminal of the differential amplifier having a current path thereof. A first MOS transistor having a low-potential side terminal connected thereto and the low-potential end and a gate connected in common, and one of the currents flowing through the current path of the first MOS transistor.
A second MOS transistor whose current output terminal is connected to the input terminal of the current mirror circuit and which has a gate width n (n> 1) times larger than that of the first MOS transistor. A third MOS transistor having a current output terminal connected to the second output terminal of the differential amplifier, the current output terminal being configured to output a current n times the current flowing through the current path of the first MOS transistor. A fourth MOS transistor in which the low potential side terminal of the current path is connected to the second output terminal of the differential amplifier, and the low potential end and the gate are commonly connected, and the fourth MOS transistor 1 of the current flowing through the current path of the transistor
A fifth MO whose current output end is connected to the output terminal of the current mirror circuit
The S-transistor and the fourth MOS transistor have a gate width n times larger than that of the fourth MOS transistor, and are configured to output a current n times the current flowing through the current path of the fourth MOS transistor, the current output end of which is A sixth M connected to the first output terminal of the differential amplifier
An OS transistor, a seventh MOS transistor that constitutes an input element of the current mirror circuit, and a high potential side terminal in the current path thereof is an input terminal of the current mirror circuit, and constitutes an output element of the current mirror circuit. A voltage comparison circuit that includes a load connected to a high-potential-side terminal in the current path and that functions as an output terminal of the current mirror circuit, and that compares the voltages of the first and second input signals. .. 2. The first to sixth MOS transistors are pMOS.
2. The voltage comparison circuit according to claim 1, wherein the seventh and eighth MOS transistors are nMOS. 3. The first to sixth MOS transistors are nMOS.
2. The voltage comparison circuit according to claim 1, wherein the seventh and eighth MOS transistors are pMOS.