JPH05258578A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To increase a noise margin of an input buffer circuit of a semiconductor memory device and to provide a high speed and a stabilized operation even when a capacity is increased. CONSTITUTION:The semiconductor memory consists of a memory cell array 6 and a timing signal generator circuit 11 generating the timing signal required for an internal operation by detecting the change of an address input signal. At least one of the output signals phi0 outputted from the timing signal generator circuit 11 is supplied to an input buffer circuit 10 of the semiconductor memory device and the response characteristic of the buffer circuit 10 is controlled so that the signal with the amplitude of an interface level inputted from the outside is inverted and amplified to a signal with the amplitude of an internal logic.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input buffer circuit used in a semiconductor memory device.

[0002]

2. Description of the Related Art With the remarkable progress of semiconductor manufacturing technology,
High-density integration of devices has become possible, and the storage capacity of semiconductor memories has increased. The increase in capacity is very convenient for a device equipped with a semiconductor memory device because the amount of information stored therein increases, but it takes time to read the data.

Conventionally, in order to realize a high speed semiconductor memory device, it has been attempted to shorten the time required for the read operation of the memory cell and to reduce the delay time of the input / output section.

FIG. 5 shows a circuit configuration diagram of a general semiconductor memory device currently used. As the circuit configuration conventionally used, the address input buffer circuit 1,
In addition to the X decoder circuit 2, the Y decoder circuit 3, the sense amplifier circuit 4, the output buffer circuit 5, and the memory cell array 6, a detection circuit 7 for detecting an address input signal, and a memory in response to the output signal of the detection circuit 7 In many cases, it is composed of a timing signal generating circuit 8 for performing a high-speed reading operation of a cell or a stable operation.

FIG. 6 shows an operation timing chart of the semiconductor memory device having the above structure. When the address input signal changes, the output signals Ai and Aj of the input buffer circuit 1 correspondingly change, and in response to this, the X decoder 2 and the Y decoder 3
Works. On the other hand, the output signal A of the input buffer circuit 1
When i and Aj change, the detection circuit 7 also operates,
In response to this, a pulse signal (for example, a precharge signal φ ₁ for precharging the bit line, which is necessary for reading the memory cell from the timing signal generating circuit 8 and the output buffer is deactivated only during the internal read operation period. Signal φ ₂ ) for generating the read operation.

In the semiconductor memory device having such a circuit configuration, in order to reduce the delay time of the input buffer circuit section 1 and the output buffer circuit 5, the driving capability of the transistors forming the input / output section is increased. Is being attempted.

FIG. 7 shows a general input buffer circuit composed of an NMOS (N channel MOS) transistor and a PMOS (P channel MOS) transistor. For example, when the amplitude of the external interface level that supplies a signal to the semiconductor memory device is the TTL level, the input buffer circuit receives the input LOW level (V _IL ) 0.8V, HI.
The characteristics of the NMOS and PMOS transistors forming the circuit are set so as to respond to the GH level (V _IH ) of 2.2 V, respectively, and the inversion voltage (V _INV ) is determined.

[0008]

However, in the input buffer circuit having the above configuration, as shown in FIG. 9, when the power supply voltage V _CC rises, the inversion voltage V _INV also rises, and the noise margin V _IH − of the input buffer circuit. V _INV becomes smaller. Further, the operation of the output buffer circuit significantly increases the instantaneous current, which makes the internal ground potential (GND in FIG. 6) unstable. As a result, the output Ai of the address input buffer circuit is once inverted as shown by the broken line in the timing chart of FIG. 6, and the timing generation circuit 8 may be activated to cause a malfunction. Therefore, in order to obtain stable operation,
Stable operation is ensured by reducing the drive capability of the output buffer circuit to reduce the instantaneous current, or by reducing the responsiveness of the input buffer circuit to ensure stable operation. At the expense of.

The present invention has been made in view of the problems of the conventional circuit as described above, and makes it possible to expand the noise margin of the input buffer circuit without impairing the high-speed performance and enable more stable operation. Is.

[0010]

A semiconductor memory device of the present invention is a memory cell array having a plurality of memory cells, and a timing signal generation circuit for detecting a change in an address input signal and generating a timing signal necessary for an internal operation. And an input buffer circuit to which at least one output signal output from the timing signal generating circuit is applied and which is controlled by the output signal to control its own response characteristics, and which has an interface level input from the outside. And an input buffer circuit for converting and amplifying an amplitude signal into an internal logic amplitude signal.

[0011]

In the input buffer circuit, the response characteristic is controlled only at a predetermined timing related to the read operation of the memory cell, and the noise margin of the input buffer circuit is expanded without hindering the original operation of the semiconductor memory device. It enables high-speed and stable operation even when the capacity of the semiconductor memory device is increased.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. Similar to the conventional semiconductor memory device, an address input buffer circuit 10, an X decoder circuit 2, a Y decoder circuit 3, a sense amplifier circuit 4, an output buffer circuit 5, a memory cell array 6, and a detection circuit 7 for detecting an input signal are provided. Set up. Here, also in the present embodiment, the detection circuit 7
Although the timing signal generating circuit 11 for controlling the high-speed read operation or the stable operation of the memory cell is provided in response to the output signal of, the timing signal generating circuit 11 has the following circuit configuration. . When the output signals Ai, Aj of the input buffer circuit 10 change, the X decoder 2 and the Y decoder 3 operate in response thereto, while the output signals Ai, Aj change, the detection circuit 7 also operates. In response to the pulse signal necessary for reading the memory cell 6 from the timing signal generating circuit 11 (for example, a precharge signal φ ₁ for precharging the bit line, the internal read operation period output buffer 5
To generate a signal φ ₂ etc.) for deactivating. Further, the timing signal generating circuit 11 of the present embodiment uses the above φ ₁ and φ ₂
In addition, a signal φ ₀ for controlling the response characteristic of the input buffer circuit 10 is generated.

FIG. 2 shows an operation timing chart. When the level of the address signal Ai output from the input buffer circuit 10 changes, the X decoder 2 and the Y decoder 3 operate in response to this, and a predetermined memory cell is selected from the array 6 to realize reading. On the other hand, by the output from the detection circuit 7, the signal φ ₀ from the timing signal generation circuit 11
φ ₁ and φ ₂ are output. The signal φ ₂ is at the “High” level for a certain period T after the level of the input signal Ai is changed, so that the output buffer circuit 5 is held in the inactive state,
When the internal read data is determined after the elapse of a certain period of time T, the level becomes “Low” again to activate the output buffer circuit 5, and the internal read data output from the memory cell is transmitted to the outside through the output buffer circuit 5. ..

Here, the level of the signal φ ₂ is "High".
Immediately before the end of the period T held at h ″, another signal φ
₀ is set to the "High" level for a certain period t. This signal φ ₀ is given to the input buffer circuit 10 as a signal for controlling the response characteristic of the circuit.

As shown in FIG. 3, the input buffer circuit 10 formed of CMOS transistors has a gate connected to the signal φ ₀ between the PMOS transistor Q _P and the power supply V _CC.
OS transistor Q _P1 and P whose gate is connected to GND
It is configured by connecting a MOS transistor Q _P2 . Therefore, when the signal φ ₀ becomes “High” level, PMO
The S transistor Q _P1 is turned off, and the voltage dropped by the transistor Q _P2 is supplied as the power supply voltage of the PMOS transistor Q _P of the input buffer circuit 10. That is, the inversion voltage can be temporarily lowered and the noise margin can be expanded while the signal φ ₀ is in the “High” level period. As a result, the output buffer circuit 5
Even if the internal ground potential becomes unstable due to the operation of
As shown in FIG. 2, the input buffer circuit 10 maintains a stable state without being inverted.

Another embodiment of the input buffer circuit is shown in FIG. In this embodiment, the input buffer circuit is the first C
The PMOS transistor Q _P2 described in FIG. 3 is connected between the source of the PMOS transistor Q _P of the transistors Q _P and Q _N forming the MOS and the power supply voltage V _CC, and
A NMOS transistor Q _N2 whose gate is connected to the power supply voltage V _CC is connected between the source of the OS transistor Q _N and GND, and a second transistor is connected in parallel with the first CMOS.
Of the transistors Q _P 'and Q _N ' that make up the CMOS of
A PMOS transistor T _P having a gate to which a signal φ ₀ is input is connected between the source of the OS transistor Q _P 'and the power supply voltage V _CC, and is inverted by the inverter 12 between the source of the NMOS transistor Q _N ' and GND. Φ ₀ is connected to an NMOS transistor T _N whose gate is applied. The signal φ ₀ is given at the timing shown in FIG. Also in the circuit configuration of the present embodiment, the response speed can be temporarily reduced while the signal φ ₀ is in the “High” level period, and the same effect can be obtained.

[0017]

As described above, according to the present invention, the response characteristic of the input buffer circuit is controlled by applying the timing signal, thereby expanding the noise margin of the input buffer circuit and increasing the capacity of the semiconductor memory device. It enables high speed and stable operation.

[Brief description of drawings]

FIG. 1 is a block diagram of a semiconductor memory device according to the present invention.

FIG. 2 is a signal timing chart of essential parts of the embodiment.

FIG. 3 is a specific circuit diagram of an input buffer circuit of the same embodiment.

FIG. 4 is another specific circuit diagram of the input buffer circuit of the same embodiment.

FIG. 5 is a block diagram of a conventional semiconductor memory device.

FIG. 6 is a signal timing diagram of a conventional circuit.

FIG. 7 is a conventional input buffer circuit.

FIG. 8 is an input voltage characteristic diagram.

FIG. 9 is a relationship diagram of a power supply voltage and an inversion voltage.

[Explanation of symbols]

6 memory cell array 5 output buffer circuit 10 input buffer circuit 11 timing signal generation circuit φ ₀ , φ ₁ , φ ₂ timing signal

Claims (1)

[Claims] 1. A memory cell array having a plurality of memory cells, a timing signal generating circuit for detecting a change in an address input signal and generating a timing signal necessary for an internal operation, and at least an output from the timing signal generating circuit. An input buffer circuit that receives one output signal and is controlled by the output signal to control its own response characteristics, and converts an interface level amplitude signal input from the outside into an internal logic amplitude signal. A semiconductor memory device comprising an input buffer circuit for amplifying.