JPH05252486A - Scanning converter for video signal - Google Patents

Abstract

PURPOSE:To make a frame end scanning conversion while keeping the smooth movement of picture as much as possible by generating interpolation frames by means of the frame interpolation for movement compensation. CONSTITUTION:A movement vector extraction circuit 3 performs the arithmetic operation between a reproduction frame signal sequence VF from a scanning line regeneration circuit 1 and delay signal sequence VFD from a frame delay circuit 2 to extract a movement vector signal MV per frame. An interpolation frame 4 corrects the shift amount in the horizontal and vertical directions according to the movement vector signal MV for the signal sequences VF and VFD to generate a signal sequence VMC of the movement-compensated interpolation frame. A selection circuit 6 selectively outputs the signal sequence of the delay- adjusted reproduction frame or the signal sequence VMC from the circuit 4 by means of a control signal CT, generating a signal sequence VP for non- interlace scanning at its output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal scanning conversion device, and more particularly to a video signal for generating an interlaced scanning signal sequence by rearranging a sequential scanning signal sequence of the same frame on the transmitting side. And a scan conversion device suitable for performing scan conversion from interlaced scan to non-interlaced scan.

[0002]

2. Description of the Related Art One of the techniques for improving the image quality of television images is signal processing for frame-completed scan conversion. This is a signal sequence of odd scanning lines and a signal sequence of even scanning lines of the same frame of the image signal sequence of non-interlaced scanning (sequential scanning) on the transmission side. The first field and the second field of interlaced scanning, respectively. The scanning line signal sequence is generated to form a video signal for interlaced scanning of the current television system. On the receiving side, the signal sequence of the first field and the second field of the interlaced scanning video signal is rearranged as the signal sequence of the odd scanning line and the even scanning line of the non-interlaced scanning, respectively, and the signal sequence of the reproduction frame is reproduced. To generate. Further, a signal sequence of the interpolation frame is generated by the frame interpolation operation. And the playback frame, and
The non-interlaced scanning image signal sequence is reproduced by the interpolation frame, and the scan conversion from interlaced scanning to non-interlaced scanning is performed. Then, the image is displayed in the form of non-interlaced scanning to obtain a high-quality reproduced image with little deterioration of the dynamic resolution characteristic.

[0003]

In the above-mentioned prior art, there is a problem that due to the frame-completed scan conversion, the reproduced image sometimes suffers from strobe obstruction that impairs the smoothness of the motion and deteriorates the image quality. is there.

It is an object of the present invention to provide a video signal scan conversion apparatus which realizes frame-complete scan conversion with little image quality interference in which smoothness of motion is impaired.

[0005]

In the frame-completed scan conversion, the reproduced frames obtained by the rearrangement operation of the signal series of interlaced scanning are composed of the signal series of one frame at the same time. Therefore, it is possible to accurately detect the motion information during this period, for example, the motion vector by the calculation between the signal sequences of the adjacent reproduction frames. Then, the signal sequence of the interpolated frame is generated by the frame interpolation operation of the motion compensation according to the detected motion vector. As a result, since it is possible to generate a signal sequence of an interpolation frame with high accuracy with respect to motion, it is possible to reduce image quality disturbance that impairs the smoothness of motion.

Further, this disturbance is easily noticeable because the visual characteristics are sensitive to movements such as horizontal pan and vertical pan. On the other hand, since a motion vector is uniform over the entire screen for this type of motion, it is possible to detect with high accuracy. Therefore, by using the interpolation frame generated by the frame interpolation operation of the motion compensation only for the movement such as the horizontal pan and the vertical pan, it is possible to reduce the image quality disturbance that impairs the smoothness of the movement.

[0007]

The principle of frame completion scan conversion according to the present invention will be described with reference to FIG. In the frame completion scan conversion method, the scan lines L ₁ , L ₃ , L ₅ of the first field of interlaced scan are used.
The signals of the scanning lines L ₂ , L ₄ , L ₆ in the second field are all composed of the same frame signal sequence of non-interlaced scanning (sequential scanning).

Therefore, the signal sequence of one frame of non-interlaced scanning can be reproduced by the rearrangement operation of these signal sequences of interlaced scanning. That is,
The signals of the scanning lines L ₁ , L ₃ , L ₅ ... Of the first field are odd scanning lines of non-interlaced scanning, and the scanning lines L ₂ , L ₄ , L _{6 of} the second field are even scanning lines. By rearranging as a series, one reproduction frame can be constructed.

On the other hand, the signal sequence of the interpolation frame constituted by the scanning lines of the dot portion of the non-interlaced scanning system has conventionally been subjected to a simple frame interpolation operation, for example, repetition of the signal sequence of the immediately preceding reproduction frame, or It is generated by the average value of the signal series of the playback frames before and after. Then, a signal sequence of the non-interlaced scanning system is generated by the signal sequence of the reproduction frame and the interpolation frame, and the scan conversion from the interlaced scanning to the non-interlaced scanning is performed. For this reason, in the reproduced image, image quality obstruction in which smoothness of motion is impaired is also conspicuous.

In the present invention, the interpolation frame is generated by the motion compensation frame interpolation operation. That is, the motion vector between adjacent reproduction frames is extracted to obtain the movement amount of the motion between frames as v (v _x , v _y ). And
Based on this movement amount, 1 for the signal sequence of the playback frame
A signal sequence in which the movement of / 2v (1 / 2v _x , 1/2 v _y ) is corrected is created, and the signal sequence of the interpolation frame is generated by this. By the frame interpolation operation of the motion compensation, the motion of the signal sequence of the interpolation frame can be displayed more accurately, so that it is possible to reduce the image disturbance that impairs the smoothness of the motion.

A motion compensation frame interpolation operation requires a motion vector, which can be extracted with high accuracy by arithmetic processing between reproduction frames. The reason is that each reproduction frame is composed of a signal sequence of the same time.

Further, the disturbance that impairs the smoothness of the movement is easily detected because the visual characteristics are sensitive to the movement such as horizontal pan and vertical pan. On the other hand, when the entire screen such as horizontal pan and vertical pan moves uniformly in the horizontal and vertical directions, the motion vector can be detected extremely accurately. Therefore, in the case of horizontal panning and vertical panning motion, a signal sequence of an interpolation frame is generated by a frame interpolation operation of motion compensation, and in other cases, a conventional frame interpolation operation is performed, for example, a signal of the immediately preceding reproduction frame. It is also possible to generate the signal sequence of the interpolation frame by repeating the sequence, the average value of the signal sequences of the reproduction frames before and after the sequence, and the like. This also makes it possible to efficiently reduce image disturbance that impairs the smoothness of movement.

As described above, according to the present invention, an accurate motion vector can be extracted from a signal sequence of a reproduction frame. Therefore, a signal sequence of an interpolation frame is generated by a frame interpolation operation of motion compensation based on the motion vector. It is possible to reduce image quality disturbance that impairs the smoothness of movement.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows the overall block construction of a first embodiment of the present invention. The interlaced scanning signal series V _I (for example, R, G, B signals of three primary colors, or luminance and two color difference signals) is input to the scanning line rearrangement circuit 1, and the rearrangement operation of the signal series shown in FIG. 1 is performed. In addition, the time axis compression processing is performed to create a reproduction frame signal series V _F.

In the motion vector extraction circuit 3, the signal sequence V
_{The F} and frame delay circuit 2 performs an arithmetic operation with the signal sequence V _FD delayed by one frame to extract the motion vector signal M _V per frame.

In the interpolation frame generation circuit 4, the signal series V
Horizontal with respect to _F and V _{FD according} to the motion vector signal M _V ,
The amounts of movement ΔX and ΔY in the vertical direction are corrected to generate a motion-compensated interpolated frame signal series V _MC .

The selection circuit 6 alternately selects and outputs the signal sequence of the reproduction frame delayed by the delay circuit 5 and the signal sequence of the interpolated frame by the control signal CT to output the non-interlaced scanning signal sequence V _P. To generate.

Each block will be described below with reference to embodiments.

FIG. 3 shows an embodiment of the scanning line rearrangement circuit 1, which comprises a memory circuit 7 and a control circuit 8.

The interlaced scanning signal series V _I is a WT mode operation having a cycle of one frame period, and the scanning lines L ₁ , L ₃ ... In the first field, and the scanning lines L ₂ , L in the second field. The signals of ₄ , ... Are written in the memory circuit 7.

Reading from the memory circuit is performed during one frame period of non-interlaced scanning in the RD mode operation. In this case, the first field of the interlaced scan,
The rearrangement operation is realized by alternately reading the signals of the second field, and the signal sequence V _F of the reproduction frame of the time series non-interlaced scanning of L ₁ , L ₂ , L ₃ , L ₄ , ... Is generated. To do.

An embodiment of the motion vector extraction circuit 3 is shown in FIG.
Shown in. In this embodiment, the motion vector is extracted by the block matching method. The signal sequence V _FD is input to the reference block signal generation circuits 9, 10 and 11 and produces signals corresponding to the reference blocks B ₁ , B ₂ , ... _BN (horizontal L pixels × vertical M pixels), respectively. In addition, the signal sequence V _F is input to the reference block signal generation circuit 12, and the reference block B
A signal corresponding to R (horizontal L pixel × vertical M pixel) is created.

In the coincidence determination circuit 13, B _i (i = 1, ...
N) and the signal pattern of BR are detected whether or not they match. When they match, 1 is output, and when they do not match, 0 is output.

The motion vector detection circuit 14 detects a reference block B _i that matches the standard block BR from the states of the output signals of these match determination circuits, and the motion vector corresponding to this reference block → v _i = (ΔX _i , ΔY _i ) is output as a motion vector signal M _V.

FIG. 5 shows another embodiment of the motion vector extraction circuit 3, which extracts a moving object region and detects a motion vector from this. The moving object region extracting circuit 15 extracts a moving object as a moving object region signal MO by subtracting the signal sequences V _F and V _FD .

The signal MO and the signal MOD delayed by one frame period by the frame delay circuit 16 are inputted to the horizontal movement amount detection circuit 17 and the vertical movement amount detection circuit 18, respectively, and the horizontal movement amount ΔX per frame, Vertical movement amount ΔY
To extract.

In the motion vector detecting circuit 19, the motion vector → v = (ΔX, Δ) from the horizontal and vertical movement amounts ΔX, ΔY.
The information of Y) is output as the motion vector signal M _V.

Next, an embodiment of the interpolation frame generation circuit 4 is shown in FIG. In the motion correction signal generation circuit 20, the horizontal and vertical directions of the signal series V _F and V _FD are (1/2) ΔX and (1/2), respectively, according to the motion vector signal M _V.
ΔY (signal V _FD ), (−1/2) ΔX, (−1/2) ΔY
A signal sequence whose position is shifted by (signal V _F ) is generated.
Then, the adder circuit 21 takes the average value of both signals and generates a motion-compensated interpolated frame signal series V _MC .

FIG. 7 shows an embodiment of the motion correction signal generation circuit 20. It is configured by a combination of the 1-line delay circuit 22 and the 1-pixel delay circuit 23, and each of these outputs is a signal whose position is shifted by the horizontal direction ΔX _i and the vertical direction ΔY _i . These signals are input to the selection circuit 24, and a signal whose position is shifted in the horizontal and vertical directions by a corresponding amount is selected by the motion vector signal M _V and output.

In the present embodiment, since the signal sequence of the interpolated frame is generated by the motion-compensated frame interpolation operation, a scan conversion device from interlaced scanning to non-interlaced scanning with less image interference that impairs the smoothness of motion is realized. it can.

Next, a second embodiment according to the present invention is shown in FIG. In this embodiment, a signal sequence of an interpolated frame is generated by a motion-compensating frame interpolation operation with respect to horizontal panning, vertical panning, and other movements in which image quality interference is noticeable.

The interlaced scanning signal series V _I is subjected to a signal series rearrangement operation and a time axis compression operation in the scanning line rearrangement circuit 1 to form a reproduction frame signal series V _F. The motion vector extraction circuit 3 extracts the motion vector signal M _V from the signal sequence V _F and the signal sequence V _FD delayed by the frame delay circuit 2. The motion mode determination circuit 25 determines the motion of horizontal pan and vertical pan from the form of the signal M _V , and produces a mode control signal RCT. The interpolation frame generation circuit 26 generates a signal sequence V _MC of an interpolation frame by a motion compensation frame interpolation operation for vertical panning and horizontal panning motions and a conventional frame interpolation operation for other motions. These operations are controlled by the mode control signal RCT.

The signal sequence of the reproduced frame and the signal sequence of the interpolated frame whose delays have been adjusted by the delay circuit 27 are alternately selected and output by the selection circuit 6 to generate the non-interlaced scanning signal sequence V _P.

Since the scanning line rearrangement circuit 1 and the motion vector extraction circuit 3 can be realized in the same manner as that shown in the first embodiment, other block configurations will be described below.

FIG. 9 shows an embodiment of the motion mode determination circuit 25. For horizontal panning and vertical panning, this kind of motion is detected by utilizing the property that the motion vector is uniform over the entire screen.

The motion vector counting circuit 28 measures the type (direction and size) of the motion vector and the number of occurrences of the motion vector over the period of one frame. Then, the maximum count vector extraction circuit 29 detects the motion vector having the largest number of occurrences and generates it as the motion vector signal M _VP .

On the other hand, the generation vector distribution detection circuit 30 determines whether or not the motion vector signal M _VP exists uniformly over the period of one frame. Then, if it exists in the entire period of one frame, it is determined that the movement is horizontal panning or vertical panning, and 1 is output to the motion mode signal PM, and 0 is output otherwise.

In the motion compensation control signal generating circuit 31, when the signal PM is 1, the motion vector signal M _VP is used for performing motion compensation control, and when the signal PM is 0, a motion vector signal of zero (ΔX = (Corresponding to ΔY = 0) is output as the mode control signal RCT.

Next, FIG. 10 shows an embodiment of the interpolation frame generation circuit 26. The signal sequence V _FD of the playback frame is
The signal for the period of one frame is written in the memory circuit 32. The WT control signal generating circuit 33 generates control signals, address signals and the like necessary for this writing operation.

On the other hand, the read operation from the memory circuit is performed by the control signal and the address signal from the RD control signal generating circuit 34 to generate the interpolated frame signal series V _MC .

The operation of this circuit is performed by the mode control signal R
Controlled by CT, when the signal RCT is a motion vector of zero, the same address signal as the write operation is generated. Therefore, in this case, the signal sequence of the reproduction frame is generated as it is as the signal sequence of the interpolation frame, and the interpolation frame is generated by the conventional frame interpolation operation (repetition of the reproduction frame immediately before).

On the other hand, the signal RCT is the motion vector signal M _VP.
In the case of, an address signal modified corresponding to this is generated. As a result, from the memory circuit 32, a signal sequence in which the horizontal pan and vertical pan movements, which are displaced in the horizontal and vertical directions, are compensated for is generated as an interpolation frame,
Realizes the operation of frame interpolation by motion compensation.

As described above, according to the present embodiment, it is possible to reduce the interference of horizontal panning and vertical panning movements, which are likely to cause image quality interference, with simple signal processing. Then, a scan conversion device from interlaced scanning to non-interlaced scanning can be realized at low cost.

[0044]

As described above, according to the present invention, it is possible to reduce the image quality disturbance that impairs the smoothness of the motion due to the frame-completed scan conversion.

Further, when an interpolation frame is generated by a motion compensating operation for a motion such as horizontal pan, vertical pan, etc. in which the image quality disturbance is conspicuous, it can be realized by a simple signal processing, so that the cost of the device can be reduced. realizable.

[Brief description of drawings]

FIG. 1 is a principle diagram of frame completion scan conversion according to the present invention.

FIG. 2 is an overall block diagram of a first embodiment of the present invention.

FIG. 3 is an explanatory diagram of an embodiment of the scanning line rearrangement circuit.

FIG. 4 is a block diagram of an embodiment of this motion vector extraction circuit.

FIG. 5 is a block diagram of an embodiment of this motion vector extraction circuit.

FIG. 6 is a block diagram of an embodiment of this interpolation frame generation circuit.

FIG. 7 is a block diagram of an embodiment of a motion correction signal generation circuit of an interpolation frame generation circuit.

FIG. 8 is an overall block diagram of a second embodiment according to the present invention.

FIG. 9 is a block diagram of an embodiment of this motion mode determination circuit.

FIG. 10 is a block diagram of an embodiment of this interpolation frame generation circuit.

[Explanation of symbols]

1 ... Scan line rearrangement circuit, 2 ... Frame delay circuit, 3 ... Motion vector extraction circuit, 4 ... Interpolation frame generation circuit, 5 ...
Delay circuit, 6 ... Selection circuit, 7 ... Memory circuit, 8 ... Control circuit, 9, 10, 11 ... Reference block signal generation circuit, 12
... reference block signal generation circuit, 13 ... coincidence determination circuit.

Claims (2)

[Claims] 1. A means for generating a signal sequence of a reproduction frame by a rearrangement operation of a video signal of interlaced scanning, a means for detecting a motion vector from a signal sequence of a plurality of the reproduction frames, and a motion compensation operation by the motion vector. And a means for generating a signal sequence of an interpolation frame from the reproduction frame, wherein a video signal of non-interlaced scanning is constituted by the signal sequence of the reproduction frame and the interpolation frame. .. 2. The interpolation frame signal according to claim 1, further comprising means for detecting movements of upper and lower pans and horizontal pans based on the motion vector, and at least for the movements of the upper and lower pans and horizontal pans. Scan conversion device using series.