JPH05251711A - Semiconductor integrated circuit and its manufacture - Google Patents

Abstract

PURPOSE:To contrive to reduce a cell area by mounting a floating gate, control gate and select gate into a longitudinal arrangement. CONSTITUTION:A protruding part is formed on the silicon surface of a semiconductor integrated circuit (memory cell) ad a floating gate 24a, control gate 30 and select gate 29 are formed into a longitudinal arrangement on the side face of the protruding part 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and particularly to an electrically rewritable nonvolatile memory cell (EEPROM: Electrically Erasable).
The present invention relates to a structure of an Able Programmable ROM) and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, there were the following. An example of such a conventional memory cell of this type is shown in FIG. FIG. 4 (a) is a plan view of this memory cell, and FIG. 4 (b) is A of FIG. 4 (a).
It is a sectional view taken along line A-.

A conventional manufacturing method for the case of using an N-channel MOS transistor will be described below. First,
After a thick oxide film 13 for element isolation is formed on the P-type silicon substrate 1 by a normal element isolation method, a relatively thin oxide film (about 50 to 120Å) 3 is formed on the surface of the silicon substrate in the active region. ..

Next, the polycrystalline silicon 5 is deposited by the CVD method and N-type impurities are diffused so as to have conductivity, and then processed into a desired shape by a usual photolithographic etching technique. Next, the oxide film 7 is formed on the surface of the polycrystalline silicon 5 by the thermal oxidation method. At this time, the oxide film 4 is simultaneously formed on the exposed surface of the silicon substrate. Next, polycrystalline silicon is deposited on the entire surface to make it conductive, and then processed by a photolithographic etching technique to form a control gate 8 and a select gate 6.

Next, N-type impurities are implanted by an ion implantation method, and heat treatment is performed to activate them to form a diffusion layer 2 having conductivity opposite to that of the Si substrate. By the heat treatment at this time, the oxide film 9 is formed on the surface of the silicon substrate. Next, the insulating film 10 is formed by the CVD method, the contact hole 11 is opened by photolitho etching, and then aluminum is deposited and processed by the sputtering method to form the extraction electrode 12. The memory cell formed through the above steps functions as follows. The polycrystalline silicon 5 that is in contact with the P-type silicon substrate 1 through the thin oxide film 3 functions as a floating electrode (floating gate),
It is capacitively coupled to the upper control gate 8 through the oxide film 7. High voltage on this control gate 8,
For example, when about 14 V is applied and a voltage is applied between the diffusion layers located on both sides of the floating gate 5, among the electrons generated in the channel portion under the floating gate 5, the one with high energy is the control gate. It is attracted to the limit of 8 and partly passes through the oxide film 3 and is accumulated in the floating gate 5.

Further, the charge is extracted from the floating gate 5 by Fowler-Nordheim tunneling by applying a positive high voltage, for example, about 17 V to the diffusion layer 2. Further, the select gate 6 has a function of selecting one of the memory cells having a two-layer polysilicon structure, and at the same time, by applying 0 V to this gate, the floating gate is accumulated between the source and drain of the memory cell. Regardless of the state of the applied charge, it has the function of making it non-conductive.

[0007]

However, in the above memory cell structure, the control gate and the select gate are formed in the same plane. Therefore, the lateral dimension is the size of the contact hole and the control gate. The length (gate length), the length of the select gate (gate length), and the sum of the overlapping margin between them are determined, and there is a drawback that further reduction is difficult.

In order to eliminate the above-mentioned drawback that the cell area cannot be reduced, the present invention provides a high-density semiconductor integrated circuit in which floating gates, control gates, and select gates are vertically arranged, and a method for manufacturing the same. The purpose is to provide.

[0009]

In order to achieve the above object, the present invention provides a semiconductor integrated circuit in which a diffusion layer formed on a protrusion of a silicon substrate and one side surface of the diffusion layer in the vertical direction. A floating gate formed via a first oxide film, and a control gate and a select gate formed vertically on a side surface of the floating gate and the other side surface of the diffusion layer via a second oxide film, respectively. And a diffusion layer formed below the control gate and the select gate, respectively.

In the method of manufacturing a semiconductor integrated circuit, a step of etching a silicon substrate to form a protrusion, a step of oxidizing the surface of the silicon substrate, and a step of forming a conductive first polycrystalline silicon film are performed. Forming process,
A step of etching the polycrystalline silicon film by anisotropic dry etching to leave the polycrystalline silicon on both side surfaces of the protruding portion and removing the other portions, and a step of removing the remaining polycrystalline silicon film on both side surfaces of the protruding portion. Etching one polycrystalline silicon of the attached polycrystalline silicon; oxidizing the polycrystalline silicon surface and the silicon substrate surface; depositing a second polycrystalline silicon; A step of removing the polycrystalline silicon by a photolithography etching step while leaving both side surfaces of the protrusions is performed in order.

[0011]

According to the present invention, the control gate and the select gate, which are conventionally formed on the same plane, are formed with the protrusion on the silicon substrate surface, and the diffusion layer is provided on the protrusion.
Since the control gates and select gates are formed on the side surfaces of the protrusions, the area in the lateral direction only needs to be the thickness of the polysilicon that forms the control gates and select gates, and the area must be greatly reduced. You can

[0012]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a configuration diagram of a semiconductor integrated circuit (memory cell) showing an embodiment of the present invention, and FIG.
Is a plan view thereof, and FIG. 1B is a sectional view taken along line BB of FIG. In the figure, 20 is a P-type silicon substrate, 21 is a protrusion, and 23 is a first oxide film, which is formed between a gate electrode 32 and a floating gate (described later). 24a
Is a first layer of polycrystalline silicon (floating gate), and 26 is a second oxide film, which is formed between the floating gate 24a and a control gate (described later). Reference numeral 29 is a select gate formed of the second-layer polycrystalline silicon, 30 is a control gate similarly formed of the second-layer polycrystalline silicon, 31,
Reference numeral 33 is a diffusion layer, 34 is an oxide film as a protective film, 35 is a contact hole, and 36 is a metal wiring provided in the contact hole 35.

As described above, in the semiconductor device of the present invention, the floating gate 24a, the control gate 30, and the select gate 29 are formed on the side surface of the protrusion 21 formed in the silicon surface. Therefore, the floating gate 24a, which is in contact with the P-type silicon 20 via the first thin oxide film 23, is
It is capacitively coupled to the side control gate 30. When a high voltage, for example, about 14V is applied to the control gate 30 and a voltage is applied between the diffusion layers 32 and 33 located on both sides of the floating gate 24a, among the electrons generated in the channel portion under the floating gate 24a. Those having high energy are attracted to the limit of the control gate 30, and a part of the first oxide film 2
3 and is accumulated in the floating gate 24a. Further, the charge is extracted from the floating gate 24a by applying a high positive voltage to the diffusion layer 32, for example, 1
Fowler-Nordheim tunneling is performed by applying about 7V. Further, the select gate 29 has a function of selecting one of the memory cells of the two-layer polysilicon structure, and at the same time, 0 V is applied to this gate.
Is applied to the floating gate 24 between the diffusion layers (source / drain) 31 and 33 of the memory cell.
It can be brought into a non-conducting state regardless of the state of the charge accumulated in a.

Next, a manufacturing process of a semiconductor integrated circuit (memory cell) showing an embodiment of the present invention will be described with reference to FIGS. Here, the case of using a P-type silicon substrate is taken as an example, but the same applies to the case of using N-type silicon if the types of impurities are replaced by N and P. (1) First, as shown in FIG. 2A, a device isolation method (LOCO) that is usually performed on the surface of a P-type silicon substrate 20.
A thick oxide film region for element isolation is formed by the S method).
Next, a part of the surface of the silicon substrate 20 is covered with a photoresist, the remaining exposed silicon surface is etched by a dry etching method, and then the photoresist is removed, so that the P-type silicon substrate 20 has a side surface (silicon step) 22. The protrusion 21 is formed.

(2) Next, as shown in FIG.
By oxidizing in a dry oxygen atmosphere at 00 ° C. for about 15 minutes, a thin silicon oxide film 23 of about 85 Å is formed on the Si surface, and then about 4000 Å of polycrystalline silicon 24 is formed by the CVD method. This polycrystalline silicon has POC
The phosphorus is diffused by the l ₂ diffusion method to make it conductive. (3) Next, as shown in FIG. 2C, the silicon substrate 2
Anisotropic etching of the polycrystalline silicon 24 on the 0 surface, for example, using OAPM400B manufactured by Tokyo Ohka, RF power 90 W, etching gas C ₂ ClF ₆ 15 SCCM, S
The polycrystalline silicon 24 on the plane of the silicon substrate 20 is removed by performing etching for approximately 1.3 minutes at F ₆ 15SCCM and an etching pressure of 220 mTorr. When the etching is performed under this condition, the etching rate of the polycrystalline silicon 24 in the vertical direction is extremely higher than the etching rate in the horizontal direction, so that the polycrystalline silicon 24a formed on the side surface of the silicon step 22 remains unetched. Next, after applying a photoresist 25 on the silicon surface, the photoresist 25 is exposed and developed using a photomask such that the resist remains on only one side of the silicon step, and the polycrystalline silicon 24a remaining on the step is formed.
Expose one side of.

(4) Next, the exposed polycrystalline silicon 24a is removed by a normal dry etching method (isotropic etching), and then the photoresist 25 is removed, as shown in FIG. 2 (d). 95 in dry oxygen atmosphere
Oxidation is performed at a temperature of 0 ° C. for 40 minutes to form an oxide film 26 of about 280 Å on the silicon substrate 20. At this time, the polycrystalline silicon 24a is also oxidized at the same time, but since the oxidation rate of the polycrystalline silicon is higher than that of the single crystal silicon, a thick oxide film is formed. In the case of this embodiment, an oxide film of about 380 Å is formed. Here, the electric field applied to the oxide film 26 between the protrusion 21 of the silicon substrate 20 and the select gate 29 needs to be 6 MV / cm or less, and for that purpose, the oxide film 26 requires about 280 Å. .. In this respect, the second oxide film 26 is formed on the protrusion 21 of the silicon substrate 20.
And the thickness between the floating gate (polycrystalline silicon) 24a and the oxide film (about 85Å).

(5) Next, as shown in FIG. 3A, about 4000 Å of polycrystalline silicon 27 is formed on the surface of the silicon substrate 20 by the CVD method, and impurities are formed by thermal diffusion using POCl ₃ as a diffusion source. Is added to make it conductive. (6) Next, as shown in FIG. 3B, a photoresist layer 28 is formed by a normal photolithography technique. The photoresist layer 28 covers the side surface 22 of the protrusion 21 and allows the wiring pattern to be formed even on the thick oxide film 101 shown in FIG.

(7) Next, the second polycrystalline silicon 27 is etched under the same conditions as when the first polycrystalline silicon 24 was etched, and as shown in FIG. A gate) 29 and a wiring layer (control gate) 30 are formed. Then, an N-type impurity such as As is injected by about 1E16 / cm ² by an ion implantation method to obtain 950
Annealed in dry oxygen at ℃, diffusion layers 31, 32, 33
To form. It should be noted that the diffusion layer is the same as that shown in FIG.
In the step (d), the region of the diffusion layer is expanded from the diffusion layers 31, 32 and 33 by ion implantation with a mask,
For example, it may extend below the floating gate.

(8) Next, as shown in FIG.
The oxide film 34 is formed by the VD method. (9) Next, as shown in FIG. 1, an electrode lead-out contact hole 35 is formed in the oxide film 34, and a metal wiring 36 is formed therein. The floating gate,
The length of the control gate and the select gate can be appropriately increased by increasing the height of the silicon protrusion.

The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the present invention, and these modifications are not excluded from the scope of the present invention.

[0021]

As described above in detail, according to the present invention, the floating gate, the control gate and the select gate, which are conventionally formed on the same plane, are formed with the protrusions on the silicon surface and the protrusions are formed. Since the control gate and the select gate are formed on the side surface of the portion, the lateral area may be the thickness of the polysilicon forming the control gate and the select gate.
The area can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a semiconductor device showing an embodiment of the present invention.

FIG. 2 is a sectional view of the first half of a manufacturing process of a semiconductor device showing an embodiment of the present invention.

FIG. 3 is a cross-sectional view of the manufacturing process of the latter half of the semiconductor device showing the embodiment of the present invention.

FIG. 4 is a configuration diagram of a conventional semiconductor device.

[Explanation of symbols]

 20 P-type silicon substrate 21 Projection 22 Side of projection 23, 26, 34 Oxide film 24 Polycrystalline silicon (first polycrystalline silicon) 24a Polycrystalline silicon (floating gate) 25 Photoresist 27 Polycrystalline silicon (second (Polycrystalline silicon) 28 Photoresist layer 29 Wiring layer (select gate) 30 Wiring layer (control gate) 31, 32, 33 Diffusion layer 35 Contact hole for electrode extraction 36 Metal wiring

Claims (3)

[Claims] 1. A diffusion layer formed on a protrusion of a silicon substrate, and a floating gate formed on one side surface of the diffusion layer in a vertical direction via a first oxide film. (C) a control gate and a select gate which are vertically formed on the side surface of the floating gate and the other side surface of the diffusion layer via a second oxide film respectively, and (d) below the control gate and the select gate. A semiconductor integrated circuit, comprising: 2. A process of (a) etching a silicon substrate to form a protrusion, (b) a process of oxidizing the surface of the silicon substrate, and (c) a first polycrystalline silicon film having conductivity. And (d) etching the polycrystal silicon film by anisotropic dry etching to leave polycrystal silicon attached to both side surfaces of the protrusion and remove the rest. e) a step of etching away one polycrystal silicon of the polycrystal silicon attached to both side surfaces of the remaining protrusion, (f) a step of oxidizing the polycrystal silicon surface and the silicon substrate surface, ) A step of depositing the second polycrystalline silicon, and (h) a step of removing the second polycrystalline silicon by a photolithography etching step while leaving both side surface portions of the protrusion portion, are performed in order. Half Manufacturing method of conductor integrated circuit. 3. A method of manufacturing a semiconductor integrated circuit according to claim 2, wherein a floating gate is formed of the first polycrystalline silicon film and a control gate and a select gate are formed of the second polycrystalline silicon.