JPH05251450A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH05251450A JPH05251450A JP1734392A JP1734392A JPH05251450A JP H05251450 A JPH05251450 A JP H05251450A JP 1734392 A JP1734392 A JP 1734392A JP 1734392 A JP1734392 A JP 1734392A JP H05251450 A JPH05251450 A JP H05251450A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- integrated circuit
- semiconductor integrated
- brazing material
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体集積回路装置に関
し、特にピン状電極リードによりチップと外部との接続
を行う半導体集積回路装置のバンプ構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a bump structure of a semiconductor integrated circuit device for connecting a chip to the outside by means of pin-shaped electrode leads.
【0002】[0002]
【従来の技術】近年、半導体集積回路装置は高集積化に
ともない外部との接続にピン状電極リードによる接続が
使用されはじめている。(出願番号63−27978
9) 図4は従来のピン状電極リード接続用のバンプの構造の
断面図である。図4(a)では半導体素子を形成した半
導体集積回路チップ1上にバンプ2を例えば金で形成
し、バンプ上にI型のピン状電極リード3を立て例えば
金錫のような金属ろう材4でピン状電極リード3を固定
する。図4(b)ではピン状電極リード形状がネイルヘ
ッド型になっている。2. Description of the Related Art In recent years, as semiconductor integrated circuit devices have become highly integrated, pin-shaped electrode lead connections have begun to be used for external connection. (Application number 63-27978
9) FIG. 4 is a sectional view of the structure of a conventional bump for connecting a pin-shaped electrode lead. In FIG. 4A, bumps 2 are formed of, for example, gold on a semiconductor integrated circuit chip 1 on which a semiconductor element is formed, and I-shaped pin-shaped electrode leads 3 are erected on the bumps, for example, a metal brazing material 4 such as gold tin. The pin-shaped electrode lead 3 is fixed with. In FIG. 4B, the pin-shaped electrode lead shape is a nail head type.
【0003】[0003]
【発明が解決しようとする課題】この従来のバンプ構造
では図4(a)のようにI型のピン状電極リード3を用
いると金属ろう材の裾広がりが狭く、金属ろう材4とバ
ンプ2の接触面積が小さいため金属ろう材4とバンプ2
の接着強度が不十分である。また図4(b)のようにピ
ン状電極リード形状をネイルヘッド型にすれば金属ろう
材4の裾広がりが同じであっても金属ろう材とバンプ2
の接触面積が広くなり金属ろう材4とバンプ2の接着強
度を増すことができるが、バンプ2の面積が大きくなり
高集積化に不利になる。In this conventional bump structure, when the I-shaped pin-shaped electrode lead 3 is used as shown in FIG. 4 (a), the skirt spread of the metal brazing material is narrow, and the metal brazing material 4 and the bump 2 are formed. Since the contact area between the metal brazing material 4 and the bump 2 is small
Adhesive strength of is insufficient. If the pin-shaped electrode lead shape is a nail head type as shown in FIG.
Although the contact area becomes larger, the bonding strength between the metal brazing material 4 and the bump 2 can be increased, but the area of the bump 2 becomes large, which is disadvantageous for high integration.
【0004】本発明の目的は、バンプ面積を大きくする
ことなく、ピン状電極とバンプとの密着強度を増すこと
ができる半導体集積回路装置を提供することにある。An object of the present invention is to provide a semiconductor integrated circuit device capable of increasing the adhesion strength between a pin-shaped electrode and a bump without increasing the bump area.
【0005】[0005]
【課題を解決するための手段】本発明の半導体集積回路
装置は、半導体素子が形成された半導体チップの表面に
バンプが形成されこのバンプ上にピン状電極リードを固
定した半導体装置において、バンプ表面が凹凸に形成さ
れていることを特徴としている。The semiconductor integrated circuit device of the present invention is a semiconductor device in which bumps are formed on the surface of a semiconductor chip on which semiconductor elements are formed and pin-shaped electrode leads are fixed on the bumps. Is characterized by being formed in an uneven shape.
【0006】[0006]
【実施例】本発明について図面を参照して説明する。図
1は本発明の一実施例の断面図およびそのバンプの3つ
の例の上面図である。図1(a)に示すように、半導体
素子を形成した半導体集積回路チップ1上の金メッキ電
極である1000オングストロームのチタンタングステ
ン6及び1000オングストロームの金7上にバンプ2
を厚さ3μm大きさ100μm□で形成し選択エッチィ
ングを行いバンプ2上に凹部を形成する。表面に凹凸を
持つ本発明でのバンプ図1(b)2と従来技術で形成し
た表面が平坦なバンプ図4(a)2において、金属ろう
材4とバンプ2の接触面積を比較すると、それぞれ凹凸
部の側面も接触面積として観ることが出来るためバンプ
面積が小さくても同等の接触面積が得られる。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of one embodiment of the present invention and top views of three examples of bumps thereof. As shown in FIG. 1 (a), bumps 2 are formed on 1000 angstrom titanium tungsten 6 and 1000 angstrom gold 7 which are gold-plated electrodes on a semiconductor integrated circuit chip 1 on which a semiconductor element is formed.
Is formed with a thickness of 3 μm and a size of 100 μm □, and selective etching is performed to form a recess on the bump 2. The contact area between the metal brazing material 4 and the bump 2 is compared between the bump in the present invention having an uneven surface (b) 2 in the present invention and the bump formed in the prior art with a flat surface in FIG. 4 (a). Since the side surface of the uneven portion can be viewed as the contact area, the same contact area can be obtained even if the bump area is small.
【0007】そしてバンプ上にネイルヘッド型のピン状
電極リード3を立て金錫のような金属ろう材4でピン状
電極リード3を固定している。図1(b)〜(d)は図
1(a)でのバンプ2の上面図ではバンプ2上に形成す
る凹凸の例を示しているがこの限りではない。図1
(b)は□状の凹部を縦横に並べたもので、図1(c)
はスリット状の凹部を並べたもので、図1(d)は同心
円上に凹部を設けたものである。図1(b)中のBB1
間、図1(c)中のCC1 間、図1(d)中のDD1 間
の断面は全て断面図図1(a)のバンプ断面で表すこと
ができる。この実施例で図4(a)と同じだけの金属ろ
う材4とバンプ2の接触面積を得るためにはネイルヘッ
ド及びバンプ面積とも小さくすることができる。Then, a nail head type pin-shaped electrode lead 3 is erected on the bump, and the pin-shaped electrode lead 3 is fixed by a metal brazing material 4 such as gold tin. FIGS. 1B to 1D show an example of unevenness formed on the bump 2 in the top view of the bump 2 in FIG. 1A, but the present invention is not limited to this. Figure 1
(B) is a square-shaped recess arranged vertically and horizontally, as shown in FIG. 1 (c).
Is an array of slit-shaped recesses, and FIG. 1D shows a concentric recess. BB 1 in FIG. 1 (b)
The cross section between CC 1 in FIG. 1C and DD 1 in FIG. 1D can be represented by the bump cross section of FIG. 1A. In this embodiment, in order to obtain the same contact area between the metal brazing material 4 and the bump 2 as in FIG. 4A, both the nail head and the bump area can be reduced.
【0008】図2は本発明の他の実施例の製造工程を示
している。まず図2(a)に示すように、半導体集積回
路チップ1上全面にメッキ電極となる例えばチタンタン
グステン6を1000オングストローム及び金7を10
00オングストロームスパッタ法により被膜し、フォト
リソグラフィ技術によりメッキのパターニング100μ
m□を行い金メッキを3μm行いバンプ2を形成する。
さらに、図2(b)に示すように、もう1度フォトリソ
グラフィ技術によりメッキのパターニングを行った後金
メッキを行い表面が凹凸に形成されたバンプ3を形成す
る。次に図2(c)に示すように、フォトレジスト5を
剥離したのち全面をRIEなどでエッチングしチタンタ
ングステン6及び金7をエッチングする。次いで図2
(d)に示すように、金属ろう材4でバンプ上にピン状
電極リード3を固定する。 図3は第3の実施例で半導
体集積回路チップ1に予め凹部を設けその上にメッキを
行うことでバンプ2上に凹凸を形成している。予め設け
た凹部はスルーホールであってもよい。FIG. 2 shows a manufacturing process of another embodiment of the present invention. First, as shown in FIG. 2 (a), for example, titanium tungsten 6 of 1000 angstrom and gold 7 of 10 serving as a plating electrode are formed on the entire surface of the semiconductor integrated circuit chip 1.
Coating by 00 angstrom sputtering method, plating patterning 100μ by photolithography technology
Then, the bump 2 is formed by performing m □ and performing gold plating by 3 μm.
Further, as shown in FIG. 2B, the patterning of the plating is performed again by the photolithography technique, and then the gold plating is performed to form the bumps 3 having the uneven surface. Next, as shown in FIG. 2C, after removing the photoresist 5, the entire surface is etched by RIE or the like to etch titanium tungsten 6 and gold 7. Then Fig. 2
As shown in (d), the pin-shaped electrode lead 3 is fixed on the bump with the metal brazing material 4. FIG. 3 shows a third embodiment in which the semiconductor integrated circuit chip 1 is provided with a concave portion in advance and plating is performed on the concave portion to form irregularities on the bump 2. The previously provided recess may be a through hole.
【0009】[0009]
【発明の効果】以上説明したように本発明はバンプ面積
を大きくすることなくバンプ表面を凹凸に形成すること
でピン状電極リードを固定する金属ろう材とバンプとの
接触面積を拡大し密着強度を向上するという効果を有す
る。As described above, according to the present invention, the bump surface is formed in a concavo-convex shape without increasing the bump area, so that the contact area between the metal brazing material for fixing the pin-shaped electrode lead and the bump is increased to improve the adhesion strength. Has the effect of improving.
【図1】本発明の一実施例の断面図およびそのバンプの
断面図に相当する3例の上面図である。FIG. 1 is a cross-sectional view of an embodiment of the present invention and top views of three examples corresponding to the cross-sectional view of a bump thereof.
【図2】本発明の他の実施例およびその製造方法を説明
するために工程順に示した半導体集積回路チップの断面
図である。FIG. 2 is a cross-sectional view of a semiconductor integrated circuit chip shown in the order of steps for explaining another embodiment of the present invention and a manufacturing method thereof.
【図3】本発明の第3の実施例の断面図である。FIG. 3 is a sectional view of a third embodiment of the present invention.
【図4】従来の半導体集積回路チップの2つの例の断面
図である。FIG. 4 is a cross-sectional view of two examples of conventional semiconductor integrated circuit chips.
1 半導体集積回路チップ 2 バンプ 3 ピン状電極リード 4 金属ろう材 5 フォトレジスト 6 チタンタングステン 7 金 DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit chip 2 Bumps 3 Pin-shaped electrode leads 4 Metal brazing material 5 Photoresist 6 Titanium tungsten 7 Gold
Claims (1)
表面にバンプが形成されこのバンプ上にピン状電極リー
ドを固定した半導体集積回路装置において、バンプ表面
が凹凸に形成されていることを特徴とする半導体集積回
路装置。1. A semiconductor integrated circuit device in which bumps are formed on the surface of a semiconductor chip on which a semiconductor element is formed, and pin-shaped electrode leads are fixed on the bumps, wherein the bump surface is uneven. Integrated circuit device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1734392A JPH05251450A (en) | 1992-02-03 | 1992-02-03 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1734392A JPH05251450A (en) | 1992-02-03 | 1992-02-03 | Semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05251450A true JPH05251450A (en) | 1993-09-28 |
Family
ID=11941412
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1734392A Withdrawn JPH05251450A (en) | 1992-02-03 | 1992-02-03 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05251450A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11176858A (en) * | 1997-12-08 | 1999-07-02 | Rohm Co Ltd | Manufacture of semiconductor chip and continuity connection method for the semiconductor chip |
US6577001B2 (en) | 2000-04-19 | 2003-06-10 | Oki Electric Industry Co., Ltd. | Semiconductor device and the method for manufacturing the same |
JP2013012725A (en) * | 2011-05-31 | 2013-01-17 | Nitto Denko Corp | Wiring circuit board and method for manufacturing the same |
JP2020009902A (en) * | 2018-07-09 | 2020-01-16 | 日本特殊陶業株式会社 | Retainer |
-
1992
- 1992-02-03 JP JP1734392A patent/JPH05251450A/en not_active Withdrawn
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11176858A (en) * | 1997-12-08 | 1999-07-02 | Rohm Co Ltd | Manufacture of semiconductor chip and continuity connection method for the semiconductor chip |
US6577001B2 (en) | 2000-04-19 | 2003-06-10 | Oki Electric Industry Co., Ltd. | Semiconductor device and the method for manufacturing the same |
US6774027B2 (en) | 2000-04-19 | 2004-08-10 | Oki Electric Industry Co., Ltd. | Semiconductor device and method for manufacturing the same |
JP2013012725A (en) * | 2011-05-31 | 2013-01-17 | Nitto Denko Corp | Wiring circuit board and method for manufacturing the same |
JP2020009902A (en) * | 2018-07-09 | 2020-01-16 | 日本特殊陶業株式会社 | Retainer |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990518 |