JPH05243519A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To increase a capacity value of a stacked capacitor and, besides, to stabilize and improve a yield by preventing mutual short circuit of lower electrodes of adjacent stacked capacitors. CONSTITUTION:A first stacked capacitor composed of a first lower electrode 6, a first dielectric film 17 and a first upper electrode 9 and a second stacked capacitor composed of a second lower electrode 8, a second dielectric film 18 and a second upper electrode 10 are made to overlap each other on a field oxide film 2 through an interlayer insulation film 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a stacked capacitor.

[0002]

2. Description of the Related Art A capacitor is indispensable for a semiconductor memory device having a dynamic RAM, and requires a capacitance value above a certain level depending on the requirements of the circuit. MO of capacitor
When the capacitance insulating film (dielectric film) is constant, the S capacitance is proportional to the area of the portion that will be an electrode. Therefore, in order to secure a certain capacitance value, it is necessary to form an electrode having a certain area or more. Further, due to the reduction in cell size due to the miniaturization accompanying the recent trend of higher integration of semiconductor devices, the capacitor portion occupying most of the cell area has been devised. Then, starting from the conventional planar type capacitor, in recent years, a trench capacitor in which a groove is formed in a substrate and a capacitor is formed in the groove to increase an electrode area has appeared. However, the trench capacitor has a problem that a crystal defect is generated on the surface of the semiconductor substrate because a trench is formed in the semiconductor substrate. For this reason, recently, a stacked capacitor is formed in which a polycrystalline silicon film forming a capacitor electrode is deposited on a gate wiring that becomes a word line via an interlayer insulating film and the upper portion of a transfer gate is used to secure a necessary electrode area. The structure is common.

FIG. 7 shows a conventional semiconductor memory device having a stacked capacitor structure. Transfer gate transistors of the respective memory cells are formed on the left and right sides of the P-type semiconductor substrate 1 with the field oxide film 2 interposed therebetween, and the stacked capacitors coupled to the respective transistors extend on the transistors and the field oxide film. ing. A transistor is a pair of N that serves as a source and a drain.
^The capacitor has a ⁺ type diffusion layer 4 and a gate electrode wiring 4, and the capacitor is a lower electrode 2 formed of a polycrystalline silicon film and connected to one N ⁺ type diffusion layer 4 by a capacitance contact portion 24.
6, a dielectric film 27 formed thereon, and an upper electrode, which is formed of a polycrystalline silicon film formed thereon and is common to each memory cell, form a MOS capacitor. Further, the first insulating oxide film 5 covers the gate electrode wiring 4, the second insulating oxide film 7 covers the stacked capacitor, and the BPSG is formed on the stacked insulating film.
A contact hole 15 for covering the digit line with the other N ⁺ type diffusion layer 4 is formed by covering with the film 12.

[0004]

In such a conventional semiconductor memory device, the size of the memory cell is reduced due to the miniaturization, so that the space between adjacent cells is narrowed and it becomes difficult to obtain a necessary area. ing. The method of increasing the surface area of the electrode is as follows in the conventional stacked capacitor structure.
The thickness of the lower electrode is only increased to increase the side wall area. However, this method has a problem that a deep groove is formed between the lower electrodes of the adjacent memory cells. Further, since the area of the electrodes is increased by increasing the planar area as much as possible, there is a problem that the yield is reduced due to a short circuit between adjacent lower electrodes.

[0005]

A feature of the present invention is that it is formed between first and second transfer gate transistors formed on a semiconductor substrate and the first and second transfer gate transistors. A field insulating film, a first stacked capacitor coupled to the first transfer gate transistor and extending on the field insulating film, and a second stacked capacitor coupled to the second transfer gate transistor, on the field insulating film. And a semiconductor memory device having the first stacked capacitor and a second stacked capacitor that overlaps and extends via an interlayer insulating film.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. Figure 1
FIG. 4 is a sectional view showing an embodiment of the present invention. Transfer gate transistors of the respective memory cells are formed on the left and right sides of the P-type semiconductor substrate 1 with the field oxide film 2 interposed therebetween. Each transistor has a pair of N ⁺ type diffusion layers 4 serving as a source and a drain, and a gate electrode wiring 4 composed of a first-layer polycrystalline silicon layer formed on a channel region between the source and the drain with a gate insulating film interposed therebetween. have. Further, two gate electrode wirings (word lines) 4 of another memory cell extend on the field oxide film 2.
These gate electrode wirings are covered with a first insulating oxide film 5 which is an interlayer insulating film. A first lower electrode 6 made of a second-layer polycrystalline silicon layer is connected to one of the N ⁺ -type diffusion layers 4 of the transistor on the left side through a first capacitance contact portion 14, and the first lower electrode 6 is field-oxidized. From the top of the film to the gate electrode wiring of the transistor on the left
It is formed on the surface of the insulating oxide film 5. And the first
A first dielectric film 17 is deposited on the lower electrode 6 and a first upper electrode 9 made of a third-layer polycrystalline silicon layer is formed thereon.
The first lower electrode 6, the first dielectric film 17 and the first upper electrode 9 form the MOS capacitance of the first stacked capacitor. The first stacked capacitor is covered with a second insulating oxide film 7 which is an interlayer insulating film. On the other hand, the second lower electrode 8 made of the fourth-layer polycrystalline silicon layer is connected to one of the N ⁺ type diffusion layers 4 of the transistor on the right side through the second capacitance contact portion 13,
The second lower electrode 8 overlaps the first upper electrode 9 of the first stacked capacitor on the field oxide film through the second insulating oxide film 7 and then extends from there to the gate electrode wiring of the transistor on the right side to form a second electrode. It is formed on the surface of the insulating oxide film 7. Then, the second dielectric film 1 is formed on the second lower electrode 8.
8 is deposited on the second upper electrode 10 formed of a fifth layer of polycrystalline silicon layer.
Lower electrode 8, second dielectric film 18 and second upper electrode 10
Constitutes the MOS capacitance of the second stacked capacitor. The second upper electrode 10 is connected to the first upper electrode 9 through the upper electrode connecting contact hole 16 formed in the second insulating oxide film 7 to form an upper electrode common to all memory cells. A CVD oxide film 11 and a BPSG film 12, which are interlayer insulating films, are covered thereover, and a contact hole 15 for connecting the digit line to the other N ⁺ type diffusion layer 4 is formed therein.

Next, an example of a method for obtaining the structure of FIG. 1 will be described in the order of steps with reference to the sectional views of FIGS.

A first gate oxide film is formed on the P-type semiconductor substrate 1 on which the field oxide film 2 and the N ⁺ type diffusion layer 3 are formed.
The gate electrode wiring 4 is formed of the polycrystalline silicon layer of the second layer, and the first insulating oxide film 5 serving as an interlayer insulating film is further formed by CVD.
Method (Chemical Vapor Deposition
ion) method to deposit a film having a thickness of 200 nm (nanometer), and the first capacitance contact hole 14 is formed by photolithography and dry etching (FIG. 2). Then, a second-layer polycrystalline silicon layer having a thickness of 200 nm is deposited on the entire surface, and thermal diffusion of phosphorus is performed to reduce the resistance value. Then, the first lower electrode 6 is formed by photolithography technique and dry etching technique. Patterning is performed (FIG. 3). Next, a silicon nitride film or a composite film of a silicon nitride film and a silicon oxide film is grown over the entire surface to a film thickness of 10 nm, and a third polycrystalline silicon layer is deposited thereon to a film thickness of 100 nm, and a phosphorus film is formed. After reducing the resistance value by performing heat diffusion of
By photolithography and dry etching techniques, the first dielectric film 17, which is the capacitor insulating film of the capacitor, is patterned and formed from the silicon nitride film or the composite film of the silicon nitride film and the silicon oxide film, and the third-layer polycrystalline film is formed. The first upper electrode 9 is patterned and formed from the silicon layer to form a first stacked capacitor (FIG. 4). Next, a second insulating oxide film 7 serving as an interlayer insulating film between the second stacked capacitor and the second stacked capacitor is formed to a film thickness of 200 nm by the CVD method.
Then, the second capacitor contact hole 13 is formed in the first and second insulating oxide films 5 and 7 (FIG. 5). Next, after forming the contact hole 16 for connecting the upper electrode in the second insulating oxide film 7, a polycrystalline silicon layer of the fourth layer is deposited on the entire surface to a film thickness of 200 nm, and thermal diffusion of phosphorus is carried out to make resistance value After lowering, the second lower electrode 8 is patterned and formed by the photolithography technique and the dry etching technique. After that, a silicon nitride film or a composite film of a silicon nitride film and a silicon oxide film is grown to a thickness of 10 nm on the entire surface, and a fifth-layer polycrystalline silicon layer is formed on top of
After being deposited to a film thickness of 0 nm and reducing the resistance value by performing thermal diffusion of phosphorus, the capacitance insulation of the capacitor from the silicon nitride film or the composite film of the silicon nitride film and the silicon oxide film is performed by the photolithography technique and the dry etching technique. The second dielectric film 18, which is a film, is formed by patterning,
A second stacked electrode is formed by patterning the second upper electrode 10 from the polycrystalline silicon layer of the second layer (FIG. 6). Next, a CVD oxide film 11 and a BPSG film 12 which are interlayer insulating films are deposited and heat-treated (reflow), and then a contact hole 15 for connecting a digit line to the other N ⁺ type diffusion layer 4 is formed therein. The semiconductor memory device shown in FIG.

[0009]

As described above, according to the present invention, when the stacked capacitors of the adjacent memory cells are superposed on the field insulating film via the interlayer insulating film, the same cell size and the same electrode film thickness are used. The electrode area can be increased by about 1.4 times as compared with the conventional technique, and as a result, a large capacitance value can be secured. In addition, since the stacked capacitors of the adjacent memory cells overlap each other on the field insulating film via the interlayer insulating film, there is no risk that the lower electrodes of the adjacent stacked capacitors are short-circuited and the yield is stable. Have.

[Brief description of drawings]

FIG. 1 is a sectional view showing a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a process of manufacturing the semiconductor memory device of FIG.

FIG. 3 is a cross-sectional view showing a process of manufacturing the semiconductor memory device of FIG.

FIG. 4 is a cross-sectional view showing a process of manufacturing the semiconductor memory device of FIG.

FIG. 5 is a cross-sectional view showing a process of manufacturing the semiconductor memory device of FIG.

FIG. 6 is a cross-sectional view showing a process of manufacturing the semiconductor memory device of FIG.

FIG. 7 is a cross-sectional view showing a process of manufacturing a conventional semiconductor memory device.

[Explanation of symbols]

1 semiconductor substrate 2 field oxide film 3 N ⁺ type diffusion layer 4 gate electrode wiring 5 first insulating oxide film 6 first lower electrode 7 second insulating oxide film 8 second lower electrode 9 first upper electrode 10 second upper electrode 11 CVD oxide film 12 BPSG film 13 Second capacitance contact hole 14 First capacitance contact hole 15 Contact hole for connecting digit line 16 Upper electrode connection contact hole 17 First dielectric film 18 Second dielectric film 24 Capacitance contact hole 26 Lower electrode 27 Dielectric film 29 Upper electrode

Claims (1)

[Claims] 1. A first and a second formed on a semiconductor substrate.
Transfer gate transistor, a field insulating film formed between the first and second transfer gate transistors, and a first insulating film which is coupled to the first transfer gate transistor and extends on the field insulating film. A second stacked gate coupled to the first stacked capacitor and the second transfer gate transistor and extending on the field insulating film so as to overlap with the first stacked capacitor via an interlayer insulating film. A semiconductor memory device having a capacitor.