JPH05241677A - Method for controlling power consumption for computer and system thereof - Google Patents

Abstract

PURPOSE:To reduce the power consumption of computers by controlling the clock frequency thereby operating integrated circuits of microprocessors. CONSTITUTION:The calculation speed of the computer system or the number of executing instructions per second is directly related to the frequency of the clock pulse supplied to a microprocessor 13 by means of a clock signal generation circuit 15. By varying the clock frequency of the clock signal generation circuit 15, the speed of calculation or logical operation is reduced during the low-capacity calculation or the logical capacity period so as to reduce the voltage consumption.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a personal computer, and more particularly to managing the battery power available in a portable computer by changing the clock frequency of the operation of the central processing unit of the computer. ..

[0002]

2. Description of the Related Art A conventional personal computer of a type generally called AT type (Advanced Technology) is 80
X86 series integrated circuits (commercially available from Intel Corp.)
ry Standard Architecture-industry standard architecture)
Or operates on EISA (extended ISA) bus. Current personal computers operate on battery power and are greatly reduced in size and weight for convenience of portability.

[0003]

However, due to the increasing speed and complexity of personal computers and the reduction in size and weight, the need for more effective management of available battery power has become a real personal computer. Then it is the highest priority issue.

The present invention has been made under the above circumstances, and an object of the present invention is to provide a method and system capable of reducing power consumption in a computer.

[0005]

In order to achieve the above object, the invention according to claim 1 controls a computer system on the basis of supplied data and instructions, and changes in interval between consecutive clock pulses. A method comprising a microprocessor performing logical operations based on supplied data and instructions in synchronization with applied periodic clock pulses, which need to settle within tolerance limits specified for For controlling the logical operation of the clock pulse according to the supplied clock pulse at a frequency of, and changing the frequency of the clock pulse supplied to the microprocessor for continuous cycle intervals. The sequence of the delivered pulses separated by an interval within the specified tolerance limit. From said one frequency among the cycle is characterized in that it comprises changing to a different frequency.

According to a second aspect of the present invention, during the period of the clock pulse supplied to the microprocessor within the range in which the allowable range of fluctuation is specified by the microprocessor for the interval between consecutive clock pulses. The power consumption in the computer system is reduced by continuously increasing the interval.

The invention according to claim 3 is characterized in that the frequency of the clock pulse supplied to the microprocessor is reduced so as to reduce the power consumption in accordance with the reduction of the requirement in calculation or logical capacity. To do.

According to a fourth aspect of the present invention, the frequency of the clock pulse supplied to the microprocessor is such that there is new data or instructions supplied to the computer system within a predetermined period from the last supplied data or instructions. It is characterized in that it is reduced in response to not doing.

A fifth aspect for achieving the above object.
The described invention performs logical operations based on data and instructions supplied in synchronization with applied periodic clock pulses that need to be stable within specified tolerance limits for variations in the spacing between consecutive clock pulses. A computer system including a microprocessor for executing, a clock pulse source connected to supply to the microprocessor periodic clock pulses having variable spacing between successive clock pulses, and the source. The microprocessor is responsive to the supplied clock pulse by changing the interval of successive clock pulses within a range in which the allowable range of variation is specified for the interval between successive clock pulses. The frequency at which the logical operation of the supplied data and instructions will continue to be performed. It is characterized in that it comprises the further.

According to a sixth aspect of the present invention, there is provided battery-operated power supply means that is operably connected to the microprocessor and that continues the logical operation with respect to the supplied data and instructions. Means increase the interval between successive clock pulses to reduce the frequency of the microprocessor's logical operations on the supplied data and instructions to reduce power consumption from the battery powered power supply means. It is characterized by.

According to a seventh aspect of the present invention, the means is a continuous clock in response to the absence of new data or instructions supplied to the computer system within a predetermined period of time since the last supplied data or instructions. It is characterized by increasing the spacing between the pulses.

[0012]

The present invention controls the clock frequency at which an integrated circuit of a microprocessor operates to reduce power consumption during slow computing power. That is, reducing the clock frequency to a lower operating frequency, for example during communications by modem, waiting for new commands to be entered, and other routine and simple computational functions.
It is also increased to the maximum operating frequency when more complex calculations are required, such as forming a representation of a rotating three-dimensional object, performing a large database search, etc. Since the number of instructions executed by the microprocessor per unit time increases as the clock frequency increases, the power consumption also increases according to the clock frequency. In addition, heat losses in microprocessor integrated circuits also tend to increase with clock frequency, resulting in increased operating temperature and increased likelihood of failure, with attendant mean time to failure (MTBF). Ratings are also reduced.

A clock frequency generator circuit is connected to the microprocessor to provide a clock signal to the clock signal,
In order to reduce or increase the clock frequency of the microprocessor according to the calculation condition, the clock frequency can be continuously changed within the range of stability of the clock signal supplied to the microprocessor. This ensures proper operation of the microprocessor while continuously changing the clock frequency of the microprocessor between its upper and lower limits. Changing the frequency of the clock signal supplied to the microprocessor in this mode eliminates the need to reset the microprocessor for operation at a particular new clock frequency, and provides continuous power depending on the computational requirements. Provides management control.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, a schematic block diagram of a typical personal computer or workstation having a central processing unit 12 including a commercial microprocessor 13 such as an 80486 integrated circuit (commercially available from Intel Corp.) is shown. It is shown. The central processing unit 12 may be controlled by a user via a keyboard or mouse or pen tablet or the like input device 16, and may further provide a graphic or character image 34 or a combination thereof in a known manner. A display device 14 is included. The central processing unit 12 may also operate on input from the network 32 and data 20 may be stored in memory 18 (and mass storage device 30) for access and interaction by the central processing unit 12 in various computational routines. sell. Central processing unit 12
And all associated peripherals can be powered from the battery 33.

The speed of computational operations or the number of instruction executions per second of the computer system of FIG. 1 is directly related to the frequency of the clock pulses supplied by the clock signal generation circuit 15 to the microprocessor 13. 80486 Commercially available microprocessors such as integrated circuits generally require a specified clock frequency within a narrow range.
Thus, such microprocessors may require clock frequencies in the range of, for example, 16 to 33 MHz, for example short term stability within 0.1% variation between clock pulses.

Short-term stability of the clock pulse is generally important, for example, to ensure that the internal phase locked loop integrated in the microprocessor circuit is locked onto the stable clock pulse. The number of instructions executed per unit time is high and the microprocessor 13 has a high clock frequency.
Since this increases, the heat loss inside the microprocessor 13 also increases, which raises the operating temperature and consumes the available battery 33 power more rapidly. Therefore, it is desirable to reduce the frequency of the clock pulses supplied to the microprocessor 13 when possible to reduce power consumption and operating temperature and extend battery life. However, because the clock signal must be stable within the specified range, it is desirable to change the clock frequency with an increase or decrease that is sufficiently smaller than the short-term conditions of clock pulse delivery are fully met.

This allows the microprocessor 13 to continue operating within specifications and does not have to be completely reset at the new fixed clock frequency. Also,
The clock frequency is, for example, a low clock frequency for low power consumption in the word processing program 24, and a high clock frequency for high calculation requirements such as forming a total natural color display 34 of a rotating three-dimensional image. , Can be selected according to the calculation conditions.

In one preferred embodiment of the present invention, the variable frequency generator circuit provides clock pulses to the microprocessor at a frequency that is continuously variable between upper and lower limits. Changes in the clock frequency do not exceed the stability requirements of the consecutive clock pulses required to ensure the proper operation of the microprocessor.
Thus, for example, clock pulse stability specifications for microprocessors in which the variation between successive pulses must not exceed 0.1% at a clock frequency of 30 MHz is specified by a decrease in clock frequency of 33 picoseconds or approximately in clock pulse intervals. It is required not to produce fluctuations (increases) above 29.97 MHz. After this, the clock frequency is 29.94003 MH within the range of 0.1%.
It can be changed (decreased) to z, and so on, until it reaches the desired new, lower, clock frequency. By varying the frequency of the clock pulses supplied to the microprocessor by this method within the stability requirements of the specification, either a phase-locked loop or any other frequency sensitive circuit embedded in the microprocessor chip can be used. The behavior will be unchanged or unaffected.

Referring to FIG. 2, the clock generation circuit 15
A schematic block diagram of the
The clock frequency is changed over a wide range from Hz to about 45 MHz, and the current flow rate is also changed from 1 A to 1.8 A with a supply amount of 5 V, respectively, while being small enough to satisfy the stability specifications. A clock pulse is supplied to the microprocessor 13 of the central processing unit 12 at a frequency change rate that can change with an increasing or decreasing amount.

That is, in the circuit shown in FIG. 2, the clock frequency designated by the user is input in parallel or in series.
"Immediately" depending on the digital signal supplied to 1,43
Alternatively, it is generated at the output 61 which can be continuously changed. This circuit is commercially available, such as the Model AV9101 integrated circuit manufactured by AVASEM Corporation in San Jose, California. Briefly, the circuit includes a phase locked loop including a phase detection circuit 45 for the reference signal input 51 and the variable signal input 53 and divider circuits 47,49. This commercially available circuit supplies an error signal from the phase detection circuit 45 to the control input of a variable voltage controlled oscillation circuit (VCO) 57 which is supplied to the phase detection circuit 45 via a frequency divider circuit 49, for example. An external connection via an amplifier circuit (or a filtering circuit) 55 is required for this purpose. The VCO output divided here is output divider circuit 5.
It is selectively divided by 9. Divider circuits 47, 49,
59 is a latch circuit 6 according to a control signal supplied through either the parallel input port 41 or the serial input port 43.
3 and multiplexer 65 to selectively generate the desired output clock frequency.

The control logic circuit 67 outputs the control signal essential for setting the frequency divider circuit according to the control signal applied so as to instruct the output 61 to change the frequency within 0.1% of the previous frequency. provide. Therefore, the output clock signal 61 is also proportional to the input frequency or by selectively setting the divider circuits 47 and 49 based on the source signals for a number of numerator and denominator taking a good ratio, and also the VCO.
It is determined by an output frequency dividing circuit 59 that performs an operation on the output obtained from 57. Of course, the clock pulse can be supplied to the microprocessor at a stable rate within the specified tolerance for fluctuation, and the clock pulse is supplied only by continuously changing each within the tolerance or fluctuation of the specification. Other clock pulse sources may be used, such that the frequency may be continuously varied.

Accordingly, the system and method of the present invention alters the frequency of the clock pulses supplied to the microprocessor so that it is inactive during periods of low power computational or logical capacity (eg, not active for a timeout period). Provides a convenient technique for limiting the power consumption so as to reduce the speed of computations or logical operations. Specifies the stability of consecutive clock intervals when sophisticated calculations or logical operations are required (for example, when manually launched from the keyboard or when an application program that requires advanced or fast computing power is detected). The clock frequency can be increased as a continuous increase that is within the allowed limits set.

[0023]

As described above, according to the present invention, with the above configuration, the clock frequency at which the integrated circuit of the microprocessor operates can be controlled, so that the power consumption in the computer can be reduced. It is possible to provide a method and system capable of performing the above.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a computer system equipped with a microprocessor according to an embodiment of the present invention.

2 is a block diagram of a circuit for generating a variable clock frequency that feeds the microprocessor of the computer system of FIG.

[Explanation of symbols]

 12 Central Processing Unit 13 Microprocessor 14 Display Device 16 Input Device 18 Memory 20 Data 30 Mass Storage Device 32 Network 33 Battery 41 Parallel Input Port 43 Serial Input Port 45 Phase Detection Circuit 47, 49, 59 Dividing Circuit 51 Reference Signal Input 53 Variable signal input 55 Amplifier circuit (filtering circuit) 57 Voltage controlled oscillator circuit (VCO) 61 Output 63 Latch circuit 65 Multiplexer

Claims (7)

[Claims] 1. An applied periodic clock pulse which controls a computer system based on supplied data and instructions and which must be stable within specified tolerance limits for variations in the spacing between successive clock pulses. A method including a microprocessor for performing a logical operation based on data and instructions supplied in synchronism with a clock pulse supplied to the microprocessor at one frequency, the clock pulse being supplied in response to the supplied clock pulse. Controlling the logical operation of the supplied pulses, the frequency of the clock pulses supplied to the microprocessor being separated by an interval within the specified tolerance for fluctuations in successive periodic intervals. It is possible to change to a frequency different from the above one frequency during consecutive cycles. Wherein the Mukoto. 2. The interval between the periods of the clock pulses supplied to the microprocessor is continuously increased within a range in which an allowable range of fluctuation is specified for the interval between consecutive clock pulses. The method of claim 1, further comprising: reducing power consumption in the computer system. 3. The frequency of the clock pulse provided to the microprocessor is reduced to reduce power consumption in response to a reduction in computational or logical requirements. Method. 4. The frequency of the clock pulse supplied to the microprocessor is responsive to the absence of new data or instructions supplied to the computer system within a predetermined period of time since the last supplied data or instruction. The method of claim 3, wherein the method is reduced. 5. A logical operation based on data and instructions supplied in synchronism with an applied periodic clock pulse that needs to settle within specified tolerance limits for variations in the spacing between successive clock pulses. A computer system including a microprocessor for executing, the clock pulse source connected to supply to the microprocessor periodic clock pulses having variable spacing between successive clock pulses, said source The microprocessor is responsive to the supplied clock pulse by changing the interval of successive clock pulses within a range in which the allowable range of variation is specified for the interval between successive clock pulses. The frequency at which the logical operation of the supplied data and instructions will continue to be performed. Additional computer system characterized in that it comprises. 6. A battery powered power supply means operably connected to said microprocessor for continuing logical operations on supplied data and instructions, said means for modifying said battery powered power supply. 6. The interval between successive clock pulses is increased to reduce the frequency of the microprocessor's logical operations on the supplied data and instructions to reduce power consumption from the means. The described computer system. 7. The means provides an interval between consecutive clock pulses in response to the absence of new data or instructions supplied to the computer system within a predetermined period of time since the last supplied data or instructions. The computer system according to claim 6, wherein the computer system is increased.