JPH05235934A - Device for connecting data communication equipment to digital communication network - Google Patents

Abstract

PURPOSE: To connect data terminal equipment to an ISDN digital communciation network, having 1st 64Kbps and 2nd 64Kbps digital communication B channels with various levels of transmission delay. CONSTITUTION: This device has a reception part, provided with a storage means 580 for storing data received from the digital network, a means 510 for measuring the difference between two levels of transmission delay, an address designating means 570 for designating the address of the storage means 580, in order to extract the data received by two digital channels and control means 540 and 550 for controlling the address designating means, in response to the measured value in order to apply the high-speed data flow of 128Kbps not to be affected by the difference of transmission delay which is led in by both the digital channels on the one hand and this device has a transmission part on the other hand.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to communication systems, and more particularly to a device for connecting communication devices to a digital communication network having at least first and second digital communication channels with different communication delays.

[0002]

BACKGROUND OF THE INVENTION Digital networks, or more precisely, integrated services digital networks (I
The concept of a leased line switching network such as SDN) began in the early 1960s with the digitization process of telephone networks in various countries, and has replaced the previous analog technology.

The CCITT (International Telegraph and Telephone Advisory Committee) recommendations give not only principles and guidelines for ISDN concepts and standards, but also detailed specifications of its user networks and inter-network interfaces.

CCITT Recommendation I. 430 defines layer 1 characteristics of the user network interface applied at the S or T reference points of the basic interface structure. IS
DN basic access is divided into three different sub-channels by the time division multiplexing mechanism: two so-called B channels and one D channel, 144 Kb /
It has a second (Kbps) transmission channel. Each channel of the B channel is a digital telephone network (pulse code modulation (PCM) is implemented by the subscriber unit) or 64 Kb
6 independent with bit timing and 8-bit byte timing that can be used for ps data communication
It is a 4 Kbps dual carrier channel. The D channel is a 16 Kbps channel that allows dynamic multiplexing of the following information: That is, signaling information about the B channel, information about low speed remote services, and information using low speed packet switched services (up to 9600 bps and 16 bps).

The 64 Kbps B channel is used for a wide range of data communication applications. 24, V.I.
35, X. Although sufficient for applications including the usual data terminal equipment interfaces described in No. 21, etc., higher transmission rates may be desirable over one ISDN network. In some cases, for example, in multimedia applications where data, voice and video are transmitted simultaneously, the user may desire a 128 Kbps channel, for example.

Known ISDN devices operate at a total of 124 Kbp because both B channels operate independently and asynchronously.
It is not possible to use both independent B channels to provide the s data communication channel. In fact, the position of one bit in a byte is maintained through the ISDN transmission network, but the transmission time of that byte in the network is significantly different on one B channel and the other, thereby synchronizing each other. Can be prevented.

It is an object of the present invention to provide a terminal adapter which allows both B channels to be used as the only fully synchronized 128 Kbps data communication channel.

[0008]

The above problem is solved by an apparatus for connecting a communication device to a digital communication network having at least first and second digital communication channels with different communication delays. The device comprises a transmission means having means for separating the only high speed data flow received from a data communication device and transmitted by a digital network into two different low speed data flows both transmitted by one of its digital channels. And storage means for storing data received from said digital network, means for measuring the difference between two transmission delays, and for providing data received by two digital channels Addressing means for addressing the storage means and controlling the addressing means in response to the measurement to provide a high speed data flow which is unaffected by the difference in transmission delays introduced by both digital channels. And a control unit for controlling the reception unit.

In a preferred embodiment of the invention, the device comprises:
Means for performing an initialization procedure to ensure to the data communication device that both the first and second digital channels are operational and thus a high speed data flow can be transmitted by both digital channels. including.

Preferably, the apparatus comprises a timing means for ensuring that the establishment of both said first and second digital channels is carried out within a predetermined period, and the other digital device within that period. Includes means for disconnecting an already established digital channel if the channel cannot be established. This advantage results in a quick disconnection of the device if the device is not allocated both digital channels by its digital network.

In a preferred embodiment of the invention, the device comprises:
If overflow of the storage means is detected, overflow detection means is included for disconnecting the digital channel connection so that possible data loss is dealt with immediately.

Preferably, the apparatus is 128K fully synchronized.
A terminal adapter for an ISDN network that enables the establishment of bps data communication, and further said 128 Kbps for providing a set of different digital channels with adaptive data transmission rates for simultaneous transmission of data, video and voice. Means for performing the time division multiplexing process of Therefore, the present invention is particularly suitable for multimedia applications.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A description will be given of FIGS. 1 to 4 (in FIG. 5, the connection relationships of FIGS. A receiver of an adapter according to the present invention is illustrated. The receiving unit is the data bus 104
And each common control lead wire READ 107, WRI
TE 105 and CHIP SELECT 109 allow IS such as INTEL iATC 29C53
It includes a microcontroller 100 such as an INTEL 80188 connected to a DN interface controller 900. The ISDN interface controller 900 is ISO 887 in the preferred embodiment of the present invention.
Data can be transmitted and received by the transformers 1001 and 1002 connected to the connector 1000 which is of the 7 type. The connector 1000 conforms to CCITT Recommendation I.S. 430
Connection to the reference point S0 according to INTEL
For more information on the iATC 29C53 Communication Controller document, see the reference "INTEL Microco.
controller Handbook ”, 1988, 5
-Page 76 (reference 231658-003). The controller 900 includes a set of three leads, namely a subscriber line data (SLD) link 901 carrying data transmitted on two B channels, a 512 kHz bit connected to the clock input of the demultiplexer circuit 300. It communicates with the demultiplexer circuit 300 by a subscriber clock (SCL) lead 903 that carries a clock and a subscriber direction (SDIR) lead 902 that indicates the direction of data flow on the SLD bus. The signals carried by these leads are described in detail in the documents mentioned above. SDI
R lead 902 carries the signal used to control demultiplexer circuit 300. The demultiplexer circuit 300 first extracts two B channels from the SLD lead wire 901. That is, B1 DA
TA IN lead wire 302 and B2 DATA IN
The data present on the data flow on SLD lead 901 is separated to give two different data flows of 64 Kbps each on the two sets of leads 301. The demultiplexer circuit 300 also includes the lead 3
B1 and B2 envelope signals are given to 04 and 303, respectively. B1 DATA IN lead wire 30
2 are connected to the input lead of the clock generator 320 and the input of the flag detector 400, respectively. Further, the clock generator circuit 320 receives the SCL clock on the lead wire 903 and supplies two types of clock signals. The byte clock signal from the lead wire 3210 is supplied to the clock input of the counter 540, the enable input of the deserializer 410 and the DMA1 CONT.
The bit clock signal transmitted to the clock input of the ROL circuit 570 and supplied to the lead wire 3211 is transferred to the AND gate 4
100 to the first input lead. Generation of the byte clock signal and the bit clock signal is easily performed using a group of frequency dividers known to those skilled in the art. The flag detector 400 first detects the occurrence of the SDLC start of frame flag and secondly to generate a control pulse on the lead 401 that is transmitted to the input lead of the control decoding circuit 510 when it occurs. , SDLC frame end flag occurrence detected, DMA1 CONTROL circuit 5
Used to generate a second control pulse on lead 402 which is transmitted to the 70 FLAG END (FE) lead. The concept of frame start and end flags is
It is known to those skilled in the art of serial data link control. The output lead wire 401 of the flag detector 400 is
It is used to synchronize the control decoding circuit 510 which receives the data flow present on the DATA IN B1 channel at its data input. The 3-bit decoding process immediately following the start flag is 6 depending on the value of those bits.
Results in the occurrence of a pulse occurring on one of the sets of output leads 511-516. More specifically, lead 511 carries a pulse when detector 510 detects the occurrence of pattern 000 immediately after the SDLC start flag. Lead 512 carries a pulse when detector 510 detects the occurrence of pattern 100 immediately after the SDLC start flag. As for the lead wire 513, the detector 510 is SD
The pulse is carried when the occurrence of the pattern 110 is detected immediately after the LC start flag. The lead wire 514 is connected to the detector 5
When 10 detects the occurrence of pattern 010 immediately after the SDLC start flag, it carries a pulse. Lead wire 515
Carries a pulse when detector 510 detects the occurrence of pattern 111 immediately after the SDLC start flag. Finally, lead 516 carries a pulse if detector 510 detects the occurrence of pattern 011 immediately after the SDLC start flag. Leads 511 to 514 are each connected to the four input leads of NOR gate 530, the output 531 of the NOR gate being used to generate an interrupt signal that is transmitted to the INT3 input of microcontroller 100. To be done. Leads 515 and 516 are each connected to two input leads of NOR gate 520, the output of which is connected to counter 54.
74163 enable inputs such as 0, DMA2 CO
Enable input of the NTROL circuit 670, DMA1 C
A synchronization control signal is generated on lead 521 connected to the start input of ONTROL circuit 570 and the clock input of 4-input D-type latch 1000. Counter 540
Has four output leads 541-544 connected to the first 4-bit input bus of comparator 550, the input of four-latch circuit 560 and the four address inputs of DMA1 CONTROL circuit 570. 4 latch circuit 56
0 has four output leads 561-564 connected to the second 4-bit input bus of comparator 550.
Comparator 550 has an output lead 551 connected to the load input of counter 540. The output of the demultiplexer circuit 300 is the 8-bit deserializer 410.
Connected to the serial input of. Deserializer 41
The 0 can be easily implemented by an octal D-type latch circuit such as 74373, as well as an 8-bit deserializer of format 74164. The deserializer 410 has an 8-bit output bus 411 connected to the input of a tri-state 8-bit buffer 340, the buffer output bus being the data bus 104 of the microcontroller 100,
It is connected to the data bus of RAM storage 580 and the input bus of octal D-type latch 720. In addition, the RAM storage device 580 includes a DMA1 CONTROL circuit 570.
RE connected to WRITE control lead 572 of
WRIT connected to the AD control lead wire 572, the READ control lead wire of the DMA1 CONTROL circuit 570, and the enable input of the 8-bit D-type latch 520.
It has a common control line such as the E control lead wire 571.
The chip select lead wire 573 of the RAM storage device 580 is
It is connected to the chip selection lead wire of the DMA1 CONTROL circuit 570. Finally, RAM storage 580
Has an address bus (not shown) connected to the address buses 541 to 544 of the DMA1 CONTROL circuit 570. In order to simplify the explanation, DMA1
It should be noted that the number of bits on the address bus of the CONTROL circuit is specified as 4, but any other number of bits is acceptable. Chip select lead 573 and WRITE control lead 572 are each connected to the input of OR gate 590, and its output lead 591 is connected to the first input lead of AND gate 2000. The AND gate 2000 has an output lead connected to the OUTPUT CONTROL lead of the deserializer 410, the latter control lead being the circuit 74373 included in the deserializer.
Corresponding to the OUTPUT CONTROL lead wire.
The microcontroller 100 has a group of programmable chip select leads used in both the transmitter and receiver of the terminal adapter in the preferred embodiment. Specifically, the microcontroller 100 has an OR with a second input lead 107 that receives a READ control signal generated by the microcontroller 100.
It has a CS4 chip select lead 106 connected to the first input of gate 360, whose READ control signal 107 is transmitted to the first input of OR gate 360. The OR gate 360 is the second gate of the AND gate 2000.
Input and OUTP of tri-state buffer 340
It has an output lead 361 connected to the UT CONTROL lead. The OR gate 350 is the CS5 chip select lead 108 of the microcontroller 100.
Connected to the first input, a second input for receiving a READ control signal, and a tristate buffer 3
30 OUTPUT CONTROL leads and A
It has an output lead 351 connected to the first input lead of ND gate 4000.

The output bus of the octal D-type latch circuit 710 is
It is connected to the 8-bit input of a selector 730 which has a second 8-bit input for receiving a fixed fixed byte corresponding to the SDLC '7E' flag. In the preferred embodiment,
The default byte is set by the wiring circuit.
Selector 730 sends DMA via SEL control leads.
2 Controlled by the CONTROL circuit 670. The output of the selector 730 is the serializer 77 whose output lead is connected to the first input of the OR gate 790.
An 8-bit bus connected to 0 parallel inputs. The serializer 770 is a DMA2 CONTROL.
It has a load input connected to the LOAD output of circuit 670, and a clock input that receives the clock signal generated at the output of AND gate 4101.

Similarly, B2 DATA IN lead wire 3
01 is an input lead wire of the clock generator 310,
Also, they are respectively connected to the inputs of the flag detector 420. Further, the clock generator circuit 310 receives the SCL clock on the lead wire 903 and supplies two types of clock signals. The byte clock signal on lead 3110 is the clock input to counter 640 and DM.
The bit clock signal transmitted on the clock input of the A2 CONTROL circuit 670 and on the lead wire 3111 is
It is transmitted to the first input lead of the ND gate 4101. As described above, the generation of the byte clock signal and the bit clock signal is easily performed using a group of frequency dividers known to those skilled in the art. The flag detector 420 is the first
Secondly, in order to detect the occurrence of the SDLC frame start flag and generate a control pulse on the lead wire 421 connected to the input lead wire of the control decoding circuit 610 at the time of occurrence, secondly, the occurrence of the SDLC frame end flag. Detected, D
FLAG END of the MA2 CONTROL circuit 670
(FE) the second on the lead wire 422 transmitted to the lead wire.
Used to generate the control pulse of The output lead of the flag detector 420 is B2 D at its data input.
It is used to synchronize the control decoding circuit 610 which receives the data flow present on the ATA IN channel.
The 3-bit decoding process that follows immediately after the start flag is the six output leads 611-61 depending on the value of those bits.
It results in the occurrence of pulses that occur in one of the 616 sets. More specifically, the lead wire 611 is connected to the detector 610.
Carries a pulse when the occurrence of pattern 000 is detected immediately after the SDLC start flag. The lead 612 indicates that the detector 610 has the pattern 100 immediately after the SDLC start flag.
The pulse is carried when the occurrence of is detected. Lead wire 6
13 carries a pulse when detector 610 detects the occurrence of pattern 110 immediately after the SDLC start flag.
Lead 614 carries a pulse when detector 610 detects the occurrence of pattern 010 immediately after the SDLC start flag. The lead wire 615 has an SDLC detector 610.
The pulse is carried when the occurrence of the pattern 111 is detected immediately after the start flag. Finally, lead 616 carries a pulse if detector 610 detects the occurrence of pattern 011 immediately after the SDLC start flag. Lead wire 61
1 to 614 are each connected to the four input leads of NOR gate 630, the output 631 of the NOR gate being used to generate an interrupt signal that is transmitted to the INT4 input of microcontroller 100. .. Lead wires 615 and 616 are each NOR
Connected to the two input leads of gate 620,
Its output is a synchronization control signal on a lead 621 connected to the enable input of the 74163 such as the counter 640, the enable input of the DMA1 CONTROL circuit 570, the start input of the DMA2 CONTROL circuit 670 and the clock input of the D-type latch 560. To generate.
The counter 640 includes a first 4-bit input bus of the comparator 650, an input of the 4-latch circuit 1000, and a DMA2C.
It has four output leads 641-644 connected to the four address inputs of the ONTROL circuit 670.
4 latch circuit 1000 includes a second input 4 of comparator 650.
It has four output leads connected to the bit bus. Comparator 650 has an output lead 651 connected to the load input of counter 640. The output of the demultiplexer circuit 300 is connected to the serial input of an 8-bit deserializer 430 having the same format as the deserializer 410. The deserializer 430 has an 8-bit output bus 431 connected to the input of the tri-state 8-bit buffer 330, the output bus of the buffer being the data bus 10 of the microcontroller 100.
4 is connected. The output bus 431 also includes a RAM storage 680 data bus and an octal D-type latch 710.
Is also connected to the input bus. In addition, the RAM storage device 680 is a WR of the DMA2 CONTROL circuit 670.
READ control lead 671 connected to ITE control lead, R of DMA2 CONTROL circuit 670
In addition to the EAD control lead, it has common control lines such as the WRITE control lead 673 which is also connected to the enable input of the 8-bit D-type latch 710. The chip select lead wire 672 of the RAM storage device 680 is DMA2.
It is connected to the chip selection lead wire of the CONTROL circuit 670. Finally, RAM storage 680 is DMA
2 address bus 641 of the CONTROL circuit 670
It has an address bus (not shown) connected to 644. Chip select lead 672 and WRITE control lead 671 are each connected to the input of OR gate 690 and its output lead 691 is connected to the first input lead of AND gate 4000.
The AND gate 4000 is the OU of the deserializer 430.
It has an output lead connected to the TPUT CONTROL lead, the latter control lead being the OUTPUT of the circuit 74373 included in the deserializer.
Corresponds to CONTROL lead wire. OR gate 350
Is the OUTPUT C of the tri-state buffer 330.
It has an output 351 connected to the ONTROL lead.

The output bus of the octal D-type latch circuit 720 is
It is connected to the 8-bit input of a selector 740 which has a second 8-bit input for receiving a fixed '7E' fixed pattern. The selector 740 is controlled by the DMA1 CONTROL circuit 570 via the SEL control lead wire. The output of the selector 740 has an output lead wire O
It is an 8-bit bus connected to the parallel input of the serializer 780 connected to the second input of the R-gate 790. The serializer 780 uses the DMA1CONTR
It has a load input connected to the LOAD output of OL circuit 570, and a clock input for receiving the clock signal generated at the output of AND gate 4100.

FIG. 6 exemplifies the transmitting unit of the terminal adapter of the present invention. The microcontroller 100 has a latch 110.
Has a data bus 104 connected to the input bus of the selector 120, and the output bus 111 of the latch is the first bus of the selector 120.
Input bus and the first input of the second selector 130. Both selectors 120 and 130 are 1
The highest 8 of each 6-bit deserializer circuit 230
Bit and its own second input bus connected to the least significant 8 bits, the deserializer of which receives the serial data flow from the data terminal device connected to the terminal adapter. The DTE and terminal adapter comply with the CCITT recommendation X. When communicating by 25, the data flow comes from the T lead. The Deserializer 230 also uses the SCL clock 90 at 512 Kbps.
The clock signal is received from the divide-by-four circuit 210 which receives 1. The microcontroller 100 has a group of three chip select leads CS1 102, CS2 103 and CS3 101. CS1 lead wire O
First input of R-gate 190 and flip-flop 1
40 and the CS2 chip select lead 103 is connected to the first input of the OR gate 250 and the set input of the flip-flop 150. CS3 chip select lead is flip-flop 1
Connected to both 40 and 150 reset input leads. The write output 105 of the microcontroller 100 is the second output of both OR gates 190 and 250.
Connected to the input of. The outputs of the OR gates are connected to the two input leads of the AND gate 260, and the output of the AND gate is an octal D-type latch 1
Connected to ten enable input leads. The true outputs of flip-flops 140 and 150 are connected to the SEL inputs of selectors 120 and 130, respectively. The selectors 120 and 130 include an input bus of the first serializer 160 and a second serializer 190.
It has an 8-bit output bus connected to each of the 0 input buses. The serializer 160 has an output connected to the B1 IN input of the B1 / B2 multiplexing control circuit 200, which circuit 200 also receives on its B2IN input lead the serial data flow coming from the output of the serializer 1900. To do. The multiplexing control circuit 200 has a U connected to the LOAD lead wire of the serializer 160.
U connected to the P B1 ENABLE output lead and the LOAD lead of the serializer 1900
P B2 ENABLE output lead. The multiplexing control circuit 200 has a lead wire 903 of 512 Kbps.
A second input for receiving the SCL clock, the output of which is connected to the shift input of the serializer 160,
B1 connected to the first input of AND gate 180
It has an ENABLE output lead. Similarly, the multiplexing control circuit 200 uses the lead wire 901 to similarly output 512 Kb.
It has a B2 ENABLE output lead connected to the first input of AND gate 190, which has a second input for receiving the ps SCL clock and whose output is connected to the shift input of serializer 1900. The multiplexing control circuit 200 generates the SDIR signal through the lead wire 902, the SCL signal through the lead wire 903, and the SLD signal generated by the ISDN interface controller 900 as described above.
The signal is received on lead 901. Multiplexing control circuit 20
0 is a set of two lead wires DOWN connected to the interrupt input lead wires INT1 and INT2, respectively.
B1 ENABLE lead and DOWN B2
Has ENABLE lead wire. Also, the data flow transmitted by the data terminal device is transmitted to the first input lead of the NAND gate 240 which receives a signal indicating the start of the frame. X. For the 21 interface, the signal matches the signal carried on the C lead. The output of NAND gate 240 is connected to the INT0 interrupt lead of microcontroller 100. The divided clock signal available at the output of divide-by-4 circuit 210 is also used as the bit element timing required by the DTE.

B1 / B2 multiplexing control circuit 200 has an output lead connected to an SLD lead 901 which carries multiplexed data coming from two shift registers 160 and 1900.

The terminal adapter according to the invention operates as follows.

The first stage is a terminal adapter by the integrated service digital network (hereinafter referred to as a calling terminal adapter).
Connection to a second terminal adapter (hereinafter, called terminal adapter). Such a connection is basically a C
CITT Recommendation I. 440. Briefly, a particular initialization communication protocol is implemented between the calling terminal adapter, the called terminal adapter and the integrated services digital network. That is, data is exchanged over the D channel to enable subsequent communications. After this first stage, both terminal adapters will then be able to exchange data over the first B channel.

As soon as one of the two B channels is assigned to the calling terminal adapter in the above-mentioned first step, that adapter transmits a predetermined SDLC frame to the other terminal adapter. The SDLC frame, in the preferred embodiment of the invention, is followed by one SDLC flag (7E in hex) followed by a particular byte that characterizes the B channel assigned to the terminal adapter. In the preferred embodiment, the most significant 3 bits of a byte that characterize the assigned B channel are: The first 3 bits are equal to "000" (in binary) if the terminal adapter is assigned the B1 channel, and "100" if the B2 channel is assigned.
be equivalent to. The byte can then be followed by a conventional frame check string (FCS) and an SDLC end flag before being transmitted by the ISDN network to the other end adapter.

Transmission of this SDLC frame is performed as follows. The microcontroller 100 generates the above-mentioned SDLC frame on the data bus 104,
The one-chip selection lead wire 102 is activated. As a result, the latch 110 is enabled and the flip-flop 140 is set. The SDLC data frame is
It is generated byte by byte in the data output bus and the microcontroller 100, then through the latch 110 to the first input bus 111 of the selector 120 and further to the input of the serializer 160. When one byte becomes available at the input of the serializer 160, that byte is transferred from the multiplexing control circuit 200 to the UPB1 ENA.
Loaded into the serializer by a pulse issued on the BLE and transmitted to the LOAD input of the serializer 160. Therefore, the serializer 160 produces a corresponding serial data flow at its output with the rhythm of the clock on its shift input lead. This clock is initially generated by AND gate 180 which receives the 512 Kbps SCL clock on lead 903 and the B1 ENABLE lead envelope signal generated by multiplexing control circuit 200. The envelope signal is high because the serial data flow is transmitted over the B1 channel just assigned to the calling terminal adapter. Multiplexing control circuit 200
Transmits the SDLC frame on the appropriate B channel through the SLD lead 901. This SDLC frame is transferred to the transformer 1001 and the connector 1 by the ISDN interface controller 900 of the calling terminal adapter.
000 to be transmitted to the ISDN network.

The called terminal adapter receives the SDLC frame and the receiver in the adapter begins processing the frame as follows. The SDLC frame is received by the demultiplexer circuit 300 via the ISDN interface controller 900 on the SLD bus lead 901. The demultiplexer circuit 300 has one of the two DATAIN B1 leads 302 or DATA IN B2 leads 301 S according to the B channel assigned to the called terminal adapter by the ISDN network.
Transmit a DLC frame. It is assumed that the ISDN network is assigned with a called terminal adapter by the B1 channel, for example. SDLC frame is DATA IN B
The control decoding circuit 51 after being generated by the one lead wire 302
0, input of flag detector 400 and deserializer 4
Transmitted to 10 inputs. Flag detector 400 is SDL
Upon detection of the C start flag, the detector produces a pulse at the IN input of the control decoding circuit 510 indicating to the detector that decoding of the bits immediately following the flag is required. The control decoding circuit 510 waits until the third bit following the start flag is received and produces an output pulse on one of the six leads corresponding to those 3-bit values. Since it is assumed that the calling terminal adapter is assigned the B1 channel, the called terminal adapter and the decoding circuit 510 therein have the pattern 000 (in hexadecimal).
, And produce an output pulse on lead 511. This pulse is then sent through NOR gate 530 to INT3 interrupt lead 53 of microcontroller 100.
1 is transmitted. This generated interrupt causes the microcontroller 100 to read the contents of the deserializer 410. To do this, the microcontroller 100 simultaneously generates an appropriate chip select signal on the CS4 lead 106 and a read signal on the lead 107, respectively, and the chip select signal is passed through the OR gate 360 and the AND gate 2000 to the deserializer. While transmitting an enable pulse to the output control (OC) input of 410,
The enable pulse is transmitted to the OC input of the tri-state buffer 340. The deserializer 410 checks the validity of its own data bus 411, and through the buffer 340, the data bus 104 of the microcontroller 100.
To produce its contents that will be transmitted to.

When the called terminal adapter identifies its first SLDC frame, the adapter begins transmitting a second SDLC frame of the same type as described above to the calling terminal adapter. Similar to the above, the transmitted SDLC frame contains specific bytes that indicate which B channel was assigned to the called terminal adapter. More specifically, when the B1 channel is allocated, the called terminal adapter has the most significant bit immediately after the SDLC start flag set to 01.
Transmit bytes that are 0. Conversely, if the B2 channel is assigned to the called terminal adapter, the called terminal adapter will transmit the byte whose most significant bit is 110. Again, assume that the called terminal adapter is assigned the B1 channel by the ISDN network. However, one of ordinary skill in the art should point out that the following description should be readily applicable even if the called terminal adapter is assigned the B2 channel. The transmission process of the second SDLC frame of the called terminal adapter is the same as the transmission of the first SDLC frame described above.

When the calling terminal adapter receives its second SDLC frame, the initialization procedure or protocol for the first B channel is complete and the calling terminal adapter has the first B channel actually operating in both directions. Guaranteed to be possible. From this moment, the called terminal adapter is
Waiting for channel establishment, which involves data exchange similar to that described above.

Once both B channels are guaranteed to be operational, the calling and called terminal adapters can begin transmitting and receiving data on their B channels.

In this transmission, the data terminal device connected to the terminal adapter receives 128 Kbps, for example, by receiving, for example, ready-for-data transmitted by the terminal adapter.
It is started when notified of the establishment of a channel. CCIT
Recommendation X. At 21, the DTE sets the C lead at the input of the NAND gate 240, so that the T signal at the input of the deserializer 230 is already high. The terminal adapter is sequence D1, D2, D3, D
4. ． ． The 128 Kbps data flow is received from the data terminal device. The terminal adapter, more specifically the deserializer 230, sends the flow to 64 Kbps 2
Separate into two different flows. First data flow D
1, D3, D5. ． ． Is the first of the deserializer 230
Is generated at the output of and is transmitted to the first input of the selector circuit 130. Similarly, the second data flows D2, D4,
D6. ． ． Is generated at the second output of the deserializer 230 and transmitted to the first input of the selector circuit 120. However, the actual transmission of the two data flows is likewise the start flag, identification byte, FCS and finally SLD.
It begins with the transmission of the third SDLC frame on the B channel, including the C end flag. This third identification byte is
It has the most significant 3 bits equal to 001 if the B1 channel is assigned to the calling terminal adapter by the network and 111 for the B2 channel respectively.

The data transmitted on each B channel begins with the same pattern, corresponding to the channel initially assigned to the calling terminal adapter.

Thus, the initialization protocol and data exchange between both terminal adapters could easily be performed as described above by the serializer and deserializer included in both the calling and called terminal adapters.

In all terminal adapters, the ISDN network does not guarantee the same transmission delay for each channel, but the receiver, in particular the circuit 9999, provides full synchronization of both B channels. .. This synchronization is performed as follows. The receiving part of one terminal adapter, in particular the control decoding circuits 510 and 610, waits for the occurrence of the above-mentioned third synchronized SDLC frame. Its occurrence depends on the actual transmission delay introduced by the network. B
Let us assume that one channel has a shorter transmission delay.
In that case, of the two control / decoding circuits 510 and 610, it is the control / decoding circuit 510 that first decodes the above-mentioned third synchronization pattern. Therefore, the control and decoding circuit decodes the occurrence of pattern 011 in the most significant 3 bits of the byte following the synchronized SDLC frame start flag. By this decoding, the OR gate 52
0 is the ENABLE input of the counter 540, DMA1
Generates a pulse that is transmitted to the START input of CONTROL circuit 570 and the RESET input of latch 560. The counter 540 starts operating from 0000 in hexadecimal with the rhythm of the byte clock on the lead 3210 generated by the clock generator 320. It should be pointed out that this byte clock is the result of a division by 8 of the bit clocks extracted from SCL lead 903. Deserializer 41
Bytes deserialized by 0 are then DM
Through the A CONTROL circuit 570, the counter 54
RAM storage device 5 at the address generated by the incremental output of 0
80 directly and sequentially. The third synchronized SDLC described above, received by the terminal adapter on the B1 channel, and also containing the above-mentioned identification byte (hex 011).
The data byte sequence contained in consecutive SDLC frames following the frame is stored in memory location 0000 to RAM.
Sequentially stored in 580. This storage process is pulsed by the byte clock. This sequential loading of data into RAM 580 results in data D2, D4, D6.
The sequence continues to be received on the B2 channel of the pattern 111, which is decoded by the control decoding circuit 610, which indicates that the sequence is enabled on the B2 channel. When detecting this pattern, the control decoding circuit 610 raises the lead wire 615 to a high level at the input of the OR gate 620. OR gate 620 is loaded with the current address value generated by counter 540, latch 560.
The corresponding high level is transmitted to the LOAD input of. Since both input buses of the comparator 550 are carrying the same digital value at this point, the comparator 550 will have a lead 55.
1 produces a pulse that is transmitted to the load input of the counter 540. From this point on, the counter 540 has its own D
0-D3 Preloaded with the value present on input lead 545. That is, it is reset to zero. Also, OR
The high level at the output of gate 620 is DMA1 C
It is transmitted to the ENABLE input of the ONTROL circuit 570. As soon as the first byte Dn of the B1 channel following the third synchronized SDLC frame, ie the first byte contained in the data field of the SDLC frame following the synchronized frame, is received on the B2 channel, D
The MA1 CONTROL circuit uses the RAM storage device 5 of the address generated by the counter 540, that is, 0000.
A read operation of the contents of 80 is executed. Data bus 104
D1 and D, which have already been loaded into the RAM 580 and are transmitted by the B1 channel.
3, D5. ． ． The data is a DMA1 CONTROL circuit 570 that generated a pulse on its read lead 571.
Is transmitted to the latch 720 which is enabled by. Bytes D1, D3, D5. ． ． Then the SEL input lead is DMA1 CONTR
The signal is transmitted to the 8-bit input bus of the selector 740 which is set to the high level by the OL circuit 570, and further to the 8-bit input bus of the serializer 780. The LOAD input lead wire is also DMA1 CONTR
Since it has been set to a high level by the OL circuit 570, the serializer 780 is generated by the AND gate 4100, and the bytes D1, D3, D5. ． ． Sequence is sequentially generated. The clock is AND gate 4100
The second input lead of the AND gate 4100 receives the bit clock generated by the clock generator 320, while the first input lead of the AND gate 4100 is B1.
/ B2 receives the B1 ENV envelope signal of B1 generated by the demultiplexer circuit 300,
It is a burst of 8-element bit clock pulses. Byte D1 stored in storage location 0000 is latched 720
Stored in the DMA1 CONTROL circuit 570
Causes the subsequent byte Dn appearing on the output bus of the deserializer to replace the preceding byte D1 and be loaded into RAM 580 at address location 0000. To do this, the DMA1 CONTROL circuit produces a low level on its WRITE output lead 572 while at the same time leads the chip select signal which causes a pulse to be transmitted through the OR gate 590 to the input of the AND gate 2000. 573. As above
Subsequent bytes are latched 560 at the rhythm of the byte clock transmitted from their storage location 0000 to the clock input of the counter 540 from the clock generator 320.
Are periodically and sequentially stored in the storage location defined by the contents of In parallel, DMA1 CONTROL
The circuit performs a read of RAM 580 at the same byte clock rhythm received on its input lead.
The data transmitted by the B1 channel and extracted from the storage device 580 is transmitted at 64 Kbps to the data terminal device connected to the terminal adapter via the OR gate 790.

Considering again the case where the signal "111" is decoded by the control decoding circuit 610, the OR gate 62
The high level produced at the 0 output is transmitted to the ENABLE input of the counter 640 which starts counting at the rhythm of the byte clock on the lead 3110 generated by the clock generator 310. As a result, DMA2C
The ONTROL circuit 670 generates a set of read control signals and write control signals for the RAM storage device 680. This read signal precedes the write signal. D is synchronized with the byte clock present on the lead wire 3110.
The MA2 CONTROL circuit 670 has a counter 640.
The read operation of the storage device is executed at the address designated by. The contents of the memory location at address 0000 are
It contains an SDLC flag of 7E at the start of transmission on the B2 channel and its ENABLE input is DMA2 CO
Since it is activated by the NTROL circuit 670,
It is transmitted to and stored in the latch 710. Then DMA2
The address 0000 is output by the CONTROL circuit 670.
The write operation is executed to the memory location of. That is, B
First byte sequence transmitted by two channels
The byte is stored in storage location 0000. Lead wire 3
When the next byte clock pulse occurs at 110, the counter 640 is incremented. But the latch 1000
The content of is loaded with the value 0000 (the two latches 560 and 100 loaded with a non-zero value
0 is the only latch corresponding to the B channel with the smaller transmission delay), comparator 65
The 0 output remains high, which prevents the increment. As a result, DMA2 CONTROL
Circuitry 670 stores each byte of the byte flow transmitted by the B2 channel at storage location 000 of storage device 680.
The data is sequentially stored in 0 and then unloaded and transmitted to the serializer 770.

B of leads 303 and 304, transmitted through AND gates 4101 and 4100 to the clock inputs of serializers 770 and 780, respectively.
Due to the presence of the 1 and B2 envelope signals, these serializers have their two byte sequences D1, D3, D5. ． ． And D2, D4, D6, D
8. ． ． Again to D1, D2, D3, D4 ,. ． ． Interleave to produce a continuous byte flow ordered by. Therefore, the output of the OR gate 790 is B1.
128 Kbps continuous data flow alternating 1 byte coming from the channel and 1 byte coming from the B2 channel
, Which causes both B channels to be resynchronized in phase.

Exemplary timing of the signals present at the output of the DMA1 CONTROL circuit 570 is shown in FIGS. 8 and 9 and a description of its state machine is shown in FIG.

After the byte loaded in storage location 0000 has been read by the DMA1 CONTROL circuit 570,
The circuit waits for the next byte.

Microcontroller 10 of terminal adapter
At 0, a timer is implemented that ensures that both B channels are established and operational within a predetermined time period.
If the second B channel is not available at the end of the period, the microcontroller 100 disconnects the first B channel and informs the application program that the connection was not successful.

Further, the terminal adapter includes a counter 54
Both 0 and 640 prevent overflow that would result in loss of data received from the network,
An overflow detector is included. In case of such an overflow, the microcontroller 100 again makes the above-mentioned disconnection of both B channels.

It has to be pointed out that the invention can also be used with terminal adapters having more than two channels. In particular, the present invention can be implemented for primary access to many basic terminal adapters. This could be done by using as many circuits for circuit 9999 as there are channels to be multiplexed. Furthermore, those skilled in the art will appreciate that the control decoding circuits 510, 610 ,. ． ． Could be easily adapted so that their circuits would decode the 4 or more most significant bits of the identification byte.

Finally, only RAM storage, only D
The MA CONTROL circuit 570 and unique counter 540 have a single 128 Kb with two B channels.
It has to be pointed out that in the case of ps channels it can be multiplexed in order to simplify the structure of the terminal adapter. This is the first assigned to the terminal adapter
This is possible because only one circuit 9999 corresponding to the B channel of the is completely used.

The initialization protocol of the second B channel assigned to both the calling terminal adapter and the called terminal adapter is executed as follows.

That is, if the other B channel is assigned to the calling terminal adapter, the ISDN interface controller 900 causes an interrupt to the microcontroller 100, causing the second B channel (ie, the first B channel to be B1). Assuming a channel, B
2 channels are assigned).
After that, the microcontroller 100 similarly
Generate a first B2 synchronized SDLC frame containing an LC start flag, an identification byte in which the first 3 most significant bits are decoded, a frame check string and an end flag. As before, the identification byte depends on which B channel was assigned to the terminal adapter. here,
Since the second B channel assigned to the calling terminal adapter is the B2 channel (the B1 channel was already assigned in the above premise), the identification byte has the first 3 most significant bits of 000. .. The generation and transmission of this B2 synchronization frame is executed by the serializer 160 and the B1 / B2 multiplexing circuit 200 as described above. The called terminal adapter is the first B2
Upon identification of the synchronization frame, the frame has the same structure as described above, that is, it includes an SDLC start flag and a specific byte indicating the nature of the remaining B channel that has not yet been assigned to the called terminal adapter. B
2 Start transmission of the synchronized SDLC frame. The remaining channel was the B2 channel, so the called terminal adapter transmits a byte whose most significant bit is 110. The transmission process of the second synchronized SDLC frame at the called terminal adapter follows the above description.

The calling terminal adapter has its second synchronization SD
Upon receiving the LC frame, the calling terminal adapter returns a third synchronized SDLC frame, which also includes a start flag and an identification byte having the most significant 3 bits, which is 111 because the B channel has already been allocated.

Upon receipt of this third synchronized SDLC frame, the initialization procedure or protocol for the second B channel is complete and the calling terminal adapter has data transmission on its assigned B channel, ie The transmission of the SDLC frame including the data by the B channel on the premise of is started.

The invention is particularly suitable for the transmission of multimedia data. In fact, since multimedia data includes voice, image, video, facsimile and ordinary data, the problem with the prior art is that only common ISDN networks have multiple transmission rates while providing dual 64 Kbps B channels. It was in the way to give a proper set of channels. Therefore, the conventional solution for transmitting both voice and video has been to allocate the first B channel for voice and the second B channel for video. However, such a solution, in some cases, may not be suitable for transmitting either voice or data. The 64 Kbps channel is not sufficient for transmitting high definition images, while it is considered too fast for transmitting voice.

The terminal adapter according to the invention solves this problem by dividing a single 128 Kbps channel into adaptive sub-channels of suitable size. In the preferred embodiment of the invention, a single 128K
The bps channel is split to create a first 112 Kbps channel that can be used for high definition video data and a second 16 Kbps channel that can be used for voice transmission. This is done by separating the 16-bit set, which is the combination of the first byte transmitted by the B1 channel and the second byte transmitted by the B2 channel. These 16 bits are split into the 14 bit set used for video and the remaining 2 bits for audio.

However, it should be pointed out that the present invention can be used to provide a set of two different 56 Kbps channels for normal video instead of a single 112 Kbps channel for high definition video. I won't More generally, the 16 bits transmitted by the B1 and B2 channels can be divided into two different parts whose size can be selected according to the requirements of the user to give the desired transmission rate. ..

[0046]

As is apparent from the above description, according to the present invention, a data communication device such as a data terminal device is connected to a digital communication network having first and second channels with different transmission delays. A device can be provided.

[Brief description of drawings]

FIG. 1 shows a first part of a preferred embodiment of the receiving part of a terminal adapter according to the invention.

FIG. 2 shows a second part of the preferred embodiment of the receiving part of the terminal adapter according to the invention.

FIG. 3 shows a third part of the preferred embodiment of the receiving part of the terminal adapter according to the present invention.

FIG. 4 shows a fourth part of the preferred embodiment of the receiving part of the terminal adapter according to the present invention.

FIG. 5 is an explanatory diagram showing a connection relationship of each part of FIGS. 1 to 4.

FIG. 6 shows a preferred embodiment of the transmitter of the terminal adapter according to the invention.

FIG. 7 is a flow chart illustrating a direct memory access (DMA) control state machine diagram of the present invention.

FIG. 8 is a time chart for explaining the operation of the preferred embodiment of the present invention.

FIG. 9 is a time chart for explaining the operation of the preferred embodiment of the present invention.

FIG. 10 is a time chart for explaining the operation of the transmitting unit according to the preferred embodiment of the present invention.

[Explanation of symbols]

100 Microcontroller 200 B1 / B2 Multiplexing Control Circuit 300 B1 / B2 Demultiplexer Circuit 310,320 Clock Generator 400,420 Flag Detector 410,430 Deserializer 510,610 Control Decoding Circuit 1, 550,650 Comparator 1,2 570,670 DMA1, DMA2 CONTROL
Circuit 580,680 RAM 1,2,730,740 Selector 770,780 Serializer 900 ISDN interface controller

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Marc, Lambretton Antibes, Schumann, De, Lavia, France, 825 (72) Inventor Jean-Francois, Le, Pune Nice, Abnyu, Saint, Maurice, France 3 (72) Inventor Patrick, Michel France La, Gorde, Schmann, Fon, de, Reeve (no address) (72) Inventor Patrick, Siksik France La, Cole, Sur, Lou, Villa, Ah / 10, Bastade, Du, Roux, Schmann, De, Les Coules (no address) (72) Inventor Joseph, Spatari Cagnes, France, Sur, Mer, Ryu, Maurice, Rostan, 14 Residence, Le, Bocage, Saint-Bellan

Claims (7)

[Claims] 1. At least a first (B1) and a second (B)
2) a digital communication channel, the first channel having a first transmission delay and the second channel having a second transmission delay for connecting a data communication device to a digital communication network. A device, a transmitter having means (230) for separating a single high speed data flow received from said data terminal device into two different low speed data flows, each of said low speed data flows being said Digital channel (B1, B
The difference between the transmission unit, which is transmitted by different channels in 2), the storage means (580, 680) for storing the data received from the digital communication network, and the difference between the two transmission delays. Means (510,610), addressing means (570) for addressing said storage means (580,680) for extracting the data received by the two digital channels, introduced by both digital channels A receiver having control means (540, 550) for controlling the addressing means in response to the transmission delay difference to provide a high speed data flow that is not affected by the transmission delay difference. A device for connecting a data communication device to a digital communication network characterized by the above. 2. The transmitter comprises means (100, 110, 120) for adding to each low speed data flow a unique identifier characterizing the digital channel concerned, and the receiver further comprises the digital network. Detecting means (510) for detecting the reception of said identifier received from, and detecting the occurrence of a second identifier to start counting upon detection of the first detected identifier and to generate a continuous address sequence. Counting means (540), which are sometimes reset, and means for storing a succession of data received from the digital channel with the smaller transmission delay in the storage means (580) at the address generated by the counting means. (570), and 1 byte extracted from the storage means to provide a fully synchronized high speed serial data flow and a low speed data. Means for applying a high speed serial data sequence consisting of an alternation with a byte received from the digital channel (770, 780), said means being active upon detection of the second identifier; The apparatus of claim 1, comprising: 3. The data communication device is provided with the first and second devices.
3. Device according to claim 2, characterized in that it comprises means (100) for carrying out an initialization procedure to indicate that the digital channel of the device is operational. 4. Timing means for measuring the delay between the establishment of both said first and second digital channels, and already established if the measured delay exceeds said predetermined level. 4. The apparatus of claim 3 including means for disconnecting the digital channel. 5. Apparatus according to claim 4, including overflow detection means for disconnecting the digital channel when an overflow of said storage means (580) is detected. 6. The device according to claim 1, wherein the device resides in a terminal adapter for an ISDN network that enables establishment of a fully synchronized 128 Kbps data communication link. 7. The 128 Kb to provide a set of different digital channels with adaptive data rates for simultaneous transmission of data, video and voice.
7. The apparatus of claim 6 including means for performing a ps time division multiplexing process.