JPH05233288A - Information processor - Google Patents

Abstract

PURPOSE:To make it possible to restart a task whose control is transferred to another task due to the generation of an exception and to prevent the drop of performance. CONSTITUTION:This information processor has the 1st flag to be changed by a previously determined instruction in order to make a memory access instruction exception accurate, plural control means (4, 5, 21 to 25) for delaying the updating of an instruction counter due to the issue of the 2nd instruction following the 1st instruction until the end of exception detecting processing for the 1st instruction for executing processing relating to a memory access in accordance with the value of the 1st flag, the 2nd flag to be changed by a previously determined instruction in order to make arithmetic instruction exception accurate, and plural control means (4, 5, 21 to 25) for delaying the updating of an instruction counter due to the issue of the 4th instruction following the 3rd instruction for executing processing relating to arithmetic until the end of the exception detecting processing for the 3rd instruction in accordance with the value of the 2nd flag.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction control system of an information processing apparatus, and more particularly to an information processing apparatus for realizing an exception processing accuracy system.

[0002]

2. Description of the Related Art Conventionally, there are the following two examples of this type of information processing apparatus. They have the instruction pipeline configuration shown in FIGS. In FIG. 3, 3-1 is a D stage instruction register, 3-2 is an instruction decoder, 3-3 is an A stage instruction register, 3-4 is an address adder, 3-5 is a T stage instruction register, and 3-.
6 is TLB (Translation Lookasi)
de Buffer), 3-7 is an OF stage instruction register, 3-8 is a memory (cache), 3-9 is an E stage instruction register, and 3-10 is an ALU (Arithum).
etic Logical Unit), 3-11 is W
Stage instruction register, 3-12 is GR (Genera)
l Register: a general-purpose register). In FIG. 4, 4-1 is an A stage instruction register, 4-2 is an instruction decoder, 4-3 is a B stage instruction register, 4-4.
Is a GR, 4-5 is a C stage instruction register, 4-6 is an address adder, 4-7 is a D stage instruction register, 4-
8 is an M1 stage instruction register, 4-9 is an M2 stage instruction register, 4-10 is an Mn stage instruction register,
4-11 is W stage instruction register, 4-12 is F1 stage instruction register, 4-13 is F2 stage instruction register, 4-14 is Fm stage instruction register, 4-15
Is GR.

Next, the operation will be described. First, FIG.
An instruction pipeline method mainly used in a general-purpose computer as shown in FIG. For simplification of description and simplification of comparison with the instruction pipeline shown in FIG. 4, the stage for fetching an instruction is omitted, and the function recovery at each stage is abstracted.
The D stage instruction register 3-1 sets an instruction code in the D register in order to decode the fetched instruction. Then, in the A stage instruction register 3-3, in order to calculate the memory address of the operand, the input data of the address adder 3-4 is set in the A register, and the logical address of the operand is calculated. The T stage instruction register 3-5 stores the logical address calculated by the address adder 3-4 in the T register, and the TLB 3-6 converts it into a physical address. OF stage instruction register 3-7 is OF
The physical address of the operand is stored in the register, and the operand is fetched from the memory (or cache) 3-8. Then, in the E stage instruction register 3-9, E
The operand fetched from the memory is stored in the register, and the ALU3-10 performs the operation. In the W stage instruction register 3-11, the result calculated by the ALU 3-10 is W
Store in a register and store the result in GR3-12. In this way, even if there are some differences in the number of stages,
GR from D stage instruction decode to W stage result
A general-purpose computer is generally used for each machine cycle until writing, and performs parallel processing flow-wise to improve performance.

Next, a computer in which memory access processing or arithmetic processing is multistaged as shown in FIG. 4 will be described. Such an information processing device is called a super pipeline.

First, the operation of the memory access instruction will be described. For example, in the case of a load instruction, the fetched instruction code is stored in the register A in the A stage instruction register 4-1 and decoded. B stage instruction register 4
In -3, the control information obtained by the instruction decoder 4-2 is stored in the register B, and the input data for calculating the logical address to be loaded is read from the GR 4-4. The C stage instruction register 4-5 stores the data read from the GR 4-4 in the register C, and the address adder 4-6 calculates the logical address of the data to be loaded. The D stage instruction register 4-7 analyzes the busy status of the functional units related to memory access and controls the issuing of instructions. The instruction issued from the D stage instruction register 4-7 is M1.
From the stage instruction register 4-8 to the Mn stage instruction register 4-10, cache access, TLB index (TLB index is first in the case of physical address cache), and main memory access is performed when the cache misses. .. The loaded memory data is stored in the W register of the W stage instruction register 4-11 and in the GR 4-15 in the next cycle, and the execution of the instruction is completed.

Next, the operation of the arithmetic instruction will be described. The A stage instruction register 4-1 to the D stage instruction register 4-7 are the C stage instruction register 4-5.
It is the same except that the address calculation is not performed in. Then, the instruction issued from the D stage instruction register 4-7 is operated in the F1 stage instruction register 4-12 to the Fm stage instruction register 4-14. Finally, the result is stored in GR 4-15 by the W stage instruction register 4-11.

Next, comparing the general-purpose machine type pipeline of FIG. 3 with the super pipeline of FIG. 4, the advantage of the general-purpose machine type is passed by the pipeline because the number of pipeline stages is small. The number of storage elements for holding the control information is small, and conversely, the machine cycle cannot be shortened due to its merit and the performance is not improved. Therefore, the super pipeline of FIG. The opposite can be said. In addition, in the super pipeline of FIG. 4, when a memory access instruction is executed, for example, even if a cache miss occurs, the entire instruction pipeline does not stop unlike the general-purpose machine of FIG. Is also possible. In addition, IC (In
The timing of updating the Structure Counter is different between the general-purpose machine and the super pipeline.
In the case of a general-purpose machine, it is performed at the transition timing of the E → W stage after confirming that the execution of the instruction corresponding to the IC is completed without any exception. On the other hand, in the super pipeline, it is often performed in the D stage which is the instruction issuing stage. The reason is that it is very difficult to maintain the instruction execution order after the D stage. For example, when a cache miss occurs in the M1 to Mn stages during execution of a memory access instruction, the time from issuance until the result is stored in GR becomes unpredictable. Therefore, the GR write of the subsequent operation instruction may be performed first. However, this type of computer often has a control mechanism for guaranteeing the execution result even if such a write timing overtaking occurs.
As an example, a system called a register scoreboard realized by a computer called CDC6600 has been generated in the past. (Reference: THORNTON.JE [1
964]. "Parallel operation
in the Control Data 660
0 ”,“ Proc. Fall Joint Compu
ter Conf. 26, 33-40] or TH
ORNTON, J. E. [1970]. Design
of a Computer, the Control
Data 6600, Scott, Foresma
n, Glenview, I11. )

Next, the process switching operation in the information processing apparatus will be described with reference to FIG. This Figure 5
5-1 is PSW (Program Stat)
us Word) 5-2 is IC (Instructi)
on Counter), 5-3 is GR (Genera)
l Register: general-purpose register), 5-4 is CB
P (Current Block Pointer),
5-5 is NBP (New Block Point)
r) and 5-6 are memories. A user program executed on an information processing device that realizes a multi-task environment is divided into processing units called multiple processes, and CPU time is divided for each process in order to effectively use shared hardware resources. Has been processed. In FIG. 5, when the process A is first executed as shown in FIG. 5A, an exception occurs, the execution of the process B is switched to the execution of the process B by the sequence A, the execution of the process B is completed, and the process A is executed by the sequence B. It shows until the execution is switched to.

Then, the process always holds the information indicating the execution state called context, and when the process is in execution, the context is prepared by hardware and the PSW 5-1 shown in FIG. 5B is used. , IC5-
2, GR5-3 exists in a high-speed storage area in the CPU. This context is mainly PSW5-1, IC
5-2, structural data composed of values to be stored in GR5-3. Here, the PSW 5-1 is composed of a flag group or the like that indicates the state of the process or whether the process allows interrupt reception. IC5-2 indicates the address in memory where the next instruction currently being executed in the process is located. GR5-3 is the value of the general-purpose register. Most of the existing information processing devices include the above three as context. Sequence A saves the context of process A in memory and then stores the context of process B in memory 6.
To load from. On the contrary, the sequence B loads the context of the process A from the memory 6 after saving the context of the process B in the memory.

The sequence A will be described in more detail with reference to FIG. New CBP
In the storage areas 5-4 and NBP5-5 existing in the CPU, the addresses in the memory for saving the context of the currently executing process A are held.
5 stores the address in the memory where the context of the process newly executed after saving the running process is present. The values of these CBP5-4 and NBP5-5 are usually managed by software called an operating system. Then, the context of the process A is the storage area in the CPU, PSW5-1, IC.
5-2 and GR5-3. That is, an exception occurs while the process A is being executed, and the context of the process A is set to the memory 5-shown by CBP5-4.
Save to address 6 above. After that, the context of the process B is loaded as from the address on the memory 6 indicated by NBP5-5 on the memory 5-6.

As described above, even when an exception occurs, the correctness at the restart of the process A is guaranteed as long as the value of the context is accurately held.

[0012]

The above-mentioned conventional information processing apparatus has a problem due to the structure of the computer having the configuration described in FIG. That is, it is difficult to guarantee the instruction execution order after the instruction issue stage.
The update timing must be the instruction issue stage. As a result, it becomes difficult to guarantee the correctness of the IC value when an exception occurs, which makes it difficult to restart the process that was saved due to the exception.
The biggest impact of the challenge is that the operating system cannot enjoy the virtual memory function. The mechanism will be described with reference to FIG. When the memory access instruction is executed in the process A, if the result of indexing the TLB reveals that the address to be accessed does not exist in the real memory, an exception occurs in the memory access instruction. An exception of this kind,
It is often called a page fault exception. When the exception occurs, the sequence A is activated and switched to the process B. Then, the process B loads the memory space required by the exception-occurring memory access instruction of the process A from the secondary storage such as a disk into the real memory, and the memory space requested to the TLB is stored in the real memory. TLB to exist
Rewrite. This operation means rewriting the bit indicating the presence / absence in the entry of the TLB corresponding to the page of the TLB. When the processing of the process B is completed, the execution control is transferred to the process A by the sequence B. In the process A, the execution is resumed from the execution of the memory access instruction that caused the page fault exception. By providing such a function by the hardware, the designer who programs the process A can think of the secondary storage as if it were the real storage, and therefore the programming and the real storage management are easy. Produces a great effect. A function represented by this function is generally called a virtual memory function.

However, in the information processing apparatus of the super pipeline system as shown in FIG. 4, it is impossible to resume the execution from the exception generating instruction of the process A by the sequence B. The biggest cause is that the context of the process A cannot be accurately stored in the sequence A, and the inaccuracy of the IC has a great influence among them.
This operation will be described with reference to the time chart of FIG. First, FIG. 6 explains the IC update timing when an exception occurs in the super pipeline computer of FIG.

In FIG. 6, cycles (5), (6) and (7) in which memory access instruction 1, instruction 2 and instruction 3 are successively processed starting from the A stage, and falling from the D stage to the M1 stage. It becomes ISSUE timing. One cycle later, that is, cycle (6),
At (7) and (8), the IC update instruction signal is generated, and one cycle later, the IC is counted up by +4. In FIG. 6, the symbol * indicates that an interrupt has occurred in instruction 2. Then, in the slowest case, the exception is instruction 2, M
It occurs in the 6-stage cycle (12). After the occurrence, all the subsequent instructions are canceled, and after the execution of the preceding instruction is completed, an interrupt sequence like the sequence A described in FIG. 5 is activated. However, the value of the IC saved as context in the interrupt sequence is
Since the instruction following the instruction 3 is shown, the restart by the sequence B as described in FIG. 5 is impossible. Therefore,
As shown in FIG. 2, it is possible to postpone issuing the subsequent instruction until it is confirmed that an exception does not occur. That is,
A flag indicating that it is confirmed that no exception has occurred is prepared, and when instruction 1 passes through the M6 stage, the flag is reset (cycle (11)), and the instruction 2 that follows the instruction Adopt control to postpone issuance of.

When this method is adopted, the issuance of all the instructions after the issuance of the memory access instruction comes after eight cycles, which has a great influence on the performance. However, when that method is adopted, as shown in FIG. 2, when an exception occurs at the M6 stage in the instruction 2, (cycle (19)) I
The value of C indicates the instruction 2 when the interrupt sequence occurs because the IC update by the instruction 2 is canceled. Therefore, it is possible to restart from the instruction 2.

To summarize the above description, it can be concluded that there is a dilemma that the performance is lowered for the accuracy of exception handling. That is, it can be said that the configuration that emphasizes the exception processing accuracy is the general-purpose machine system in FIG. 3 and the configuration that emphasizes the performance is the super pipeline system in FIG.

[0017]

According to the information processing apparatus of the present invention, the memory access after the instruction is issued is processed in a plurality of stages, and the next instruction can be issued before the processing of the preceding instruction is completed. In an information processing device that performs pipeline processing, a first flag that can be changed by a predetermined instruction, and an exception of the first instruction that performs processing related to memory access according to the value of the first flag The control means is provided to postpone the update of the instruction counter by the issuance of the second instruction following the first instruction until the end of the detection processing. An information processing apparatus according to another invention of the present invention executes a pipeline process in which an operation after issuing an instruction is processed in a plurality of stages and the next instruction can be issued before the processing of the preceding arithmetic instruction is completed. In the information processing apparatus to perform, until the end of the exception detection process of the second instruction that can be changed by a predetermined instruction and the third instruction that performs processing related to the operation according to the value of the second flag The control means is provided to postpone the update of the instruction counter by issuing the fourth instruction subsequent to the third instruction.

[0018]

In the first aspect of the present invention, the software can instruct the hardware to execute the instruction in consideration of the memory access type exception precision, and in the second aspect,
Similar to the memory exception correction, the operation of the second flag allows the program developer to specify the execution part that requires exception correction, thereby realizing the operation exception correction without degrading the performance.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of the present invention and shows an example in which the present invention is realized based on the super pipeline type computer explained in FIG. In FIG. 1, 1 is an instruction pipeline control unit, 2 is a PS
W, 3 is an "ISSUE" flag, 4 is an IC update flag,
5 is an IC update postponement flag, and 6 is an IC (Instruct
Ion Counter), 7 is an interrupt sequence control unit, 8 is a +4 incrementer, 9 is a memory system exception detection unit, 10 is an A stage instruction register, 11 is a B stage instruction register, 12 is a C stage instruction register,
13 is a D-stage instruction register, 14 is an M1 stage instruction register, 15 is an M2 stage instruction register,
16 is an M3 stage instruction register, 17 is an M4 stage instruction register, 18 is an M5 stage instruction register, 19 is an M6 stage instruction register, 20 is an M7 stage instruction register, 21, 22 and 23 are AND circuits, 24 , 25 are OR circuits.

In the information processing apparatus which executes pipeline processing capable of issuing the next instruction before the memory access after issuing the instruction is processed in a plurality of stages and the processing of the preceding instruction is not completed, FIG. The shaded portion in PSW2 of is a first flag that can be changed by a predetermined instruction, and the IC update flag 4, the IC update postponement flag 5, the AND circuits 21 to 23, and the OR circuits 24 and 25 are Control for postponing the update of the instruction counter due to the issuance of the second instruction following the first instruction until the exception detection processing of the first instruction, which performs processing related to memory access according to the value of the flag of 1, is completed. Constitutes a means. In addition, in the information processing apparatus that executes the pipeline processing capable of issuing the next instruction before the processing of the preceding arithmetic instruction is completed by the operation after the instruction issuance being processed in a plurality of stages, the PSW2 of FIG. The shaded portion is a second flag that can be changed by a predetermined instruction, and includes the IC update flag 4, the IC update deferment flag 5, the AND circuits 21 to 23, and the OR circuit 24,
25 updates the instruction counter by issuing a fourth instruction subsequent to the third instruction until the end of the exception detection processing of the third instruction that performs processing related to the operation according to the value of the second flag. It constitutes a control means for postponing.

Next, the operation of the embodiment shown in FIG. 1 will be described. First, here, the A-stage instruction register 10
The instruction pipeline control unit 1 performs various controls from the instruction register 13 of the D stage to the instruction issuance. The signal lines 110, 111, 112, 113 for sending the instruction signal to each stage of the instruction pipeline are hold signals for stopping the flow of the pipeline of the A to D stages. The instruction issue timing is determined by the instruction pipeline control unit 1, the instruction is sent out by the signal line 1003, and the "ISSUE" flag 3 is turned on. Further, in the next cycle, the IC update flag 4 is turned on by the signal line 3040. The signal line 3040 is connected to the AND circuit 21.
Is also connected to. Then, the instruction pipeline control unit 1 sends out "1" if the instruction existing in the D stage on the signal line 1021 is a memory access instruction. Furthermore, P
An instruction of a certain memory system exception precision flag in SW2 is sent to the AND circuit 21 through the signal line 2021. Therefore, at the "ISSUE" timing of the memory access instruction, and when the memory system exception precision flag is turned on,
The IC update postponement flag 5 is set. Further, the AND circuits 22, 23, and the OR circuit 24 realize the operation described below. That is, when the memory system exception precision flag is not lit, the signal line 2406 sends “1” at the lighting timing of the IC update flag 4 and the signal line 6
060,8060 and +4 incrementer 8
The value of C6 increases by "4".

Next, when the memory system exception precision flag is turned on, the signal of the IC update flag 4 cannot update the value of the IC 6 by turning on the IC update postponement flag 5, and the update instruction signal Disappears by the AND circuit 22. However, the IC update request itself is held in the IC update postponement flag 5 and the signal indicating the absence of detection of a memory system exception is sent by the signal line 9025.
The signal line 2406 sends “1” through the D circuit 23 and I
The value of C6 is updated. Then, the memory access instruction reaching the M6 stage is analyzed by the signal line 1909, and the control information of the instruction register 19 of the M6 stage is analyzed by the memory system exception detection unit 9. Here, if an exception occurs, "1" is sent to the memory system exception occurrence signal 9007, and if it does not occur, "1" is sent to the memory system exception non-detection signal line 9025. When an exception occurs, the signal line 9007 notifies the interrupt sequence control unit 7 of the memory system exception occurrence and activates the interrupt sequence. Then, when the exception occurs, the update request stored in the IC update postponement flag 5 is sent to the signal line 9007,
Reset via the OR circuit 25 and the signal line 2505,
Although the update request of the IC 6 is canceled, when it is confirmed by the signal line 9025 of the memory system exception-free detection, the IC update postponement flag 5 is similarly reset, and at the same time, A
The value of the IC 6 is updated via the ND circuit 23, the signal line 2324, the OR circuit 24, and the signal line 2406.

Next, the continuous operation of the instruction 1 and the instructions 2 and 3 which generate an exception in the embodiment of the present invention will be described with reference to the time chart of FIG. During this operation, the memory system exception precision flag of the PSW 2 is on, the instructions 1 and 2 are memory access instructions, and the instruction 3 is an arbitrary instruction. First, the instruction 1 reaches the D stage in the cycle (5), is "ISSUE", and turns on the IC update flag 4 in the next cycle (6). However, since the memory system exception precision flag is lighting, the IC update request is not accepted and the IC update request is not accepted.
The update postponement flag 5 is set in cycle (6). After that, the instruction 1 reaches the M6 stage in the cycle (11) and no exception occurs therein, so the IC is updated by the memory system exception non-detection signal and the IC update postponement flag 5 is reset (cycle (12 )). Next,
One cycle later (cycle (13)), the instruction 2 becomes “I
SSUE ”. Then, as in the case of the instruction 1, the IC update is postponed and reaches the M6 stage, but an exception occurs there, and the instruction 2 and the subsequent instruction 3 are canceled by the memory system exception generation signal (cycle (20)). Then, after the execution of the instructions before the instruction “1” is completed, the interrupt sequence control unit 7 activates the interrupt sequence. Since the value of the IC saved at this time points to the instruction that caused the exception, it can be restarted.

In FIG. 1, the configuration of the embodiment according to the present invention will be described in more detail by focusing on the memory access side. Supplementing the operation of the embodiment shown in FIG. 1, the exception that occurs during memory access does not occur after the M6 stage. That is, if the instruction arrives at the M7 stage without being canceled, it can be determined that the instruction ends normally without causing an exception. Further, for simplification of description, the memory is byte addressing, and the instruction length is all 4 bytes.

As described above, the present invention provides an information processing apparatus capable of executing the next instruction before the processing of the preceding instruction is completed before the processing related to memory access after the instruction is issued spans a plurality of stages. Is a writable flag by an instruction, and until the first instruction that requires processing related to a certain memory access may cause an exception depending on the value of the first flag. By providing the control means for postponing the update of the instruction counter due to the issuance of the subsequent second instruction, it is possible to instruct the software to execute the instruction in consideration of the memory access system exception precision. That is, the program developer recognizes an execution part of the memory system that requires exception precision, and by delaying the IC update of the subsequent instruction by rewriting the first flag only for that part, the exception can be performed without degrading the performance. Accuracy is realized. This can eliminate the dilemma mentioned in the task.

On the other hand, in the information processing apparatus capable of executing the next instruction before the processing of the preceding arithmetic instruction is completed by the arithmetic processing after issuing the instruction straddling a plurality of stages.
Depending on the second flag writable by the instruction and the value of the second flag, the third instruction requiring the arithmetic processing may not generate an exception until the succeeding fourth instruction. By having the control means for postponing the update of the instruction counter due to the issue, the program developer is allowed to specify the execution part that needs the exception correction by operating the second flag as in the memory exception correction. With this, it is possible to realize the accuracy of the operation exception without degrading the performance. Then, such instruction control is provided by hardware. For example, if the program developer or the operating system designer can predict the occurrence of a page fault exception, or if it is unknown whether a page fault exception will occur. The present invention exerts a great effect if it can be narrowed down.

[0027]

As described above, according to the present invention, it is possible to instruct the software to execute the instruction in consideration of the memory access type exception precision in the software, and in the same manner as the memory type exception precision, the second aspect of the present invention is provided. By allowing the program developer to specify the execution part that requires exception precision by manipulating the flag, without significantly reducing performance,
It is possible to restart after exception handling, which has the effect of ease of programming and multitask management.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram for the timing of continuous issuance of instructions in the super pipeline system according to the present invention, which is used for explaining the operation of FIG.

FIG. 3 is an explanatory diagram showing a configuration example of a pipeline in a general-purpose computer.

FIG. 4 is an explanatory diagram showing a configuration example of an instruction pipeline in a super pipeline system.

FIG. 5 is an explanatory diagram showing a process context switching process in the information processing apparatus.

FIG. 6 is an explanatory diagram of timings of continuous issuance of instructions in a conventional super pipeline system.

[Explanation of symbols]

 1 Instruction Pipeline Control Unit 2 PSW 3 ISSUE Flag 4 IC Update Flag 5 IC Update Postponement Flag 21-23 AND Circuit 24, 25 OR Circuit

Claims (2)

[Claims] 1. An information processing device that executes pipeline processing in which memory access after issuing an instruction is processed in a plurality of stages, and the next instruction can be issued before the processing of the preceding instruction is completed, is predetermined. The first flag that can be changed by the instruction and the first instruction that continues until the end of the exception detection processing of the first instruction that performs processing related to memory access according to the value of the first flag. Second
An information processing apparatus comprising: control means for postponing update of an instruction counter due to issuance of the instruction. 2. An information processing apparatus that performs a pipeline process in which an operation after issuing an instruction is processed in a plurality of stages and the next instruction can be issued before the processing of the preceding arithmetic instruction is completed is determined in advance. The second flag that is changeable by the second instruction, and the third instruction that follows the third instruction until the exception detection processing of the third instruction that performs processing related to the operation according to the value of the second flag is completed. 4. An information processing apparatus, comprising: control means for postponing update of an instruction counter due to issue of instruction No. 4.