JPH0522742A - Image signal synchronizing circuit - Google Patents

Abstract

PURPOSE:To realize an image signal synchronizing circuit that can record a plurality of programs at a time by storing an A/D converted video signal in synchronism with a timing for the first reset signal, and by reading the A/D converted video signal in synchronism with a timing for the second reset signal. CONSTITUTION:Video signal 1 to be delayed is converted 6 into a digital signal and a vertical synchronous signal is separated from the video signal 1 by a vertical synchronous signal separating circuit 2, a write reset signal WR to memory 13 is generated 7, and the 4FSC clock that is supplied from a burst lock clock generator 4 to the clock input terminal of memory 13 is used to write the video signal 1 in memory 13 starting from the head of the memory 13. Further, a reset signal generated based on the vertical synchronous signal that is obtained by making video signal 2 to pass through synchronous separating circuit 3 is read in synchronism with the clock 4FSC' locked to the burst of the video signal 2 passed through a theta delay circuit 9. With this configuration, the image signal synchronizing circuit 1 which in able to record two programs at a time can be realized by using a relatively simple circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal synchronizing circuit, and more particularly to a video signal synchronizing circuit suitable for field synchronization of video signals in a home VTR capable of simultaneously recording two channels (two programs).

[0002]

2. Description of the Related Art Although it is convenient for a VTR to record an absent TV program by timer recording, two VTRs are required when it is desired to record two TV programs at the same time. Further, it becomes more convenient if two programs can be recorded by one VTR. However, such a conventional example has not been realized yet, and there was no circuit for synchronizing the video signals of the respective programs. Slightly, the frame synchronizer is a conventional example that is close in terms of function. In addition, an AV unit (VSX-X919) that records two programs alternately for each field in a VTR and uses a field skip for reproduction has been released by a domestic AV device manufacturer.

[0003]

The frame synchronizer has a large circuit scale and a high cost. Further, the AV unit (VSX-X919) is similar in function to the circuit of the present invention in that it is synchronized on a field-by-field basis, but since it thins out every other field, the configuration is quite different and the image quality deteriorates. There is a drawback that. Therefore,
It has been desired to realize a VTR (video signal synchronization circuit) capable of recording two programs at the same time with one device without changing the current VTR standard.

[0004]

According to the video signal synchronizing circuit of the present invention, a second video signal which is not synchronized with a first video signal serving as a reference is provided with a certain time difference between the first video signal and the first video signal. In a video signal synchronizing circuit for synchronizing with a signal, an A / D converter for converting a first video signal into a digital signal in a state of a composite signal, and first and second separating a sync signal from each video signal. And a first and second clock generator for generating clock signals respectively synchronized with the color subcarriers of these video signals,
Necessary for synchronization with first and second reset signal generation circuits that generate first and second reset signals based on the first and second clock signals and the first and second synchronization signals, respectively Delay circuit for delaying the time slightly longer than the delay time, and a second reset signal that has passed through the delay circuit while temporarily storing the A / D converted video signal at the timing of the first reset signal. The above problem is solved by including the memory for reading the video signal temporarily stored at the timing.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before explaining the video signal synchronizing circuit of the present invention, a general two-head type VTR such as a home VTR is described.
Then, the principle and method of realizing the above-mentioned function (function of simultaneously recording two programs by one unit) will be briefly described.

Two pairs of reverse azimuth magnetic heads H _A1 , H _A2 and H _B1 , H _B2 as shown in FIG. 2 are attached to the circumferential surface of the drum D, and a recording video signal is supplied to each of them. Two programs (video signals) can be recorded simultaneously by running the tape at a pitch that is at least twice the head recording width. However, since the two video signals are sent independently, their frequencies and phases are naturally different. Therefore, if the two video signals are supplied to the magnetic heads H _A1 , H _A2 and H _B1 , H _B2 as they are, at least one video signal causes skew distortion on the screen due to head switching switching during reproduction.

Therefore, it is necessary to apply a VTR servo to one of the video signals and match the other video signal with the servo. To match the servo, the video signal can be delayed appropriately. To explain specifically,
The video signal 2 serving as a servo reference is supplied to a pair of magnetic heads H _A1 and H _A2 mounted on the drum D as shown in FIG. 2, and a pair of magnetic heads H _B1 differing in angle by θ ° from this. , H _B2 is supplied with the video signal 1 and recorded on the magnetic tape T in the manner as shown in FIG. In this FIG.
A _1, A _r and B _1, B _r are recording tracks formed by the magnetic heads H _A1 , H _A2 and H _B1 , H _B2 , respectively.

At this time, the video signal 1 is recorded later than the video signal 2 by θ / (180 × 60) seconds, so that the switching switching of the head enters the vertical blanking of the video signal, and the skew distortion is generated. Will not do. Since the phase difference between the video signal 1 and the video signal 2 at the time of input to the VTR is indefinite, it is necessary to constantly monitor the phase difference. However, the video signal 1 has a maximum delay of 1 field (1/60 second). Need.

A specific embodiment of the video signal synchronizing circuit of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of a video signal synchronizing circuit 1 of the present invention.
Is a vertical sync signal separation circuit, 4 and 5 are burst lock clock generators (hereinafter also simply referred to as “clock generators”), 6 is an A / D converter, 7 and 8 are reset signal generation circuits, and 9 is a θ delay circuit , 11 and 12 are frequency dividers, 13 is a delay memory, and 14 is a D / A converter. The operation timing of the signal in each of these constituent circuits is shown in the timing chart of FIG.

Next, the function of the video signal synchronizing circuit 1 of the present invention will be described with reference to FIG. First, the video signal 1 to be delayed (see FIG. 4 (A)) is converted into a digital signal by the A / D converter 6 and is also supplied to the vertical sync signal separation circuit (hereinafter also simply referred to as “sync separation circuit”) 2. Then, the vertical sync signal of the video signal 1 (see FIG. 4 (C)) is separated, the write reset signal (WR) of the memory 13 is generated from this vertical sync signal, and the clock input of the memory 13 is input from the clock generator 4. The video signal 1 is written from the beginning of the memory 13 by the 4Fsc clock supplied to the terminal WC.

Next, a vertical synchronizing signal obtained by passing the video signal 2 (see FIG. 4B) through the sync separation circuit 3 (FIG. 4D).
The reset signal generated by the reset signal generation circuit 8 is locked by the θ delay circuit 9 to the burst of the video signal 2 supplied to the RC terminal of the memory 13 with a delay of the mounting angle θ °. It is read in synchronization with the clock 4Fsc '{see FIG. 4 (E)}. The burst lock clock generator 4 (, 5) generates the frequency Fsc (Fsc ') of the color burst signal included in the video signal 1 (, 2) (4Fsc (4Fsc in this embodiment).
It is a circuit that generates a clock signal synchronized with ')}. Specifically, it is configured by using a color decoder IC (M51271 or the like) or a blocking oscillator or the like.

By the way, since the video signal 1 is simply delayed, the composite signal can be converted into a digital signal as it is. Therefore, a color signal decoder, color A / D converter, and D / A converter are not required. However, if the continuity of the delayed color subcarrier of the signal is not maintained, the decoder of the color signal may malfunction at the discontinuity point and the color may be lost. Therefore, the memory 13
In the generation of the reset signal for, the reset is applied only in the color subcarrier period.

Specifically, the reset signal generation circuit 7 (8)
Is configured as shown in FIG. FF16 and 17 in FIG. 5 are D
Type flip-flop, 18 and 19 are AND gates,
Reference numerals 21 and 22 are inverters. The operation of the reset signal generation circuit 7 will be described with reference to the reset signal generation timing chart of FIG. First, the sync separation circuit 2 is operated with the clock synchronized with the subcarrier {Fsc, see FIG. 6 (E)}.
The vertical sync signal from is latched by FF (flip circuit) 16 and a reset signal is generated from this falling edge, and a clock for memory writing (4Fs in this case).
c, see FIG. 6 (E)}.
As a result, the head address 0 of the memory 13 is always written from the rising phase of the subcarrier.

Next, the reset signal for reading is also synchronized with the subcarrier of the read signal and the reset signal is generated by the reset signal generating circuit 8 in the same manner as described above. This allows
The last reading from the memory 13 is always immediately before the rising edge of the subcarrier, and the subcarrier is continuous. In addition, as a matter of course, the delay of θ ° must also be an integral multiple of the period of the subcarrier.

Since the delay so that the continuity of the subcarriers is maintained is not an accurate fixed delay, the luminance signal varies in the range of 0 to 280 nsec in each field. become. However, in a domestic VTR, the continuity of the luminance signal is lost due to the expansion and contraction of the tape T at the time of reproduction and the compatible reproduction, so this change does not pose a problem.

In the above description, the image generating memory is used as the memory 13 constituting the circuit 1 of the present invention, so the address generating circuit is omitted, but a general-purpose memory is used, and this memory is further used. It may be configured by providing an address generation circuit for the. Further, although the subcarrier frequency 4Fsc which is 4 times as high as the clock is used, the frequency is not limited to this, and any frequency other than 4 times as long as it is an integral multiple of Fsc, for example 3Fsc may be used.

The video signal synchronizing circuit 1 of the present invention is connected to the VT.
When applied to R, the audio signal accompanying each video signal must also be recorded for two programs. As the simplest example of the recording method, there is a method of performing monaural recording on each of two tracks with a fixed head. In addition, in the so-called HiFi VTR specification which also includes a 2ch. (Channel) rotary head for audio, the audio of each program may be distributed to these two fixed heads and two rotary heads and recorded in stereo respectively. good.

The VTR having such a function is used for TV program 2ch. In addition to simultaneous recording, new applications will be developed by combining with two video cameras. For example, two video cameras are installed apart from each other by the distance between the left and right eyes of a human, and the respective images are placed on the left and right ch. If the viewer's left eye sees the left TV screen and the right eye sees the right TV screen at the same time, the stereoscopic images can be combined in the head, Without using simple glasses
You can enjoy more realistic color images.

[0019]

Since the video signal synchronizing circuit of the present invention is constructed as described above, it has the excellent feature that it can be constructed with the minimum required memory and can be realized with a relatively simple circuit because perfect synchronization is not performed. is there. Furthermore, if the circuit of the present invention is applied to a VTR, 2 ch. It has the effect of developing various excellent and interesting applications, including simultaneous recording.

[Brief description of drawings]

FIG. 1 is a block system diagram showing an embodiment of a video signal synchronizing circuit of the present invention.

FIG. 2 is a rotary head mounting view of a VTR to which the circuit of the present invention can be applied.

FIG. 3 is a track pattern diagram formed on a magnetic tape when the circuit of the present invention is applied to a VTR.

FIG. 4 is a timing chart for explaining the operation of the circuit of the present invention.

FIG. 5 is a circuit diagram showing a configuration example of a reset signal generation circuit that constitutes the circuit of the present invention.

FIG. 6 is a timing chart for explaining the operation of the reset signal generation circuit.

[Explanation of symbols]

1 Video signal synchronization circuit 2,3 Vertical sync signal separation circuit 4, 5 Burst lock clock generator 6 A / D converter 7,8 Reset signal generation circuit 9 θ delay circuit 11,12 frequency divider 13 memory 14 D / A converter 16,17 FF (flip-flop circuit) 18, 19 AND gate 21,22 inverter T magnetic tape

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI Technical display location H04N 9/80 C 9185-5C 9/89 Z 9185-5C

Claims (3)

[Claims] 1. A video signal synchronizing circuit for synchronizing a second video signal, which is not synchronized with the first video signal as a reference, with the first video signal with a certain time difference. And an A / D converter for converting the first video signal into a digital signal in the state of a composite signal, and a first and a second for separating a synchronization signal from the first and second video signals, respectively. A synchronization signal separation circuit, first and second clock generators for generating clock signals respectively synchronized with the color subcarriers of the first and second video signals, the first and second clock signals and the first and second clock signals. First and second
First and second reset signal generation circuits that generate the first and second reset signals based on the respective synchronization signals, and a delay time slightly longer than the delay time required for the synchronization. A delay circuit and the A / D converted video signal are temporarily stored at the timing of the first reset signal, and the temporarily stored video signal is read at the timing of the second reset signal that has passed through the delay circuit. A video signal synchronizing circuit characterized by comprising a memory for outputting. 2. The video signal synchronizing circuit according to claim 1, wherein the constant time difference is substantially the same as the time difference resulting from the mounting angle difference between the two sets of video heads in the rotary head type VTR. 3. The first video signal serving as a reference is not completely synchronized with the second video signal, but is synchronized with each cycle of the color signal subcarrier of the video signal. Video signal synchronization circuit.