JPH05226665A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To control a tunnel current in the band to band tunnel phenomenon by setting equally a potential of a substrate to a source potential in such a case that the required potential is applied to the source. CONSTITUTION:In a semiconductor storage device, an N well 9 consisting of am impurities of the type inverted from the impurities implanted to a substrate 1 is formed, a P well 8 consisting of an impurities of the type same as the impurities implanted to the substrate 1 is formed within the N well 9, and the source is electrically connected to the N well 9 and P well 8. In this case, the potential of the P well 8 and N well 9 is equalized to the source potential. Therefore, program and readout operation are concerned, a transistor does become conductive since the source potential becomes 0V. Even in the deleting mode, a voltage as high as 12V is applied to the source 4 in the same manner, but the P well 8 is also charged to the same potential. Therefore, a potential between the source and substrate becomes 0V, thus suppressing generation of the band to band phenomenon.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, it is a nonvolatile memory device which is suitable for use in the field of FLASH memory or the like and which can electrically write and erase predetermined data. The present invention relates to a semiconductor memory device. recent years,
As a nonvolatile semiconductor memory device, for example, FALSH
Many semiconductor memory devices called memories have been developed.

This is a non-volatile semiconductor memory device in which data can be electrically written in a memory and the written data can be electrically erased collectively.
However, the FLASH memory has the disadvantage that the erasing characteristic at the time of erasing data changes in addition to its excellent advantage. Therefore, in order to take advantage of the excellent features of the FLASH memory, a FALASH memory having a small change in erase characteristic is required.

[0003]

2. Description of the Related Art As a conventional semiconductor memory device of this type, for example, there is one shown in FIG. In the figure, 1 is a P-type silicon substrate (hereinafter simply referred to as a substrate), 2 is a floating gate made of polysilicon (hereinafter, FG).
3 is a control gate made of polysilicon and capacitively coupled to FG2 (hereinafter abbreviated as CG), 4 is an N-type region source, 5 is an N-type region drain, and 6 is a thickness. tunnel oxide film but made of SiO ₂ of about 100 Å, 7 is an oxidation film composed of SiO ₂ having a thickness of about 250 Å. Note that S, D, G, and BG are terminals connected to the source, drain, gate, and substrate, respectively.

In the above configuration, first, in the initial state, the terminal BG is connected to 0V, so that the charge of FG2 is 0. Hereinafter, this state is defined as information "1". When the substrate 1 and the source 4 are set to 0 V and the voltage of 12 V is applied to the CG 3 and the voltage of 6 V is applied to the drain 5 in the state of the information “1”, so-called avalanche breakdown occurs and high-energy electrons are generated in the vicinity of the drain 5. And a large amount of holes are generated, and some of these high-energy electrons cross the tunnel oxide film 6 and are captured by the FG 2 to store data.

In this state, the substrate 1 and the source 4 are 0
Even if the voltage applied to the CG3 is changed to 5V and the voltage applied to the drain 5 is changed to 1V, the FG2 is
For example, since it has a low value such as -2V,
The transistor does not become conductive. Hereinafter, this state is defined as information “0”. Here, the substrate 1 and CG3 are 0
When the drain 5 is set to V and the drain 5 is opened and a high potential voltage of 12 V is applied to the source 4, a phenomenon called a so-called tunnel phenomenon occurs,
Electrons tunnel from FG2 to source 4 and pass to FG
2 charge is reduced.

That is, by adjusting the time required for the tunnel, the electric charge of FG2 can be made almost zero, so that the data is erased. That is,
The memory cell of the FLASH memory changes from information "1" to information "0" due to the avalanche breakdown. Hereinafter, this is called a program. Further, the memory cell changes from information "0" to information "1" due to the tunnel phenomenon.
Hereinafter, this is called erasure.

That is, in the FLASH memory, all memory cells are set to information "1" by erasing, and required information is stored by programming a predetermined memory cell. On the other hand, to read the stored information, the drain 5 has 1 V and the CG 3 has 5 V.
It is performed by applying V. Specifically, the drain current flows in the memory cell of information “1”, and the drain current does not flow in the memory cell of information “0”.
The value information is read out.

[0008]

However, in such a conventional semiconductor memory device, since the memory is erased by utilizing the tunnel phenomenon, a high energy electron and a positive electron are erased at the time of erasing. A hole is generated, a part of the hole is trapped in the tunnel oxide film 6, and an F
There is a problem that the electric field between G2 and the source 4 is weakened and the erase characteristic is changed.

This will be described with reference to FIG. The generation of these high-energy electrons and holes is caused by a phenomenon called a BAND TO BAND tunnel, in which electrons and holes tunnel and appear on the source and the substrate, as shown in the figure. In addition, it is strongly accelerated by a high-voltage electric field to obtain high energy. Then, as shown in the figure, the holes are drawn into the tunnel oxide film 6 by the electric field created by FG2.

This is the cause of changing the erase characteristic. [Purpose] Therefore, the present invention provides a FLASH memory,
It is an object of the present invention to provide a semiconductor memory device that suppresses a phenomenon called a BAND TO BAND tunnel at the time of erasing.

[0011]

In order to achieve the above object, a semiconductor memory device according to the present invention has a semiconductor substrate into which a predetermined amount of impurities are implanted, and a floating gate provided on the semiconductor substrate via an insulating film. And a control gate capable of controlling the potential of the floating gate by capacitively coupling with the floating gate, and an impurity of a type opposite to that of the impurity implanted in the semiconductor substrate at a position facing the floating gate. A semiconductor memory device comprising a plurality of MIS transistors having a source and a drain, wherein when a predetermined voltage is applied to the source, a voltage of the same level as the voltage to be applied to the source is applied to the semiconductor substrate. Is configured.

In this case, a first well made of an impurity of the opposite type to the impurity implanted in the semiconductor substrate is formed on the semiconductor substrate, and an impurity implanted in the semiconductor substrate is formed in the first well. It is preferable to form a second well made of the same type of impurities and electrically connect the source to the first well and the second well. In addition, a semiconductor substrate formed on a mother substrate with an insulating layer interposed therebetween, and having a region electrically isolated as necessary, into which a predetermined amount of impurities are injected, and an insulating film provided on the semiconductor substrate with an insulating film interposed therebetween. A floating gate to be provided, a control gate capable of controlling the potential of the floating gate by capacitively coupling with the floating gate, and a reverse gate of the impurity implanted in the semiconductor substrate at a position facing each other with the floating gate interposed therebetween. A semiconductor memory device including a plurality of MIS transistors each having a source and a drain made of an impurity of a type, wherein the source and the semiconductor substrate having the MIS transistor may be electrically connected. ..

[0013]

Operation: Considering the model shown in Fig. 5, BAND
The current generated by the phenomenon called the TO BAND tunnel has the characteristics shown in FIG. In other words, the tunnel current exponentially increases with the source voltage, and as the source voltage decreases, the tunnel current decreases, and the high-energy electrons and holes that are generated secondarily also decrease. Injection of holes is suppressed.

Therefore, in the present invention, when a predetermined voltage is applied to the source, the potential of the substrate forming the MIS transistor is made equal to the voltage to be applied to the source, so that the tunnel current can be suppressed. That is, in the FLASH memory, a phenomenon called a BAND TO BAND tunnel can be suppressed at the time of erasing.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an embodiment of a semiconductor memory device according to the present invention, and is a cross-sectional view showing the configuration of the main part of this embodiment. First,
The configuration will be described.

In FIG. 1, the same numbers as the numbers given to the conventional example shown in FIG. 3 indicate the same parts. 1 in the figure
Is a P substrate, 2 is an FG, 3 is a CG, 4 is an N-type region source, 5 is an N-type region drain, 6 is a tunnel oxide film made of SiO ₂ having a thickness of about 100 Å, 7 is a thickness of 250 Å
An oxide film made of SiO ₂ to a certain extent, 8 is a P well which is the second well, and 9 is an N well which is the first well.

That is, in this embodiment, the N well 9 and the P well 8 are sequentially formed in the substrate 1, and P
The potentials of the well 8 and the N well 9 are the same as the source potential. Therefore, since the source potential becomes 0 V in the program and read operations, the operation is the same as the conventional one, and the high potential voltage of 12 V is applied to the source 4 also in the erase operation. When a voltage of 12V is applied to the P-well 8, the P-well 8 also has the same potential, so that the potential difference between the source and the substrate becomes 0V,
The occurrence of the phenomenon called BAND TO BAND tunnel is suppressed.

This effect can be obtained by making the substrate 1 potential the same as the source potential even in the conventional memory cell configuration. However, in an actual memory element, a decoder circuit for selecting a memory or a memory cell is used. It is impossible to change the potential of the substrate 1 because there is a sense amplifier circuit that reads out the information. Further, by providing the P well 8 in the N well 9 having the same potential as in the present embodiment,
The PN junction formed by the N-type semiconductor of the source 4 and the P-type semiconductor of the P-well 8 and the PN junction formed by the N-type semiconductor of the N-well 9 and the P-type semiconductor of the P-well 8 are both forward. Since it is not biased, the PN junction formed by the N well 9 and the P substrate 1 is fixed to 0 V or 12 V for the N well 9 and 0 V for the P substrate 1, so that it is not biased in the forward direction either.

FIG. 2 is a diagram showing another embodiment of the semiconductor memory device according to the present invention, and is a cross-sectional view showing the structure of the main part of this embodiment. First, the configuration will be described. In FIG. 2, the same numbers as the numbers given to the embodiment shown in FIG. 1 indicate the same parts.

In the figure, 2 is FG, 3 is CG, 4 is the source of the N-type region, 5 is the drain of the N-type region, and 6 is 100 in thickness.
Å About ₂ tunnel oxide film made of SiO ₂ , 7 is 2
An oxide film made of SiO _{2 of} about 50 Å, 10 is an insulating layer,
Reference numeral 11 is a mother substrate, 12 is a P-type well region, and 13 is an etching region in the P-type well region. That is, in this embodiment, the FLASH memory is replaced with an SOI (Silicon On Ins
The etching area 13
Electrically insulates the memory cell from other parts,
Separated.

Also in this case, the P-type region in which the memory cell is provided is set to the same potential as the source 4, and the above-mentioned BAND
The occurrence of the phenomenon called TO BAND tunnel is suppressed.
As described above, in the present embodiment, when a predetermined voltage is applied to the source, the potential of the substrate portion and the source potential are made the same, so that the tunnel current in a phenomenon called a BAND TO BAND tunnel can be suppressed.

Therefore, in the FLASH memory,
It is possible to prevent the phenomenon called BAND TO BAND tunnel when erasing.

[0023]

According to the present invention, the tunnel current in the BAND TO BAND tunnel phenomenon can be suppressed by making the potential of the substrate portion the same as the source potential when a predetermined voltage is applied to the source. Therefore, in the FLASH memory, a phenomenon called a BAND TO BAND tunnel can be prevented at the time of erasing.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a configuration of a main part of an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the configuration of the main part of another embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a memory cell of a conventional FLASH memory.

FIG. 4 is a schematic diagram for explaining a BAND TO BAND tunnel phenomenon.

FIG. 5 is a model for explaining a tunnel current due to a BAND TO BAND tunnel phenomenon.

FIG. 6 is a graph for explaining a tunnel current due to a BAND TO BAND tunnel phenomenon.

[Explanation of symbols]

 1 Silicon substrate (P substrate) 2 Floating gate 3 Control gate 4 Source 5 Drain 6 Tunnel oxide film 7 Oxide film 8 P well (2nd well) 9 N well (1st well) S terminal D terminal G terminal BG terminal

Claims (3)

[Claims] 1. A semiconductor substrate formed by implanting a predetermined amount of impurities, a floating gate provided on the semiconductor substrate via an insulating film, and a potential of the floating gate by capacitively coupling with the floating gate. A semiconductor memory device including a plurality of MIS transistors each having a controllable control gate, and a source and a drain made of an impurity of a type opposite to that of the impurity implanted in the semiconductor substrate at positions facing each other with the floating gate interposed therebetween. A semiconductor memory device, wherein when a predetermined voltage is applied to the source, a voltage of the same level as the voltage to be applied to the source is applied to the semiconductor substrate. 2. A semiconductor substrate formed by implanting a predetermined amount of impurities, a floating gate provided on the semiconductor substrate with an insulating film interposed therebetween, and a potential of the floating gate is controlled by capacitively coupling with the floating gate. A semiconductor memory device including a plurality of MIS transistors each having a controllable control gate, and a source and a drain made of an impurity of a type opposite to that of the impurity implanted in the semiconductor substrate at positions facing each other with the floating gate interposed therebetween. And forming a first well on the semiconductor substrate, the first well being made of an impurity of the opposite type to the impurities injected into the semiconductor substrate, and having the same type as the impurities injected into the semiconductor substrate in the first well. Forming a second well made of impurities, and electrically connecting the source to the first well and the second well. The semiconductor memory device which is characterized in that. 3. A semiconductor substrate formed on a mother substrate with an insulating layer interposed therebetween, and a predetermined amount of impurities having an electrically isolated region is implanted as necessary, and an insulating film on the semiconductor substrate. An impurity implanted in the semiconductor substrate at a position facing the floating gate, a control gate capable of controlling the potential of the floating gate by capacitively coupling with the floating gate, and a position facing the floating gate. A semiconductor memory device having a plurality of MIS transistors each having a source and a drain made of impurities of a type opposite to the above, wherein the source and a semiconductor substrate on which the MIS transistor is present are electrically connected. And semiconductor memory device.