JPH05226374A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a rapid operating transistor having the characteristics of the wide operational range and the high gain. CONSTITUTION:This transistor has a three layer structured channel layer wherein undoped GaInAs layers 130a, 130b are arranged above and below a GaAs layer 140 including at least one delta doped layer (n type). Next, a cap layer 150, a buffer layer 120 are provided abobe and below the three layer structure on a substrate 110. Finally, a gate electrode 340 as well as a source region 350a, a drain region 350b, a source electrode 360 and a drain electrode 370 are self-matchingly formed with the gate electrode 340.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor, and more particularly to a low noise and high speed operation heterojunction field effect transistor and a monolithic integrated circuit (MMIC) for microwaves using the FET.

[0002]

2. Description of the Related Art A heterojunction field effect transistor (or a high electron mobility transistor (HEMT)) using a selectively doped heterojunction has been proposed as a transistor operating at low speed with low noise. FIG. 4 shows the structure of a typical AlGaAs / GaAs high electron mobility transistor. Its structure is as follows.

A non-doped GaAs layer 210 is formed on the semi-insulating GaAs substrate 110.
AlGaA, which has a smaller electron affinity than GaAs on 10
An s layer (non-doped AlGaAs spacer layer 220) is formed. The AlGaAs layer is non-doped AlGa
It is composed of an As spacer layer 220 and an AlGaAs layer 230 doped with an n-type dopant (an element such as Si or Se), and these are formed on the GaAs 210. A gate electrode 250 is provided on the AlGaAs layer, and the source electrode 270 and the drain electrode 2 are sandwiched between the gate electrode 250 and the Si-GaAs contact layer 260.
And 80 are provided. This electrode structure is called a recess type structure because the gate electrode is at the bottom of the groove (recess), and is a general gate electrode structure in HEMT. With such a structure, Ga at the AlGaAs / GaAs interface is
A two-dimensional electron gas 240 is formed on the As side, and this serves as a channel (current path) between the drain and the source. Then, the concentration of the two-dimensional electron gas 240 is controlled by the gate electrode 250, and the current between the source electrode 270 and the drain electrode 280 is modulated.

On the other hand, as a transistor having a structure other than HEMT and operating at a low noise and at a high speed, a pulse-doped M is used in the Institute of Electronics, Information and Communication Engineers ED89-152, etc.
ESFETs have been reported. Pulse dope MESFE
T uses a Si pulse-doped GaAs layer for its channel and has a structure as shown in FIG. Its structure is as follows.

On a semi-insulating GaAs substrate 110, carrier conductivity type p-type (up to 5 × 10 ¹⁵ cm ⁻³ ) non-doped G is used.
The aAs buffer layer 310 is formed, and Si-doped GaA is formed.
The s (4 × 10 ¹⁸ cm ⁻³ ) 320 has a thickness of 100 Å. Si-doped GaAs channel layer 32
0, the carrier conductivity type is n-type (up to 1 × 10 ¹⁵ c
m ⁻³ ) non-doped GaAs cap layer 330 is formed. On such a pulse-doped structure, the gate electrode 340, the n ⁺ ion implantation layers 350a and 350b self-aligned with the gate electrode, and the source electrode 36 are formed.
0, the drain electrode 370 is formed. This electrode structure is called a planar structure because the gate electrode is flat (planar).

[0006]

FIG. 3 shows AlGaA.
s / GaAs HEMT and pulse-doped MESFET
An example of the characteristics of is shown. This figure shows that the gate length is 0.
Transfer conductance (g when using 3 μm element)
It shows the gate bias dependence of m). In the pulse-doped MESFET, the transfer conductance gm is a terrace-like profile with respect to the gate bias (broken line).
And has a characteristic that the change of the transfer conductance gm is small even if the bias point is slightly deviated, but the value of the transfer conductance gm itself is lower than that of the HEMT. Also,
The steepness of rising of the transfer conductance gm in the gate bias near the threshold (Vth), which is important as a low noise element, is inferior to that of the HEMT.

On the other hand, HEMT has a transfer conductance g
Although the rise of m is steep and the maximum value is also high, it has a peak-shaped profile (dashed line) with respect to the gate bias, and if the bias point is slightly deviated, the transfer conductance gm is greatly reduced. The transfer conductance gm of the HEMT decreases on the shallow side of the gate bias because a part of the two-dimensional electrons is AlGa whose electron traveling speed is low.
This is due to a phenomenon called a real space transition that transits to the As layer. This peak-shaped profile of the transfer conductance gm causes a disadvantage that a design margin is small and the yield of the integrated circuit is low when the integrated circuit (IC) is manufactured using the HEMT. Further, in the HEMT structure, since the steepness of the AlGaAs / GaAs interface is important, the planar type gate electrode by self-aligned ion implantation is not adopted. That is, in order to activate the ion-implanted Si, it is necessary to anneal at a high temperature. In this annealing step, Al in the AlGaAs layer is changed to GaA.
This is because the mobility of electrons and the saturation speed are significantly reduced when they diffuse into the s layer. Therefore, the gate electrode in the HEMT is generally of the recess type, and variations in the depth of the recess in the etching process when forming the recess are
It becomes the variation of Vth. Thus, in terms of process margin as well, the conventional HEMT is not always suitable as a device that constitutes an integrated circuit.

In view of the above inconveniences, the present invention has been made, and provides a high-speed transistor having the features of a pulse-doped MESFET (wide operating range) and HEMT (high gain).

[0009]

In order to solve the above-mentioned problems, the semiconductor device of the present invention is a semiconductor device in which the current flowing in a channel (current path) between a drain and a source is controlled by a voltage applied to a gate electrode. (For example, a field effect transistor (FET), a monolithic integrated circuit including an FET), and at least one including an n-type dopant (eg, Si, Se, S, Te, etc.)
GaAs layer composed of two two-dimensional layers and non-doped layers sandwiching the two-dimensional layers (layers to which no dopant is added, including the case where impurities are mixed) and the GaA
It has a channel layer composed of a non-doped GaInAs layer sandwiching the s layer and is electrically connected to the gate electrode.
A cap layer made of a non-doped semiconductor having a band gap larger than InAs (for example, GaAs, GaInP, AlGaAs, etc.) and a buffer layer made of a non-doped semiconductor having a band gap larger than GaInAs were provided on both sides of the channel layer. Is characterized by.

The composition of In of the non-doped GaInAs layer may have a continuous or stepwise change.

It may be characterized in that it has a drain region and a source region formed by introducing impurities to the vicinity of both ends of the channel.

[0012]

In the semiconductor device of the present invention, the two-dimensional electron gas is formed in the vicinity of the GaAs layer containing at least one two-dimensional layer containing the n-type dopant and the GaInAs hetero interface immediately below. Since the electrons of the two-dimensional electron gas have a very high saturation velocity, they operate at a very high speed. In addition, GaIn
A heterojunction is formed by the As layer and a buffer layer made of a semiconductor having a band gap larger than that of GaInAs, and a conduction band energy barrier is formed at this hetero interface.
Therefore, the electrons of the two-dimensional electron gas are less likely to flow into the buffer layer, and the transfer conductance gm rises sharply in the gate bias near the threshold voltage V _th .

Further, since the channel layer has a laminated structure of a two-dimensional layer containing an n-type dopant and a non-doped GaAs layer, when a gate bias (positive voltage bias) for increasing drain current is applied. Even if some of the two-dimensional electrons make a real space transition and jump into the GaAs layer, the conventional S
As compared with HEMTs using an i-doped AlGaAs layer, lowering of electron mobility and saturation speed can be suppressed. Further, in the quantum well of the GaInAs layer on the GaAs layer, Ga
Since electrons that have transited to the real space in the As layer fall into a two-dimensional electron gas, a sharp decrease in the transfer conductance gm on the positive voltage side of the gate bias, which is peculiar to the conventional HEMT, is prevented.

[0014]

Embodiments of the present invention will be described with reference to the drawings.
Description of the same or equivalent elements as those of the above-mentioned conventional example will be simplified or omitted. Further, “doped” means that impurities are added, and “non-doped” means that impurities are not added.

FIG. 1 shows an embodiment in which the present invention is applied to a field effect transistor (FET). The feature of this transistor is that undoped Ga is formed above and below a GaAs layer 140 including at least one delta-doped layer (n-type).
This is to have a channel layer having a three-layer structure in which the InAs layers 130a and 130b are arranged. Here, the delta-doped layer is a thin layer in which impurities are planarly doped, and has a stepwise impurity distribution with respect to the upper and lower layers.

Above and below the channel layer of this three-layer structure (above and below the non-doped GaInAs layers 130a and 130b),
A cap layer 150 and a buffer layer 120, which are non-doped GaAs layers, are provided and formed on the substrate 110. Then, similarly to the pulse-doped MESFET, the gate electrode 340 and the n ⁺ ion implantation layer (source region, drain region) 3 formed in self-alignment with the gate electrode 3
50a, 50b, a source electrode 360, and a drain electrode 370 are formed.

The transfer conductance g of this transistor
The m characteristic is as shown by the solid line in FIG. The rise of the transfer conductance gm in the vicinity of the threshold level Vth is steeper than that of the pulse-doped MESFET, and the transfer conductance gm does not have a peak-shaped profile as in the HEMT. It can be suppressed, and the value of the transfer conductance gm is higher than that of the pulse-doped MESFET as a whole. That is, the characteristics are such that the wide operating range of the pulse-doped MESFET and the high gain of HEMT are combined. This is probably due to the following points.

This transistor uses a channel layer having a three-layer structure as a channel, and includes a GaAs layer 140 and a GaIn layer.
The interface of the As layer 130a and the cap layer 150 (GaA
s) and the interface of the GaInAs layer 130b form a two-dimensional electron gas. The electrons of the two-dimensional electron gas have a higher saturation velocity than those in the pulse-doped GaAs layer. Therefore, the response speed, that is, the operation speed is high. The current flowing between the source electrode 360 and the drain electrode 370, that is, the traveling of the electrons of the two-dimensional electron gas is controlled by controlling the band structure of this interface by the voltage applied to the gate electrode 340. This allows the above-mentioned HE
The same high speed as MT can be obtained.

The GaInAs layer 130a and the buffer layer 12
At the hetero interface with 0 (GaAs), an energy barrier is formed in the conduction band due to the difference in the band structure. Due to this energy barrier, the electrons are buffer layer 12
Since it is difficult for the gate bias to flow into 0, the transfer conductance g is near the gate bias in the vicinity of the threshold level Vth.
The rising edge of m is steep. This point causes a difference in characteristics from the above-mentioned pulse-doped MESFET.

Further, even if a part of the two-dimensional electrons of the GaInAs layer 130a make a real space transition and jump into the GaAs layer 140 at the gate bias point for increasing the drain current, that is, the bias point in which the gate bias is swung to the + side, the above-mentioned effect occurs. The mobility and saturation rate of electrons do not decrease as much as the Si-doped AlGaAs layer of HEMT. This is because the GaAs layer 140 is a GaAs layer including a layer in which impurities are delta-doped. Furthermore, GaInA is formed directly below the GaAs layer 140.
Since the s layer 130b is provided, the electrons flow into the GaInAs layer 130b, which has a low conductor potential, and become two-dimensional electrons. In this way, a sharp decrease in the transfer conductance gm peculiar to the conventional HEMT is prevented, and a wide operating range with respect to the gate bias is provided.

Further, since the gate electrode has a planar structure, it is very suitable as a transistor constituting an integrated circuit.

Next, the manufacturing process of the transistor of FIG. 1 will be described.

First, metal organic chemical vapor deposition (OMVPE)
Method) or a molecular beam epitaxy method (MBE method) or the like on the semi-insulating GaAs substrate 110, and is a carrier conductivity type p-type (up to 5 × 10 ¹⁵ cm ⁻³ ) non-doped GaAs.
The buffer layer 120 made of 10000 angstrom is formed. Then, on the buffer layer 120, a GaInAs layer 130a made of non-doped Ga _0.72 In _0.18 As whose carrier conductivity type is n-type (up to 5 × 10 ¹⁵ cm ⁻³ ).
To 80 angstroms. Subsequently, non-doped G in which the conductivity type of the carrier is n-type (up to 1 × 10 ¹⁵ cm ⁻³ ).
The aAs layer 140a ₁ is formed to 25 angstroms.
(FIG. 2 (a)).

On the non-doped GaAs layer 140a ₁ , S
A delta-doped layer 140b ₁ is formed by delta-doping n-type impurities such as i and Se. Subsequently, a non-doped GaAs layer 140a ₂ of carrier conductivity type n type (˜1 × 10 ¹⁵ cm ⁻³ ) is formed in a thickness of 25 Å. Similar steps are repeated to form the delta-doped layer 140b ₂ and the non-doped GaAs layer 140a ₃ . Thereafter, an undoped Ga _0.80 an In _0.20 of the non-doped GaAs layer 140a ₃ conductive carrier is n-type on (~1 × 10 ¹⁵ cm ^-3)
A GaInAs layer 130b made of As is formed to 100 angstrom. Subsequently, a cap layer 150 made of non-doped GaAs whose carrier conductivity type is n type (up to 1 × 10 ¹⁵ cm ⁻³ ) is formed in a thickness of 300 Å (FIG. 2B).

The gate electrode 3 is formed on the epi structure of FIG.
40 is formed. Then, the n ⁺ ion implantation layers (source region and drain region) 350a and 350b and the source electrode 36
0, the drain electrode 370 is formed in self alignment with the gate electrode 340 (self alignment), and the transistor is completed (FIG. 2C).

In this manufacturing process, since the compound semiconductor containing Al is not used as the material of the channel even in the annealing process after the ion implantation, the deterioration of the electron mobility and the saturation speed is suppressed.

As described above, a transistor having the characteristics of HEMT and pulse-doped MESFET can be obtained. Therefore, it is useful as a low noise element, high frequency element, or high speed element. Also,
Since it can have a shrimp structure and an electrode structure suitable for integration, it is useful when used as a transistor forming an MMIC, for example.

The present invention is not limited to the above-described embodiment, but various modifications can be made.

For example, although the cap layer and the buffer layer have been described as having a single layer structure of a non-doped GaAs layer, they have a single layer of a compound semiconductor such as AlGaAs or GaInP or a laminated structure of a combination of these compound semiconductor GaAs. Is also good.

The delta-doped layer in the channel layer can be formed in several layers so that a transistor having a desired threshold level Vth can be obtained.

The gate electrode structure is also a planar structure using self-aligned ion implantation, but it has a recess structure (FIG. 3) having a contact layer of a compound semiconductor (Si-doped GaAs layer, Si-doped GaInAs layer, etc.). You may do like 4).

Further, the GaInAs layer of the channel layer may also have a structure in which the In composition is continuously and stepwise changed in the GaInAs layer. This has the advantage that the lattice mismatch of the crystal lattice of GaAs and GaInAs is relaxed and the electron mobility is improved.

Regarding the chemical composition, GaInAs is a substance expressed by the general formula as Ga _1-x In _x As (x> 0), and AlGaAs is Al _m Ga _1-m As (m> 0).
GaInP is a substance expressed as “Ga _r In _1-r P”
A substance expressed as (r ≧ 0) can be used.

[0034]

As described above, according to the semiconductor device of the present invention, since the two-dimensional electron gas is formed in the vicinity of the hetero interface, very high speed operation is possible and the energy of the conduction band of the hetero interface is high. Transfer conductance gm due to barrier
The rising edge of can be made steep. Furthermore, Ga
Due to the band structure of the hetero interface between the As layer and the GaInAs layer, a sharp decrease in the transfer conductance gm can be prevented, and high gain and high speed operation can be obtained even with a wide gate bias.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment.

FIG. 2 is a manufacturing process diagram of the embodiment.

FIG. 3 is a characteristic diagram of an example and a conventional example.

FIG. 4 is a configuration diagram of a general HEMT.

FIG. 5 is a configuration diagram of a general pulse-doped MESFET.

[Explanation of symbols]

110 ... Substrate 120 ... Buffer layer, 130a, 130b
... GaInAs layer, 140 ... GaAs layer, 150 ... Cap layer, 350a, b ... n ⁺ ion implantation layer.

Claims (3)

[Claims] 1. A semiconductor device, wherein a current flowing in a drain-source channel is controlled by a voltage applied to a gate electrode, wherein at least one two-dimensional layer containing an n-type dopant and the two-dimensional layer. GaAs layers composed of non-doped layers sandwiching the layers, and non-doped Ga sandwiching the GaAs layers
A channel layer formed of an InAs layer, electrically connected to the gate electrode, and made of a non-doped semiconductor having a band gap larger than GaInAs; and a non-doped semiconductor having a band gap larger than GaInAs. A semiconductor device comprising a buffer layer on both sides of the channel layer. 2. The semiconductor device according to claim 1, wherein the composition of In in the non-doped GaInAs layer has a continuous or stepwise change. 3. The semiconductor device according to claim 1, further comprising a drain region and a source region formed by introducing impurities up to the vicinity of both ends of the channel.