JPH05224999A - Runaway processor - Google Patents

Abstract

PURPOSE:To provide a runaway processor which can deal with detection of runaways of plural CPUs with a single timer for simplification of a circuit and for deletion of a timer program and then, can extremely reduce the software developing burden. CONSTITUTION:A dual port RAM 3 is provided between the CPU1 and 2 which transmit the data to each other. Then, the RAM 3 outputs an interruption signal to the CPU2 when the data to be transferred to the CPU2 from the CPU1 are written and then, stops the output of the interruption signal when the CPU2 reads out the data. Meanwhile, a watchdog timer circuit 6 fetches the interruption signal from the RAM3 outputs a runaway detection signal if the output of the interruption signal is not stopped even after a prescribed time to prevent the runaway of the CPU 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a runaway processing device for preventing runaway of a microcomputer.

[0002]

2. Description of the Related Art A technique called a watchdog timer is widely adopted as a technical means for preventing a runaway of a microcomputer. This is to detect a runaway by outputting a signal of a constant cycle to an output port of a microcomputer and monitoring this signal with a monitoring circuit.

Various technical means for performing runaway processing by software have also been proposed. For example, JP-A-2-2632
As described in No. 43, an instruction for jumping to a specific address is written in an unused area of the memory, and when the instruction is jumped to a specific address, a processing program for computer runaway is written there. There are a method of fetching a program and executing a runaway process, and a method of rewriting the contents of the stack register each time the main loop completes to prevent a runaway, as described in JP-A-2-259936.

[0004]

However, in the runaway monitoring of the microcomputer by the watchdog timer, since the program for accessing the watchdog timer is inserted in the program within a certain time, the program is operating normally. Moreover, the insertion position of the program for the watchdog timer must be adjusted so that the watchdog timer does not detect an abnormality, and time is spent for work unrelated to the original program creation.

In a system having a plurality of CPUs,
Since the watchdog timer signals are output at different timings for each CPU, there is a problem that a watchdog timer is required for each CPU and the circuit becomes complicated.

Further, in software runaway processing, since the operation of the microcomputer and the runaway processing are not independent, runaway that cannot be dealt with may occur.
It was insufficient as a measure against runaway.

The present invention has been made in view of the above-mentioned circumstances, and one watchdog timer is used for a plurality of CPUs.
Provides a runaway processing device that can deal with the detection of runaway and simplify the circuit, can delete the program for the watchdog timer, does not need to adjust the insertion position of the program, and can significantly reduce the burden of software development The purpose is to do.

[0008]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a runaway processing device between a plurality of CPUs for data transmission.
A dual port RAM, which outputs an interrupt signal to the other CPU when data to be transmitted to the PU is written, and stops the output of the interrupt signal by the other CPU reading the data, and the dual port RAM And a watchdog timer circuit for stopping the runaway of the other CPU that has runaway by outputting the runaway detection signal when the interrupt signal does not stop even if a predetermined time has elapsed. In addition to the above configuration, a memory in which a processing program at the time of a runaway is stored, and a return address to the main routine after the completion of the interrupt routine is stored in each of the CPUs provided for each interrupt routine and accessed. Check the existing stack and execute the above processing program if it cannot return to the main routine. It has a structure provided with the means.

[0009]

According to the present invention in which the above means are taken, the data transmission between the CPUs is performed through the dual port RAM, and when the data transmission is performed from one CPU to another CPU, The data transmitted from the dual port RAM is once written in the dual port RAM, and accordingly, an interrupt signal is output from the dual port RAM to the destination CPU and the watchdog timer circuit. Destination C
When the PU receives the interrupt signal, it reads the data written in the dual port RAM and
The AM stops the output of the interrupt signal when the destination CPU reads the data. On the other hand, in the watchdog timer circuit, when the interrupt signal is input, the timer is started, and when the output of the interrupt signal is not stopped even after the lapse of a predetermined time, that is, the transmission destination CPU does not go to read the data. In this case, an abnormality detection signal is output and the transmission destination CPU is reset.

In the interrupt routine, the return address is traced back to check the stack to see if it can return to the main routine. If the stack cannot be returned, the runaway program is executed. As a result, even if a runaway that accepts an interrupt occurs, the runaway is surely stopped.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic configuration of a runaway processing apparatus according to an embodiment of the present invention. As shown in the figure, in this embodiment, the CPU 1 on one side and the C on the other side are used for data transmission.
PU2 is connected via dual port RAM3,
Each of the CPUs 1 and 2 is connected to an address bus and a data bus via input ports 4 and 5, respectively. The output terminal of the dual port RAM 3 that outputs an interrupt signal to the CPU 1 or 2 of the data transmission destination is connected to the input terminal of the watchdog timer circuit 6, and the output terminals that output the runaway detection signal of the watchdog timer circuit 6 are CP
It is configured to be connected to the input ports 4 and 5 of U1 and U2, respectively.

A more detailed structure of this embodiment is shown in FIG.

In this embodiment, a graphic system processor (hereinafter referred to as "G") is used as a microcomputer.
(Hereinafter referred to as "SP") and a microcomputer for controlling an external device will be described as an example.

The CPU 11 is a GSP that mainly controls the display on the display, and the CPUs 12 and 13 are CPUs that control the external equipment. An address bus and a data bus are connected to the CPUs 11 to 13, respectively.

The address bus and data bus connected to the CPU 11 include a ROM containing a program,
An IC card in which data and programs are stored and which is detachably provided, and a RAM for reading and writing data are connected. A RAM for storing programs and data is connected to the address bus and data bus connected to the CPUs 12 and 13.

Between CPU 11 and CPU 12, and CPU
Data is transmitted between the CPU 11 and the CPU 13, and the CPU 1 and the CPU 2 shown in FIG. 1 are connected to each other through the dual port RAMs 14 and 15, respectively. These dual-port RAMs 14 and 15 have two interrupt output terminals. When data is written to one address from one side, the interrupt output to the other becomes active, and when the data content of that address is read from the other, Interrupt output becomes non-active. Of the interrupt output terminals of these dual port RAMs 14 and 15, C
The interrupt output terminal on the PU 11 side is connected to the interrupt terminal of the CPU 11 via the AND circuit 16, and the CPUs 12 and 13 are connected.
The side interrupt output terminals are connected to the interrupt terminals of the CPUs 12 and 13, respectively. These dual port RAM
The interrupt output terminals 14 and 15 are further connected to the watchdog timer circuit 16.

The circuit configuration of the watchdog timer circuit 16 is shown in FIG.

The watchdog timer circuit 16 uses the interrupt output terminal on the CPU 11 side of the dual port RAM 14 as the interrupt line 1 and the interrupt output terminal on the CPU 12 side as the interrupt line 2, and the CPU 1 of the dual port RAM 15
If the interrupt output terminal on the first side is the interrupt line 3 and the interrupt output terminal on the CPU 13 side is the interrupt line 4, each of the interrupt lines 1 to 4 is a latch circuit 2 including a flip-flop.
They are connected to D inputs 1 to 24, respectively. The Q outputs of the latch circuits 21 to 24 are connected to one input terminals of the OR circuits 25 to 28, respectively, and the corresponding interrupt lines 1 to 4 are connected to the other input terminals of the OR circuits 25 to 28, respectively. There is. The output terminals of the OR circuits 25 to 28 are connected to the input terminals of the NAND circuit 29, respectively. The output terminal of the NAND circuit 29 is connected to the timer circuit 30. The output terminal of the NAND circuit 29 is connected to the other input terminal of the OR circuit 20 whose one input terminal receives the clock signal. This OR circuit 2
The 0 output is input as a clock signal to the clock terminals of the latch circuits 21 to 24.

The timer circuit 30 starts counting at the rising edge of the input signal and stops counting at the falling edge. Then, a negative pulse is output when counting a predetermined time. This predetermined time, that is, the timer setting time
It takes longer than the time from when an interrupt is input from M to when the CPU reads data and becomes inactive. The OR circuits 31 to 34 are connected in parallel to the output terminals of the timer circuit 30, and the OR circuits 31 to 34 are connected.
The outputs of the OR circuits 25 to 28 in the preceding stages are applied to the other input terminal of the. OR corresponding to interrupt lines 1 and 3
The outputs of the circuits 31 and 33 are input to the AND circuit 35, and the runaway detection signal S1 is output when the logical condition is satisfied. In addition, the runaway signal S2 is output from the OR circuit 32 corresponding to the interrupt line 2, and the O signal corresponding to the interrupt line 4 is output.
A runaway signal S3 is output from the R circuit 34.

An AND circuit 35 which outputs a runaway detection signal S1 indicating that the CPU 11 has runaway is connected to the reset terminal of the CPU 11 and the input ports built in the CPUs 12 and 13. Further, the OR circuit 32 that outputs the runaway detection signal S2 indicating that the CPU 12 has run out of control
It is connected to the input port 41 of U11 and the input port of the CPU 13. Further, an OR circuit 3 that outputs a runaway detection signal S3 indicating that the CPU 13 has runaway
Reference numeral 4 is connected to an input port 41 of the CPU 11 and an input port built in the CPU 12. Furthermore, the runaway detection signals S1 to S3 are input to the AND circuit 42, and its output terminal is connected to each interrupt input terminal of the CPUs 11 to 13. As a result, if any one of the runaway detection signals is output, the CPU 11 to 13 is interrupted.

The CPU 11 has a CPU 12 and a CPU C.
It has an output port 43 connected to the reset terminal of the PU 13. The CPU 12 and the CPU 13 have reset signals RST2 and RS output from the output port 43.
Reset by T3. Further, the CPU 12 and the CPU 13 have output terminals for outputting to the CPU 11 non-reset signals NR2 and NR3 that are not reset by the CPU 11 during the startup operation after the CPU 11 is reset.

Next, the operation of this embodiment configured as described above will be described.

During normal operation, the CPU 11 and the CPU 12
And between the CPU 11 and the CPU 13 via the dual port RAMs 14 and 15. For example, when data is transmitted from the CPU 11 to the CPU 12, the CPU 11 uses the dual port RAM 14
Write the data to the specific address of. The dual port RAM 14 in which the data is written outputs an interrupt signal to the CPU 12 and the watchdog timer circuit 16.

When this interrupt signal is output, in the watchdog timer circuit 16, the interrupt line 2 becomes low level, the NAND circuit 29 is not established, the input signal of the timer circuit 30 rises, and time counting is started. It On the other hand, when the CPU 12 receives the same interrupt signal,
The data written in the dual port RAM 14 is read. When the CPU 12 reads the data from the dual port RAM 14, the output of the interrupt signal output from the dual port RAM 14 is stopped, the interrupt signal line 2 also returns to the high level accordingly, and the NAND circuit 2
When the condition 9 is satisfied, the input signal of the timer circuit 30 falls and the counting is stopped. Therefore, the watchdog timer circuit 16 does not output the runaway detection signal S2.

On the other hand, when a runaway that does not cause an interrupt to the CPU 12 occurs, the CPU 12 does not read data from the dual port RAM 14, so that the interrupt signal remains output from the dual port RAM 14 and the watch dock When the timer circuit 30 of the timer circuit 16 finishes counting the preset time,
Output a negative pulse. As a result, both input terminals of the OR circuit 32 corresponding to the interrupt line 2 become low level,
A runaway detection signal S2 indicating that the CPU 12 has run out is output.

The runaway detection signal S2 is input to the input ports of the CPU 11 and the CPU 13 other than the CPU 12. When the CPU 11 receives the runaway detection signal S2, the reset signal R is output from its output port 43 to the CPU 12.
ST2 is output to reset the runaway CPU 12.

When the CPU 12 is reset, the CPU 11 starts up the CPU 12.

That is, while the CPU 11 resets the CPU 12, the boot program (the program for the CPU 12 to write the original program in the RAM connected via the bus) and the reset vector are written in the dual port RAM 14. After that, the reset of the CPU 12 is released. Then, the CPU 12 reads the original program from the CPU 11 into its own RAM via the dual port RAM 14, and the original program starts up on the RAM. At this time, the CPU 13
Do not send to U12.

The above-described runaway detection, reset and start-up operations are similarly performed for the CPU 13.

When the CPU 11 runs out of control, the AN of the watchdog timer circuit 16 is operated as described above.
When the runaway detection signal S1 is output from the D circuit 35, the CPU
11 is reset, and CP is sent to the CPUs 12 and 13.
Informed that U11 had runaway.

Here, when the power is normally turned on, first, C
PU11 starts up, and then the CPU is executed by the procedure described above.
12 and the CPU 13 are started up. Therefore, CP
When U11 runs out of control, it is necessary to prevent the CPU 12 and the CPU 13 from being reset when the CPU 11 starts up.

In this embodiment, the CPUs 12 and 13 use the CP
When it knows that U11 has runaway by the runaway detection signal S1, it outputs the non-reset signals NR2 and NR3 to the CPU 11. The CPU 11 judges whether or not the non-reset signals NR2 and NR3 are input to the input port 41, and if the non-reset signals NR2 and NR3 are output, the CPUs 12 and 13 are not reset.

When two or more CPUs transmit at the same time, or when the timer circuit 30 is counting, another C
When the PU transmits, the watchdog timer circuit 16 operates according to the time chart shown in FIG. In the figure, first, transmission is performed from the CPU 12 to the CPU 11, the interrupt line 1 becomes low level, and C is transmitted during the transmission.
PU11 to CPU12 and CPU13 to CP
This is a case where the transmission is performed to U11, the interrupt lines 2 and 3 are set to the low level, and the CPU 12 is out of control.

First, when the interrupt line 1 becomes low level, both input terminals of the OR circuit 25 become low level, and N
When the condition of the AND circuit 29 is not satisfied, the timer circuit 30
Input signal TP1 of rises. The timer circuit 30 starts counting at the rising edge of the input signal TP1, and the output of each of the latch circuits 21 to 24 is latched by the signal TP1 clocked through the OR circuit 20. When the interrupt line 1 rises within the timer setting time, the NAND is waited until the next clock signal rises.
Since the input signals of the circuit 29 are all at the high level, the condition is satisfied and the input signal TP1 falls. At this fall, the counting of the timer circuit 30 is stopped. At this time, the interrupt lines 2 and 3 are at the low level, so that the NAND circuit 29 rises at the next rise of the clock signal.
Is not established again, and the input signal TP of the timer circuit 30 is
1 rises and counting is started. This time, the interrupt line 2 does not rise even after the timer setting time elapses. Therefore, when the timer setting time elapses, the timer circuit 30
Outputs a negative pulse. At this time, the OR circuits 31 to 3
One input terminal of 4 is an OR corresponding to the interrupt line 2.
Since only the circuit 32 is at the low level, the OR circuit 3
The output of 2 goes low and the runaway detection signal S2 is output.

As described above, it is possible to deal with the case where two or more CPUs simultaneously transmit, or when another CPU transmits while the timer circuit 30 is counting.

Further, in the present embodiment, the processing shown in FIG. 4 is executed in order to cope with a kind of runaway that accepts an interrupt even if the runaway is caused by an infinite loop.

First, when shifting from the main loop to the interrupt loop, the stack in which the return address after the end of the interrupt routine is stored is checked. This stack check determines whether the return address can be traced back to the main routine. If it can return to the main routine, it shifts to the interrupt routine and executes interrupt processing. Further, as a result of the stack check, if it is not possible to return to the main routine, a process such as initialization is performed by jumping to a predetermined address in which an initialization program for runaway processing is stored in advance.

As described above, according to this embodiment, the CPUs 11 to 11 are
Data transmission between 13 and dual port RAM 14, 15
Via each dual port RA for data transmission
The timer of the watchdog timer circuit 16 is started by the interrupt signal output from M14 and M15, and the transmission destination C
When the PU does not read the data even after the preset time elapses, the runaway detection signal regarding the CPU of the transmission destination is output and the runaway CPU is reset. On the other hand, one watchdog timer circuit 16 can detect runaway and each C
The circuit is greatly simplified as compared with the conventional case where a watchdog timer circuit must be provided for each PU. Further, since the program for the watchdog timer can be deleted and it is not necessary to adjust the position where the program is inserted, the burden of program development can be greatly reduced.

Further, a stack check is carried out in which the return address after the end of the interrupt routine is stored, and if the routine cannot return to the main routine, processing such as initialization is carried out. Even then, the runaway can be detected and effectively dealt with.

In the above embodiment, the runaway detection signal S1
~ S3 is connected to the input ports of the CPUs 11 to 13, but is not limited to such a structure, and the runaway detection signal output from the watchdog timer circuit 16 is input as data through the encoder. You can also do it. With this configuration, it is possible to easily deal with the case where the number of CPUs increases.

Further, in the above embodiment, when the CPU 11 runs out of control, the runaway detection signal S1 is used as the reset signal of the CPU 11, but other C receiving the runaway detection signal S1.
The PUs 12 and 13 may be configured to reset the CPU 11.

[0043]

As described above in detail, according to the present invention, one watchdog timer can cope with runaway detection of a plurality of CPUs to simplify the circuit, and the watchdog timer program can be deleted. Therefore, it is possible to provide a runaway processing device that does not require adjustment of the insertion position of the program and can significantly reduce the burden of software development.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of a runaway processing device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a detailed configuration of a runaway processing device according to an embodiment.

FIG. 3 is a configuration diagram of a watchdog timer circuit according to an embodiment.

FIG. 4 is an operation explanatory diagram for explaining an interrupt process including a stack check according to an embodiment.

FIG. 5 is a diagram showing a time chart of the watchdog timer circuit in the embodiment.

[Explanation of symbols]

1, 2 ... CPU, 3 ... Dual port RAM, 4, 5 ...
Input port, 6 ... Watchdog timer circuit.

Claims (2)

[Claims] 1. A CPU is provided between a plurality of CPUs for data transmission, and when data to be transmitted from one CPU to another CPU is written, an interrupt signal is output to the other CPU, and the other CPU is Dual port R that stops the output of the interrupt signal by reading the data
AM and an interrupt signal output from the dual port RAM are taken in, and when the interrupt signal does not stop even after a predetermined time has elapsed, a runaway detection signal is output to stop the runaway of the other CPU that has runaway. A watchdog timer circuit for causing a runaway processing device. 2. A memory in which a processing program at the time of a runaway is stored and a stack in which a return address to a main routine after completion of an interrupt routine is stored in each CPU provided for each interrupt routine and accessed The runaway processing apparatus according to claim 1, further comprising: a unit that performs a check and executes the processing program when the process cannot return to the main routine.