JPH0521378A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a silicon film including boron which ensures excellent step-portion covering characteristic and is just suitable for manufacturing process under a low temperature condition. CONSTITUTION:An amorphous Si film is deposited by the pressure-reduced CVD method under a low temperature of 200 or higher and 400 deg.C or lower using any one of disilane (Si2H6) or trisilane (Si3H6) and dibolane (B2H6). Thereby, a Si film including boron which ensures excellent step-portion covering characteristic can be formed. Using the obtained Si film as a diffusion source, extremely shallow junction may be formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of forming electrodes and wirings having excellent step coverage at a low temperature.

[0002]

2. Description of the Related Art Low pressure chemical vapor deposition method using pyrolysis of monosilane (SiH ₄ )
A polycrystalline silicon (Si) film formed by eposition; abbreviated as LPCVD) is widely used for electrodes and wiring of semiconductor devices. However, since the polycrystalline Si film formed by the LPCVD method has extremely high resistance, impurities are doped by a well-known thermal diffusion method or ion implantation method in the subsequent steps to lower the resistance and obtain conductivity.

In the manufacture of a bipolar transistor, after forming an opening reaching the Si substrate in an insulating film formed on the Si substrate, a polycrystalline Si film is deposited, and impurities are doped by the ion implantation method. By heat treatment, impurities in the polycrystalline Si film are diffused into the Si substrate to form an emitter. Related to this type of method are, for example, BLU S Technology-Second Edition SMC-Edit (McGraw Hill,
1988) 499 to 507 (VLSI Technology,
SMSze ed. (McGraw-Hill, 1988) pp499-507).

[0004]

However, when boron ions or boron difluoride (BF ₂ ) ions are implanted into a polycrystalline Si film to form an emitter of a pnp bipolar transistor, boron in the polycrystalline Si film is activated. In order to achieve this, a high temperature heat treatment of 900 ° C. or higher is required, and boron having a large diffusion coefficient diffuses over a long distance, making it difficult to form a shallow base-emitter junction. as a result,
There has been a problem that the speedup of the pnp transistor cannot be realized.

Along with the miniaturization of LSI, the aspect ratio of the opening for forming the emitter increases, and the polycrystalline Si film formed in the opening having such a steep side wall is ion-implanted. If you do
There has been a problem that a portion of the polycrystalline Si film lacking boron is generated, and the resistance of electrodes and wirings becomes high.

On the other hand, in the case of doping impurities by the thermal diffusion method, it is possible to dope impurities into the steep step sidewalls by performing thermal diffusion at high temperature for a long time. However, as in the case of using the above-mentioned ion implantation method, at a place where the polycrystalline Si film is in contact with the Si substrate like the emitter, boron is diffused for a long distance in the Si substrate, and it is difficult to form a shallow junction. Is.

Disilane (Si ₂ H ₆ ) and diborane (B ₂ H ₆ ) are used as a method of doping boron into the polycrystalline Si film formed on the side wall of the opening, which is one of the above problems. Used as a raw material gas, in the temperature range of 520 ° C to 665 ° C,
A method of depositing a Si film while doping with boron has also been proposed (Journal of Electrochemical Society: Solid State Science and Technology, Vol. 133, No. 8, 1721-1).
724, August 1986; Electroche
m. Soc. SOLID-STATE SCIENCE
ANDTECHNOLOGY, Vol. 133, N
o. 8, pp1721-1724, August 19
86).

However, according to the study by the present inventor, Si ₂
A Si film deposited using H ₆ as a source gas in such a temperature range has poor step coverage, and when deposited in a deep groove, the film thickness on the side wall of the groove becomes significantly smaller than that on the upper surface. There was a problem. Further, it has been revealed that in the temperature range of 400 to 600 ° C., the deposition reaction of the film is extremely strong and it is difficult to control the film thickness and the like.

The object of the present invention is to solve the above-mentioned problems of the prior art, to have excellent step coverage, to be able to completely fill deep trenches and openings with large aspect ratios, and to easily form good electrodes and wirings. A method of manufacturing a semiconductor device is provided.

Another object of the present invention is to provide a method of manufacturing a semiconductor device which can easily form an extremely shallow junction.

[0011]

In order to achieve the above object, the present invention contains at least either disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H ₆ ) and diborane (B ₂ H ₆ ). LPCVD using mixed gas as a raw material, that is, CVD performed at a gas pressure lower than 1 atm
By the method, an amorphous Si film containing boron is formed in a temperature range higher than 200 ° C. and lower than 400 ° C.

[0012]

The amorphous Si film containing boron thus formed has excellent step coverage and can be completely buried even in a deep groove.

It is assumed that this is due to the following reasons. That is, Si ₂ H ₆ is above 400 ° C

[0014]

Embedded image Si ₂ H ₆ (g) ---> SiH ₂ (g) + SiH ₄ (g) ... (1) Decomposes in the gas phase to produce SiH ₂ (silylene).
Cause Since SiH ₂ has extremely high reactivity, it reacts with the substrate immediately after decomposition to deposit a Si film. as a result,
The deposition reaction of the film is rate-controlled by the supply of SiH ₂ . The supply of SiH ₂ is insufficient in the side wall of the deep step or in the groove as compared with the flat portion, and the step coverage is deteriorated. An inert gas or a doping gas that produces an n-type dopant (eg, phosphine (PH ₃ ) or arsine (AsH ₃ )) has a lower sticking probability to the substrate than SiH ₂ and does not affect the reaction of the formula (1). Has no effect. Therefore, even if these gases are introduced into the reaction vessel at the same time as Si ₂ H ₆ , the deposition rate of the Si film hardly changes and the step coverage is poor.

On the other hand, B ₂ H ₆ has a low decomposition temperature of 200 ° C.
It reacts with the substrate at temperatures above about a certain degree to form adsorbed species.
Since this adsorbed species easily reacts with Si ₂ H ₆ ,
The deposition reaction of the Si film proceeds even at a lower temperature.
Since this reaction is a pure surface reaction, the step coverage is not deteriorated as in the case where no impurities are contained or when an n-type doping gas is simultaneously supplied, and the film is uniformly deposited even in a deep groove. It is possible.

According to the plasma CVD method using one of SiH _{4 and} Si ₂ H ₆ and B ₂ H ₆ as the source gas, the Si film can be deposited at a temperature equal to or lower than that of the present invention. It is possible. However, plasma C
The film formed by the VD method has poor step coverage, and when deposited in a deep groove, voids are generated. Therefore, even if the source gas is the same, if the plasma CVD method is used to form the Si film, it is difficult to completely fill the deep groove.

In the present invention, the Si film is amorphous in the as-deposited state. For example, when this is heat-treated in nitrogen or an inert atmosphere at 650 ° C. for about 15 minutes, dendritic crystal grains (dendrites) grow, and at the same time, activation of impurities is completed and sufficient conductivity is obtained. Therefore, the temperature of the process of forming the electrodes and wirings made of polycrystalline Si, which has been conventionally about 900 ° C. or higher, can be significantly lowered.
If the Si film obtained by the present invention is used as an impurity diffusion source when forming a p-type emitter of a bipolar transistor, an extremely shallow base-emitter junction can be formed, and high-speed LSI can be realized. Particularly preferred.

If the Si film formed according to the present invention is applied to the formation of a MOS transistor, a shallow P-type source / drain diffusion layer can be formed, so that even a fine transistor having a short gate length is stable. It is possible to operate. Therefore, it is also effective for high integration of LSI. The average crystal grain size of the Si film formed by the present invention is equal to or larger than the film thickness, which is larger by one digit or more than that of the polycrystalline Si film formed by the conventional method. Therefore, the carrier mobility is high, and high conductivity can be obtained even if the boron concentration is reduced.

Since the Si film formed according to the present invention has excellent step coverage, it is possible to completely fill deep contact holes. Therefore, according to the present invention, Si
After the film is filled in the contact hole, it is reacted with a tungsten (W) -containing compound gas by using this as a reducing agent to replace the Si film with the W film, so that the contact hole is filled with W and a low resistance multilayer wiring is formed. it can. In the present invention, since the temperature at which the Si film is deposited is lower than 400 ° C., the present invention can be carried out even if a low melting point wiring material such as an aluminum alloy exists in the lower layer.

The reaction of replacing the Si film with the W film is represented by the following equation (2).

[0021]

2WF ₆ (g) + 3Si (s)-→ 2W (s) + 3SiF ₄ (g) (2) The formula (2) consumes the Si film and corresponds to the shape of the Si film. A reaction for forming a W film is shown, and the expression of substituting is used in this specification from that meaning. Therefore, in the reaction represented by the formula (2), when the Si film is completely consumed as the reducing agent, the W precipitation reaction spontaneously stops. Therefore, W does not precipitate at the location where the Si film does not exist. In addition, the Si film formed by the present invention is
When replaced by a film, it was confirmed that some amount of Si and boron were present in the replaced W film because the Si film was doped with boron.

When the Si film is replaced with the W film, if a thin W film is formed on the entire surface of the Si film in the initial stage of the reaction, the reaction between WF ₆ and Si in the film thickness (depth) direction is caused. The progress becomes extremely slow, and finally the reaction stops at a very thin portion of the Si film. Therefore, when forming a thick W film, it is necessary to previously form a W deposition reaction control film on the Si film and then perform CVD at an appropriate temperature (200 to 400 ° C.) to cause a substitution reaction. According to this method, S
It becomes difficult to form a thin W film on the i film surface, and WF ₆ and S
The reaction with i proceeds deep in the depth direction of the Si film, and
The film can be replaced with the W film. A Si oxide film is preferable as this type of reaction control film, but if it is a thin film having a function and effect of hindering nucleation of W formation on the surface of the Si film at the initial stage of the reaction and promoting the reaction in the depth direction of the film Alternatively, a film made of another material may be used. In this case, the film thickness is 1 to 3n
It is desirable to use a thin film of m. Then, it is preferable to practically form the Si oxide film in view of the ease of the pretreatment and the effect thereof. A practical method is to perform a well-known oxidation treatment called Chemical Oxide using a chemical agent capable of forming a thin silicon oxide film on the Si film surface. The reaction control film becomes unnecessary and is removed when the W substitution reaction of the Si film is completed.

When it is desired to stop the W substitution reaction at the interface between the Si film and the underlying layer, a film serving as a reaction barrier may be provided at this interface. This barrier film plays a role of stopping the replacement at the interface when the Si film is sequentially replaced with W from the surface in the depth direction. Therefore, it is desirable that this barrier film is a thermally stable substance that has a low resistance and does not easily react with W in the temperature range of CVD of Si and W (≦ 400 ° C.). As such a barrier film, for example, a transition metal element simple substance such as W, Mo, Ti, or Ta, or its nitride, or its silicide, cobalt silicide, aluminum nitride, and Ti are used.
Any one kind of conductor layer selected from the group of -W alloy can be used. The preferred thickness is 50 to 300 nm, more preferably 100 to 200 nm. Al, Au,
Ag and the like are not preferable because they easily react. This kind of barrier film is effective, for example, when direct connection between the semiconductor substrate and W is not desired, or when it is desired to surely stop the W substitution reaction at the bottom interface of the Si film that is the target of substitution with W. .

After replacing the Si film with the W film, if SiH ₄ , H ₂ or the like for reducing WF ₆ is added as in the prior art, the W deposition reaction from WF ₆ proceeds and the W film is replaced. W
It goes without saying that W can be further deposited in the gaps in the film or in the upper part thereof.

[0025]

EXAMPLES Example 1 FIG. 3 is a schematic diagram of a horizontal low pressure CVD apparatus used in this example. A jig 30 was placed in the center of the quartz tube 10, and a silicon substrate 40 was placed on it. The following two types of substrates were prepared as silicon substrates. The substrate 1 was formed by forming a thermal oxide film of 100 nm on a Si substrate, and after depositing a Si film containing boron thereon, it was used for measuring the film thickness. The substrate 2 was created by the procedure shown in FIG. First, as shown in FIG. 4A, a thickness of 1 μm is formed on the substrate 101.
m thermal oxide film 102 was formed. Next, as shown in FIG. 4B, grooves 103 having a width of 0.5 μm were formed at equal intervals by known lithography and dry etching techniques.
Subsequently, the oxide film 10 having a thickness of 100 nm is formed by the low pressure CVD method.
4 was formed as shown in FIG.

After placing the substrate 1 and the substrate 2 on the jig 30 and evacuating the inside of the quartz tube 10, the valves 50 and 60 are opened, Si ₂ H ₆ is 50 cc / min, and B ₂ H ₆ is 0.5 c.
Si containing boron at the same time with a flow rate of c / min
Was deposited to a thickness of about 200 nm. The pressure inside the quartz tube was maintained at 30 Pa while flowing Si ₂ H ₆ and B ₂ H ₆ . After depositing the Si film by flowing gas for a predetermined time, the substrate 4
0 was taken out from the quartz tube 10.

After that, for the substrate 1, the thickness of the Si film was measured by the optical interference method. On the other hand, the substrate 2 was cleaved along a plane perpendicular to the groove 103, and the step coverage was evaluated. The step coverage was defined as b / a by measuring the film thickness at the upper part of the step and the film thickness b at the lowermost part of the step sidewall in a cross-sectional photograph obtained using a scanning electron microscope.

FIG. 1 shows the relationship between the deposition rate of the Si film and the deposition temperature. For comparison, FIG. 1 shows B as a conventional technique.
The results when only Si ₂ H ₆ was introduced at a pressure of 30 Pa without adding ₂ H ₆ are also shown. From FIG. 1, it is understood that the addition temperature of the Si film can be reduced by about 150 ° C. by adding B ₂ H ₆ , and the Si film can be deposited at a sufficient rate even at 400 ° C. or less. When B ₂ H ₆ is added and the deposition temperature is 400 ° C. or lower, the deposition rate increases as the deposition temperature rises, and the system becomes the surface reaction rate limiting. On the other hand, at 400 ° C. or higher, the deposition rate decreases and the system becomes rate-controlled. In order to process a large number of substrates at the same time with good uniformity, it is desirable that the system is surface reaction rate-determining, and the film deposition temperature must be lower than 400 ° C.

FIG. 2 shows the relationship between the deposition temperature of the Si film and the step coverage. When the deposition temperature of the Si film is lower than 400 ° C., the step coverage is almost 1, and the deep trench can be filled. On the other hand, the deposition temperature of the film is 400 ℃
In the above cases and when B ₂ H ₆ was not added, the step coverage was deteriorated to 0.9 or less, and it was confirmed that the deep groove could not be completely filled.

It should be noted that Si ₂ H ₆ is doped with n-type doping gas such as phosphine (PH ₃ ) or arsine (AsH ₃ ) as B.
No change in the reaction of Si ₂ H ₆ may be added in place of the ₂ H _6,
No increase in deposition rate was observed. Further, the step coverage is almost the same as the case where no impurities are contained, and it is impossible to completely fill the deep groove.

According to the present embodiment, by using Si ₂ H ₆ and B ₂ H ₆ to deposit a Si film while doping boron at a temperature lower than 400 ° C., a sufficient deposition rate and step c
With overage, the deep holes can be filled with Si.

Example 2 In this example, an amorphous Si film containing boron formed according to the present invention is used as a diffusion source of impurities. Two samples 3 and 4 were prepared by the method shown in FIG. First, a Si ₃ N ₄ film 402 having a thickness of 0.5 μm was deposited on the Si substrate 401 by a known CVD method (FIG. 5A). Then, part of the Si ₃ N ₄ film 402 was removed by well-known lithography and dry etching techniques, and grooves 403 having a width of 0.5 μm were formed at equal intervals (FIG. 5B). Then, a Si film was formed and impurities were doped as described below. For sample 3, Si ₂ H ₆ and B ₂ H ₆ were 50 cc / min, respectively.
5 cc / min at the same time, under conditions of 350 ° C. and 30 Pa, as shown in FIG.
A 0 nm amorphous Si film 404 was formed. In Sample 4, a polycrystalline Si film 405 having a thickness of 30 nm was formed under the conditions of 630 ° C. and 80 Pa using SiH ₄ as a source gas.
After forming as shown in (d), BF ₂ + ions 406
With a driving energy of 20 keV and a driving amount of 2.5 × 1
I hit it with 0 ¹⁵ / cm ³ . Thereafter, the samples 3 and 4 are heat-treated at a temperature at which the impurities are sufficiently activated, and the diffusion regions 4
After forming 09, the distance that the impurities diffused from the surface of the Si substrate 401 into the substrate 401 (that is, the diffusion region 409).
Depth x _j ) was measured by a secondary ion mass spectrometer (SIMS). The results are shown in FIGS. 6 (a) and 6 (b).
In the sample 3 using the amorphous Si film containing boron according to the present invention as the diffusion source, the impurities were activated at a low temperature of 700 ° C., and the diffusion depth was increased as shown in FIG. Has a very shallow junction of 35 nm. Further, according to the study by the present inventor, it was confirmed that the impurities can be sufficiently activated even when the heat treatment is performed at a temperature lower than 700 ° C., for example, 650 ° C. On the other hand, when the sample 4 in which the BF ₂ + ion is implanted in the polycrystalline Si film is used as the diffusion source, 90% is required to sufficiently activate the impurities.
Heat treatment at about 0 ° C is required, and as a result, as shown in Fig. 6 (b).
As described above, the diffusion depth was as large as 250 nm, and it was difficult to form a shallow junction.

According to this embodiment, by using the amorphous Si film containing boron formed according to the present invention as a diffusion source of impurities, the heat treatment temperature can be reduced and the diffusion of impurities can be suppressed. It was confirmed that an extremely shallow junction could be formed.

<Embodiment 3> In this embodiment, an amorphous Si film containing boron formed by the present invention is formed by MO
An example used as a diffusion source when forming a source / drain region of an S transistor will be shown.

The MOS transistor was manufactured by the following procedure. First, as shown in FIG. 7A, the resistivity is 10Ω.
The oxide film 202 for element isolation is formed on the surface of the n-type Si substrate 201 ′ having a cm and plane orientation (100) by a known selective oxidation technique.
Was formed. Then, the Si substrate 201 ′ in an oxygen atmosphere
Oxide the surface of the gate oxide film 202 'with a thickness of 10 nm
Was formed. Next, a 100 nm polycrystalline Si film 203 was deposited by a low pressure CVD method, and impurities were added to reduce the resistance, and then a 200 nm thick SiO ₂ film 205 was formed by a low pressure CVD method. After that, the SiO ₂ film 205 and the polycrystalline Si are formed by the well-known lithography and dry etching techniques.
The unnecessary portion of the film 203 was removed. Subsequently, a SiO ₂ film having a thickness of 20 nm is formed on the entire surface by a low pressure CVD method, and then S
Anisotropic dry etching was performed until the surface of the i-substrate 201 ′ was exposed to form the SiO ₂ film 205 ′ only on the side wall of the SiO ₂ film 205 or the like. After that, Si ₂ H ₆ and B ₂ H ₆ are used as source gases, and a low pressure CVD method is performed to obtain 350
Thickness of 200n containing boron under conditions of ℃ and 30Pa
An amorphous Si film 208 having a thickness of m was formed, and then this Si film 208 was processed into a predetermined shape by a known technique as shown in FIG.

Next, the amorphous Si film 208 is set to 700
Amorphous Si film 2 after heat treatment for 20 minutes in a nitrogen atmosphere at ℃
Boron 08 was diffused into the Si substrate to form the source / drain regions 204 as shown in FIG. 7B. The heat treatment changed the Si film 208 from amorphous to polycrystalline 214.

The MOS transistor produced in this embodiment has a high punch-through breakdown voltage and a gate length of 0.3.
It was possible to operate with a sufficient margin even in the case of an extremely short μm. This is because the heat diffusion at a low temperature of 700 ° C. made it possible to form a junction having an extremely shallow and nearly rectangular shape. On the other hand, when the source / drain regions are formed by performing BF ₂ + ion implantation using a gate electrode made of a polycrystalline Si film as a mask as in the conventional case, the effective channel length becomes short. The punch-through phenomenon occurred at a lower voltage than the case of using the present invention. As a result, when the gate length is 0.3 μm,
It was impossible to obtain stable transistor characteristics. This is because the implanted impurities are distributed over a wide area according to the Gaussian distribution, and heat treatment at 900 ° C. or higher is required to activate the impurities, and the implanted impurities diffused deeply in the silicon substrate. is there.

According to the present embodiment, the source / drain regions are formed by diffusing impurities from the amorphous Si film containing boron formed according to the present invention to form a MOS transistor having a high punch-through breakdown voltage. Yes, L
The miniaturization of SI was realized.

<Embodiment 4> This embodiment is an example in which a Si film deposited in an amorphous state while adding boron according to the present invention is used for forming a diffusion layer of a polycrystalline SiMOS transistor.

The polycrystalline SiMOS transistor was produced by the procedure shown in FIG. First, as shown in FIG. 8A, an insulating film SiO ₂ film 218 was formed on the semiconductor substrate 201. Then, by a low pressure CVD method, Si ₂ H ₆ and B ₂
H ₆ was simultaneously flown to form a 100-nm-thick amorphous Si film 208 containing boron under the conditions of 350 ° C. and 30 Pa. After that, the Si film 208 containing boron was processed into a predetermined shape by using known lithography and dry etching. Next, by a low pressure CVD method using Si ₂ H ₆ as a source gas, a thickness of 1 at 525 ° C. containing no impurities is obtained.
A 0 nm amorphous Si film 215 was formed as shown in FIG. After that, a SiO ₂ film 205 having a thickness of 20 nm was formed at 700 ° C. by the LPCVD method. This allows
The Si films 208 and 215 became polycrystalline Si films 214 and 216, and at the same time, the diffusion layer 204 was formed. Next, Si
_After forming a 100 nm-thick amorphous Si film containing boron by a low pressure CVD method using ₂ H ₆ and B ₂ H ₆ as source gases, heat treating it in a nitrogen atmosphere at 700 ° C. for 20 minutes,
By patterning, a gate electrode 214 'of the transistor was formed as shown in FIG. After that, the well-known CV
8D, after forming the interlayer insulating film 217 as shown in FIG. 8D, a contact hole reaching the diffusion layer 204 is formed, and then an Al film 211 is formed and patterned to form a lead wiring. did. The polycrystalline SiMOS transistor manufactured in this example has a high punch-through breakdown voltage and was able to operate with a sufficient margin even when the gate length was about 0.3 μm. Conventionally, the formation of the source / drain is performed by ion implantation through the oxide film 205, and damage to the gate oxide film has been a problem. Since the ion implantation method is not used in this embodiment, the gate oxide film is not damaged.

According to this embodiment, a Si film formed by using Si ₂ H ₆ and B ₂ H ₆ at a low temperature is polycrystalline SiMO.
By using it as the source / drain of the S transistor, high reliability can be obtained even with high integration.

<Embodiment 5> This embodiment is an example in which the amorphous Si film containing boron formed according to the present invention is used for forming an emitter region of a pnp type bipolar transistor.

First, as shown in FIG. 9A (a), a depth of 1.2 μm was formed in a predetermined region on an n-type, plane orientation (100) Si substrate 501 by a thermal diffusion method using boron nitride.
A boron embedded layer 516 of m was formed. Then thickness 50
After forming the 0 nm epitaxial layer 503, a SiO ₂ film 504 having a thickness of 30 nm is formed by a well-known dry oxidation method, and further, a Si film having a thickness of 80 nm is formed by an LPCVD method.
_{A 3} N ₄ film 505 was formed. Then, after forming a trench for the isolation groove and the emitter and collector regions for element isolation reaching the buried layer by a known photoetching technique, SiO ₂ film 504' these grooves by LPCVD, 504
″ And a polycrystalline Si film 506. Then Si
_After forming a ₃ N ₄ film and using this as a mask to implant boron ions, heat treatment was performed at 950 ° C. for 30 minutes to form a collector region 507. Next, phosphorus is ion-implanted and heat-treated in a nitrogen atmosphere at 900 ° C. for 10 minutes to extract the external base region 50 for extracting the intrinsic base region.
8 was formed.

Next, using well-known lithography and dry etching, the Si ₃ N ₄ film 505 and the SiO ₂ film 504 in predetermined regions were sequentially removed. Thereafter, arsenic ions of 5 × 10 ¹³ / cm ² were implanted at an acceleration voltage of 40 keV and heat treatment was performed for 10 minutes in a nitrogen atmosphere at 900 ° C. to form an intrinsic base region 510 as shown in FIG. 9A (b).

As shown in FIG. 9A (c), the well-known LPCV is used.
A SiO ₂ film 504 ″ was formed by the D method, and a hole for forming an emitter was opened by known photoetching.

Next, by a low pressure CVD method using Si ₂ H ₆ and B ₂ H ₆ as source gases, as shown in FIG. 9B (d), boron containing 50 nm in thickness is contained under the conditions of 350 ° C. and 30 Pa. Amorphous Si film 509 was formed. At this time, the boron concentration in the Si film was set to 5 × 10 ²⁰ / cm ³ . Then, unnecessary portions of the amorphous Si film 509 were removed by known photoetching.

Heat treatment is performed for 20 minutes in a nitrogen atmosphere at 700 ° C. to diffuse the boron in the amorphous Si film 509 to the Si substrate, and as shown in FIG. 9B (e), the emitter region 513.
Was formed. Note that the amorphous Si film 50 is formed by this heat treatment.
9 becomes a polycrystalline silicon film 511 and exhibits conductivity.

After forming openings in the external base region and the collector as shown in FIG. 9B (f), an Al film 515 was formed and processed into a predetermined shape to form an electrode.

The thickness of both the emitter and base regions of the pnp bipolar transistor formed according to this embodiment is about 20 nm, which is extremely shallow compared to the emitter and base formed according to the prior art, and as a result, a high cutoff frequency was obtained. . In addition, the emitter resistance is also reduced compared to the conventional one.

According to this embodiment, Si ₂ H ₆ and B ₂ H ₆ are used as source gases to form a Si film containing boron at a low temperature, and impurities are diffused from the Si film to form an emitter region. By forming the, the cut-off frequency of the bipolar transistor can be improved and the speedup is realized.

<Embodiment 6> In this embodiment, an amorphous Si film containing boron is used for forming a base region of an npn-type bipolar transistor.

First, as shown in FIG. 10A (a), p-type,
Si substrate 501 having a plane orientation (100) and a resistivity of 10 Ωcm
A low resistance antimony burying layer 502 having a depth of 1.2 μm was formed on the predetermined region by a thermal diffusion method. Then, an epitaxial layer 503 having a thickness of 400 nm is formed by using a known Si epitaxial growth technique, and then a SiO ₂ film 504 having a thickness of 30 nm is formed by a known dry oxidation method, and an Si ₃ N ₄ film having a thickness of 80 nm is formed by LPCVD. 505
Were sequentially formed. After that, a well-known photoetching is performed to form a groove for element isolation reaching the buried layer 502 and a groove for separating the emitter and the collector.
SiO ₂ films 504 ′ and 504 ″ and a polycrystalline Si film 506 were formed by the CVD method to fill the inside of the groove. Si ₃
A N ₄ film (not shown) was formed, phosphorus ions were implanted using this as a mask, and then heat treatment was performed at 950 ° C. for 30 minutes to form a collector region 507. afterwards,
BF ₂ + was ion-implanted, followed by heat treatment in a nitrogen atmosphere at 900 ° C. for 10 minutes to form an external base region 508 for extracting the intrinsic base region.

As shown in FIG. 10A (b), the Si ₃ N ₄ film 505 and the SiO ₂ film 504 formed in predetermined regions were sequentially removed by using known lithography and dry etching. Next, by the LPCVD method using Si ₂ H ₆ and B ₂ H ₆ as source gases, under the conditions of 300 ° C. and 20 Pa,
A Si film 509 containing boron having a thickness of 20 nm was formed. The boron concentration in the film was adjusted to 1 × 10 ¹⁹ / cm ³ . The Si film 509 containing boron was processed into a predetermined shape by known photoetching.

A heat treatment was performed in a nitrogen atmosphere at 700 ° C. for 20 minutes to diffuse boron in the Si film 509 into the Si substrate to form a base region 510 as shown in FIG. 10A (c). By the heat treatment, the Si film 509 becomes
The portion in contact with the substrate became a single crystal by solid phase epitaxial growth, and the remaining portion became a polycrystalline silicon film 511.

By the low pressure CVD method using Si ₂ H ₆ and PH ₃ as source gases, an amorphous Si film 512 containing phosphorus having a thickness of 50 nm is formed under the condition of 500 ° C. and 30 Pa as shown in FIG. 10B.
It was formed on the Si film 511 as shown in FIG. At this time, the phosphorus concentration in the Si film 511 was set to 4 × 10 ²⁰ / cm ³ . Next, the amorphous Si film 512 was processed into a predetermined shape by known photoetching.

A heat treatment was performed for 20 minutes in a nitrogen atmosphere at 700 ° C. to diffuse phosphorus in the Si film 512 into the Si substrate to form an emitter 513 as shown in FIG. 10B (e). By this heat treatment, the Si film 512 became a polycrystalline silicon film 514 and exhibited conductivity. Then, after forming openings in the external base region and the collector region, respectively,
As shown in FIG. 10B (f), an Al film 515 was formed to serve as an electrode.

Since the base region of the bipolar transistor formed in this embodiment has a thickness of about 30 nm, which is extremely shallow as compared with the conventional one, a much higher cutoff frequency than that of the conventional one was obtained.

According to this embodiment, Si ₂ H ₆ and B ₂ H ₆ are used as source gases to form a Si film containing boron, and impurities are diffused from the Si film to form a base region. The cutoff frequency of the bipolar transistor was improved.

<Embodiment 7> In this embodiment, an amorphous Si film containing boron formed at a low temperature according to the present invention is used for a memory cell of a dynamic random access memory (DRAM). .

As shown in FIG. 11A, the Si substrate 701
A groove having a depth of 5 μm was formed in a predetermined region of the substrate by known lithography and dry etching. Next, SiH ₄ and N ₂
SiO ₂ film 70 is formed by LPCVD using O as a source gas.
After forming No. 2, anisotropic etching was performed to leave the SiO ₂ film 702 only on the side wall in the groove, and removed from other portions. An amorphous Si film 704 containing boron was formed by LPCVD using Si ₂ H ₆ and B ₂ H ₆ , and this was patterned by known photoetching. The formation temperature was 350 ° C. and the pressure was 30 Pa. Then 900 ° C
Of the boron diffusion layer 70 by heat treatment in the nitrogen atmosphere of
3 was formed as a plate electrode. At this time, the amorphous Si film 704 containing boron became polycrystalline. Next, by LPCVD using SiH ₂ Cl ₂ and NH ₃ ,
A silicon nitride film (Si ₃ N ₄ ) was deposited and the surface was oxidized to form a silicon nitride film / oxide film laminated film 705.
Then, amorphous Si 706 containing boron was deposited by LPCVD using Si ₂ H ₆ and B ₂ H ₆ to completely fill the groove. The deposition conditions are a furnace temperature of 350 ° C and a pressure of 30P.
a. Under this condition, the amorphous Si had excellent step coverage and could fill the groove almost completely even if the aspect ratio was 1.5 or more. After that, well-known dry etching was performed on the entire surface to leave the amorphous Si film only in the groove and remove it from other portions. Then 700 ° C
Was heat-treated in the nitrogen atmosphere for 20 minutes to make the Si film 706 polycrystalline and used as a storage electrode. At this time, the Si film 706
Boron is diffused into the substrate 701 to form a diffusion layer 707. Through the above steps, the capacitor part was formed.

Next, as shown in FIG. 11B, the surface of the Si substrate 701 was oxidized in an oxygen atmosphere to form a gate oxide film 708 having a thickness of 6 nm. A thickness of 150 n containing boron by LPCVD using Si ₂ H ₆ and B ₂ H ₆ .
m amorphous Si film is formed, and it is used in a nitrogen atmosphere at 650 ° C. for 2 hours.
It was treated for 0 minutes to be polycrystallized, and patterned by well-known lithography and dry etching to form a gate electrode 709. After implanting BF ₂ + ions, heat treatment was performed in a nitrogen atmosphere at 900 ° C. to form source / drain regions 710. After that, CVD SiO ₂ film 7
11 was deposited and processed to complete a transistor.

The resistance of the storage electrode and the plate electrode of the memory cell manufactured in this example was remarkably lower than that of the conventional one, so that the operation at a much higher speed than the conventional one was possible. Further, since Si has a step coverage, it is possible to prevent the generation of voids (voids) in the groove, and the defects such as disconnection are greatly reduced as compared with the prior art.

According to the present embodiment, by using the amorphous Si film containing boron formed at a low temperature for the storage electrode and plate electrode of the capacitor, the speedup and the reliability improvement of the DRAM are realized. It was

Although the DRAM having the groove type capacitor has been described in this embodiment, the same effect can be obtained even with the laminated type capacitor.

<Embodiment 8> This embodiment is an example in which the amorphous Si film containing boron is replaced with a W film and the inside of the opening is filled with W.

The basic structure of the apparatus used in this example is the same as that shown in FIG. 3, and only the gas to be introduced is different.

The following was used as the sample substrate 40. First, a 100 nm thick SiO ₂ film was formed on a Si wafer by a thermal oxidation method. Next, using Si ₂ H ₆ and B ₂ H ₆ as source gases, an amorphous Si film containing boron having a thickness of 1 μm was formed. At this time, the flow rates of Si ₂ H ₆ and B ₂ H ₆ were 50 cc / min and 0.5 cc / min, respectively, the furnace temperature was 350 ° C., and the pressure was 30 Pa.

The jig 30 was placed in the center of the quartz tube 10 and the sample substrate 40 was mounted on it. After evacuating the inside of the quartz tube 10, the valves 50 and 70 are opened to introduce WF ₆ and N ₂ into the furnace, and the amorphous Si film containing boron is W
The membrane was replaced. The flow rate of WF ₆ and N ₂ is 20cc /
Min, 2000 cc / min, the furnace temperature was 300 ° C., and the furnace pressure was 100 Pa. After introducing the gas for a predetermined time to replace the film, the sample substrate 40 was taken out. afterwards,
The sample substrate 40 was cleaved along a plane perpendicular to the surface, and the film thickness of W formed by a scanning electron microscope was measured. Results are shown in FIG.

In FIG. 12, a straight line (a) shows that a 1.1 nm thick oxide film (Chemical Oxide) is formed on the surface of the amorphous Si film containing boron by the nitric acid treatment heated to 110 ° C.
Of the amorphous Si film as a W
This is the result when the film was replaced. The W film thickness increased in proportion to the replacement time.

In FIG. 12, the straight line (b) shows that the amorphous Si film containing boron is washed with a 1% HF aqueous solution for 60 seconds to remove the oxide film on the surface of the Si film, and then the amorphous Si film is subjected to W This is the result of replacing the film. At 300 ° C., the formed W film thickness was approximately 10 nm and was constant regardless of the formation time, and the substitution reaction hardly proceeded.

According to this embodiment, a W reactive deposition control film is formed on an amorphous Si film containing boron, and this film is subjected to WF ₆
It was found that a W film with a thickness of about 1 μm can be formed by reacting with. In addition, since the amorphous Si film formed under the above conditions has a very good step coverage, by replacing this amorphous Si with W, the inside of the contact hole or the connection hole can be very well filled with W. It was confirmed that filling was possible.

<Embodiment 9> FIGS. 13A (a) to 13C (i) are views showing steps of forming a tungsten film burying layer.

First, as shown in FIG. 13A (a), after forming an element isolation SiO ₂ film 202 and a gate SiO ₂ film 202 'on a p-type (100) Si substrate 201 by a known technique, The polycrystalline Si film 203 having a thickness of 300 nm is set to L
The gate electrode was formed by the PCVD method, and after adding impurities to reduce the resistance, patterning was performed by ordinary lithography and dry etching techniques. The gate electrode 20 made of the Si film thus formed
Impurity ion implantation is performed using 3 as a mask, and further heat treatment is performed to form an impurity diffusion layer 2 serving as a source and a drain.
After forming 04, the SiO ₂ film 20 is formed by the LPCVD method.
5 was formed as an interlayer oxide film.

As shown in FIG. 13A (b), a SiO ₂ film (Boron Doped Phosphosilicate Gl) containing boron and phosphorus is formed.
An ass film (hereinafter referred to as a BPSG film) 206 is formed to a thickness of 700 nm by a CVD method, and then annealed in N ₂ at 900 ° C. for reflow, and then a contact hole having a diameter of 0.5 μm is formed by lithography and dry etching techniques. opened h.

Next, as shown in FIG. 13A (c), a titanium nitride (TiN) film 207 is formed by reactive sputtering.
(Thickness 150 nm) is formed on the entire surface, then Si ₂ H ₆ and B
Using ₂ H ₆ as a source gas, by LPCVD, furnace temperature 350 ° C., thickness containing boron at a pressure 30 Pa 500
An amorphous Si film 208 having a thickness of nm was formed. At this time, when the deposition temperature of the film exceeded 400 ° C., peeling of the TiN film occurred. Therefore, it is desirable that the deposition temperature of the Si film be lower than 400 ° C. Then, a photoresist film 209 was applied on the entire surface so that the surface was flat.

As shown in FIG. 13B (d), dry etching using SF ₆ is performed on the entire surface to leave the TiN film 207 and the amorphous Si film 208 containing boron only inside the contact hole h. All other parts were removed.
The TiN film 207 may remain outside the contact hole. Rather, when a conductor layer of Al or the like is formed thereon in a later step, the TiN film acts as a barrier layer also on the Al film, which helps improve reliability. Then 1
Immerse the sample in HNO ₃ heated to 10 ° C. for 1 minute,
1.1 nm thick silicon oxide film 2 on the surface of Si film 208
02 ”was formed. As shown in FIG. 13B (e), WF was formed.
_The amorphous Si film 208 containing boron was entirely replaced with the W film 210 by the CVD method using ₆ as a source gas. The CVD conditions are gas flow ratio WF ₆ / N ₂ = 2
0 / 2000sccm, total pressure 100Pa, temperature 300
It was ℃. After the replacement, the silicon oxide film 202 ″ partially left on the surface was removed by an aqueous solution of hydrofluoric acid.

As shown in FIG. 13B (f), the Al film 211
(Thickness 500 nm) and molybdenum silicide film 21
2 (thickness 100 nm) is sequentially deposited, and Al wiring is formed by patterning by well-known photo-etching, followed by plasma SiO film / SOG (Spin on Glass) film /
A laminated film 213 (thicknesses of 300 nm / 400 nm / 300 nm, total 1 μm) made of a plasma SiO film is formed, and the molybdenum silicide film 21 is formed on the laminated film 213 by using known lithography and dry etching techniques.
A contact hole h ′ having a diameter of 0.5 μm and reaching 2 was formed.

As shown in FIG. 13C (g), low pressure CVD
Method, the amorphous Si film 208 containing boron (thickness: 500 n) under the conditions of a furnace temperature of 350 ° C. and a pressure of 30 Pa.
m) was formed. At this time, the temperature exceeds 400 ° C and 500
When the temperature was close to 0 ° C, the Al wiring was melted. Then, the entire surface was dry-etched to leave the amorphous Si film 208 only in the contact holes h ′ and remove the other parts. afterwards,
HN heated to 110 ° C in the same manner as in the process of Fig. 14B (d)
The sample was dipped in O ₃ for 1 minute to form a 1.1 nm thick silicon oxide film 202 ″ on the surface of the Si film 208.

As shown in FIG. 13C (h), the amorphous Si film 20 containing boron is formed by the CVD method using WF _6.
All of 8 were replaced with W film 210. The CVD conditions were a gas flow rate ratio WF ₆ / Ar = 20/2000 sccm, a total pressure of 100 Pa, and a temperature of 300 ° C. The silicon oxide film 202 ″ partially left on the surface of the W film 210 was removed by an aqueous solution of hydrofluoric acid. Further, the well-known C using WF ₆ and H ₂ was used.
The contact hole h ′ was completely filled with the W film by the VD method. The CVD condition in this case is that the gas flow rate is WF ₆ / H ₂ =
20 / 2000sccm, total pressure 60Pa, temperature 350
It was ℃. At this time, the reason why the conventional CVD with addition of H ₂ is used is that, when the Si film is replaced with the W film, 2 mol of the W film is generated with respect to 3 mol of the Si film as shown in the above formula (2). ,
This is because the volume is reduced. CV by this condition
By performing D, W could be selectively deposited only on the W film.

As shown in FIG. 13C (i), the Al film 211
(Thickness 900 nm) is formed by the sputtering method,
The second layer Al wiring was formed into a predetermined shape by using known photo etching.

According to this embodiment, the Si substrate and the Al wiring,
The contact hole between the Al wiring and the Al wiring is filled with tungsten, and a flat multilayer wiring structure is obtained. As a result, A
Problems such as step breaks between 1 wirings have been greatly improved. Also,
Source / drain and wiring contact resistance, and Al
The contact resistance between the wirings was significantly reduced compared to the conventional one.

<Embodiment 10> This embodiment is an example in which an amorphous Si film containing boron is used as it is for filling a contact hole without replacing it with a W film.

First, as shown in FIG.
A semiconductor device having the same sectional structure as A (c) was formed. Subsequently, as shown in FIG. 14A (a), the entire surface is dry-etched using SF _6, and the amorphous Si film 208 containing boron is left only inside the contact hole h, and other portions are formed. Removed. In this example, the dry etching was terminated when the TiN film 207 was exposed, and the TiN film was left outside the contact hole.

Then, as shown in FIG. 14A (b), Ti
After forming the N film 207 and the Al film 211 in an overlapping manner, they were patterned into a predetermined shape by well-known lithography and dry etching to form an Al wiring. Plasma SiO
Film / SOG film / plasma SiO film three-layer film 213
(Thickness is 300 nm / 400 nm / 300 nm, respectively)
Then, a predetermined portion was etched again by a well-known dry etching to form a contact hole h ′ having a diameter of 0.5 μm and reaching the Al film 211.

As shown in FIG. 14A (c), a molybdenum silicide film 212 is formed over the entire surface, and further Si ₂ H ₆ and B _{2 are formed.}
An amorphous Si film 208 containing boron having a thickness of 500 nm was formed at a temperature of 350 ° C. by CVD using H ₆ to completely fill the contact hole h ′. The entire surface was dry-etched to leave the amorphous Si film 208 containing boron only inside the contact hole h ′ and remove the other parts, as shown in FIG. 14B (d).

Finally, as shown in FIG. 14B (e), Al
After the film 211 (thickness 900 nm) is formed by the sputtering method, the Al film 211 and the molybdenum silicide film 212 are formed by using well-known lithography and dry etching techniques.
Was patterned to form a second-layer Al wiring.

In this embodiment, since the Si film 208 buried in the contact holes h and h ′ remains amorphous, it has almost no conductivity. It is the TiN film 207 and the molybdenum silicide film 2 that are in contact with the Al wiring that contribute to electrical conduction.
Twelve. Therefore, the resistance of the wiring was slightly higher than that in the case of Example 9. However, the surface of the multilayer wiring structure was even flatter than that of Example 9, and the problems such as disconnection of the Al wiring on the step were further improved. Furthermore, simplification of the process has been realized.

<Embodiment 11> In this embodiment, an example is shown in which a W film is formed on an amorphous Si film containing boron and a W—Si alloy is formed by a subsequent heat treatment.

Samples 5 and 6 were prepared by the procedure shown in FIGS. 15 (a) to 15 (f). First, as shown in FIG. 15A, the surface of the Si substrate 601 is thermally oxidized to a thickness of 100 nm.
Of SiO ₂ film 602 was formed. Then, a Si film was formed and impurities were doped by the following method. In Sample 5, as shown in FIG. 15B, Si ₂ H ₆ and B ₂
H ₆ was simultaneously flown at flow rates of 50 cc / min and 0.5 cc / min, respectively, to form a boron-containing amorphous Si film 603 having a thickness of 400 nm under the conditions of 350 ° C. and 30 Pa.
In Sample 6, 630 was used as the source gas of SiH _4.
After forming a polycrystalline Si film 604 having a thickness of 400 nm as shown in FIG. 15C under the condition of 80 ° C. and 80 Pa, B + ions 605 are implanted with an energy of 50 keV and an implantation amount of 2 ×.
Ion implantation was performed under the condition of 10 ¹⁶ / cm ² . After that, Sample 6 was heat-treated in a nitrogen atmosphere at 950 ° C. for 30 minutes so that the distribution of impurities was substantially constant in the film thickness direction.

As shown in FIGS. 15D and 15E, an amorphous Si film 603 containing boron and a polycrystalline S film are formed.
A W film 607 having a thickness of 200 nm was formed on the i film 604 by a low pressure CVD method using WF ₆ and H ₂ . The conditions at this time are as follows: gas flow rate WF ₆ / H ₂ = 20/2000 sccm,
The temperature was 350 ° C. and the total pressure was 60 Pa. Next, 800 ℃
Was heat-treated in the H ₂ atmosphere for 30 minutes to dissolve Si in the W film to form a W-Si alloy 608 as shown in FIG. 15 (f). By this heat treatment, the amorphous Si film 603 containing boron becomes a polycrystalline silicon film 606.
Becomes Finally, the hydrogen peroxide solution removed the unreacted W film.

Then, the samples 5 and 6 were cleaved along a plane perpendicular to the Si substrate surface, and the surface condition of the W-Si alloy and the condition of the interface between the W-Si alloy and the Si film were examined by a scanning electron microscope. Moreover, the composition of each alloy was observed by Auger electron spectroscopy.

As a result, the unevenness of the surface of the sample 5 obtained by W-Si alloying the amorphous Si film containing boron and the interface between the Si film 606 and the W-Si alloy film 608 are flat as compared with the sample 6. there were. This is because uniform alloying did not proceed due to the presence of crystal grains of various orientations in the Si film of Sample 6, whereas the Si film of Sample 5 was amorphous, so that the W film and S
It is considered that uniform alloying proceeded at the interface of the i film. In each of Sample 5 and Sample 6, the composition of the formed alloy was approximately 1 W atom and 2 Si atoms.

According to this embodiment, the W film is formed on the Si film containing boron formed by the CVD using Si ₂ H ₆ and B ₂ H ₆ and the heat treatment is performed to remove the surface and interface. It was confirmed that a W-Si alloy having excellent flatness can be formed.

Although the low pressure CVD method using WF ₆ and H ₂ is used as the method for forming the W film in this embodiment, a low pressure CVD method or a sputtering method using WF ₆ and SiH ₄ may be used. Absent. Moreover, you may use these multiple types.

<Embodiment 12> In this embodiment, an amorphous Si film containing boron is used as a program wiring of an integrated circuit, and a part of the film is irradiated with an energy beam spot to be polycrystallized for programming. It is an example.

16 (a) and 16 (b) are schematic diagrams showing the basic concept. As shown in FIG. 16 (a), Si
On the substrate 301, a three-layer insulating film 302 composed of a plasma SiO ₂ film / SOG film / plasma SiO ₂ film is interposed,
Al wirings 303 and 303 'are formed. Fig. 16
Although omitted in (a), the Al wiring 303,
At least one of 303 ', for example, Al wiring 3
03 is connected to a semiconductor device provided on the Si substrate 301. For example, a TiN film 304 is formed as a barrier metal film on the Al wirings 303 and 303 ′. Plasma SiO film / SOG film / plasma SiO on this wiring
A three-layer film 302 'made of a film was formed and patterned by a well-known lithography and dry etching technique to expose a part of each of the wirings 303 and 303'. Then, an amorphous Si film 305 containing boron is formed by a low pressure CVD method using Si ₂ H ₆ and B ₂ H ₆ as source gases under the conditions of 350 ° C. and 30 Pa, and well-known photoetching is performed. The Si film 305 containing boron was patterned.

The Si film 305 is amorphous at this stage, and the hydrogen concentration in the film is small, so that the resistance is extremely high. Therefore, it can be said that the Al wirings 303 and 303 'are completely insulated from each other. By irradiating the Si film 305 with a laser beam spot 306 and applying energy thereto, amorphous Si as shown in FIG.
The film 305 becomes a polycrystalline silicon film 307, and at the same time Si
The impurities contained in the film 307 are activated to obtain conductivity. As a result, the Al wirings 303 and 303 'are electrically connected to each other.

The resistance of the Si film 305 before laser irradiation was 10 ¹⁰ Ω or more, and the Al wirings 303 and 303 ′ were insulated. However, the diameter is 1 μm from the top of the Si film 305.
When a laser beam of m is irradiated for 30 nsec, S
The i film 305 is polycrystallized and its resistance becomes 200Ω, which is reduced to 1/10 ⁷ before irradiation, and the Al wirings 303 and 30 are formed.
The 3's were conducted to each other. The energy of the laser is about 1/100 to 1/10 of the energy required to melt and cut the Al film or the polycrystalline Si film.
The Al film, the TiN film, the interlayer insulating film, and the underlying Si substrate were hardly affected.

That is, according to the present embodiment, it is possible to convert a high resistance body into a conductor by using an inexpensive laser with low energy and low power. Therefore, the amorphous Si
A wiring or a circuit formed by using a film is placed in an integrated circuit, and a predetermined portion is short-circuited by the laser irradiation to replace a defective circuit or circuit block with a good circuit or circuit block. As an example, if a decoder circuit in the memory circuit is provided with a spare decoder circuit using the Si film and a corresponding spare memory cell is provided, the defective bit can be repaired. Furthermore, if the Si film is incorporated in the decoder circuit itself in the memory circuit, information can be written by the short circuit caused by the laser light irradiation.

Conventionally, most of the defect repairs of the memory are
This method has been performed by cutting a Si film or an Al film with a laser beam having a large energy, opening a decoder connected to a defective cell, and replacing it with a defect-free cell connected to a dummy decoder. However, in this method, melted polycrystalline Si or Al connects to nearby wiring or damages the insulating film, so that a sufficient margin is required for the layout and there is a drawback that the area becomes large. However, according to this embodiment, since the Si film and the Al film are not melted, the spare decoder circuit can be downsized. This effect is further promoted by the feature that the Si film can be formed on the Al wiring.

Although the present embodiment utilizes only the short circuit, it can be opened by increasing the energy of laser irradiation, and it is needless to say that if these are used together, the degree of freedom of wiring is further increased. Absent. Further, although the laser beam is used as the energy source in this embodiment, an electron beam or an ion beam having similar energy may be used.

In Examples 1 to 12, the amorphous Si film containing boron was deposited at 200 ° C. or higher and 40
It was found that the same effect can be obtained if the temperature is lower than 0 ° C. When the deposition temperature of the film is higher than 400 ° C., the reaction is rate-determined, and it becomes difficult to deposit the Si film with good controllability. Further, the step coverage becomes 0.9 or less, which makes it difficult to fill the groove having a large aspect ratio. When the deposition temperature is 200 ° C. or lower, the deposition rate of the Si film is extremely low at 1 nm / min or less, and the throughput is extremely low, so that it cannot be applied to the manufacture of semiconductor devices. Although Si ₂ H ₆ was used as the source gas when depositing the amorphous Si film containing boron in the above-mentioned examples, the same effect can be obtained by using Si ₃ H ₈ .

In Examples 9 and 10, the transition metal elements such as Ti and Ta, or their nitrides, or their silicides, aluminum nitrides, gobarto silicides, and titanium tungsten are used as barrier metals in the contact portions. The same effect can be obtained by using an alloy film such as. In addition, as the interlayer insulating film, the first
BPSG as the layer and plasma SiO / SOG / as the second layer
Although the stacked film of plasma SiO is used, the same effect can be obtained by using PSG or a polyimide heat resistant organic polymer insulating film instead.

[0104]

According to the present invention, it is possible to form a boron-containing Si film having excellent step coverage. Since activation of impurities is completed in the Si film by heat treatment at a lower temperature than in the conventional case, an extremely shallow junction can be formed by using this Si film as a diffusion source. Also, the formed Si
Since the film can be replaced with the W film, a flat and highly reliable wiring can be formed, and high speed and high integration of the LSI can be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing a relationship between a deposition rate of a Si film and a deposition temperature.

FIG. 2 is a diagram showing a relationship between a step coverage of a Si film and a deposition temperature.

FIG. 3 is a schematic view of an apparatus used for carrying out the present invention.

FIG. 4 is a diagram showing a procedure for creating a step sample.

FIG. 5 is a view showing a procedure for preparing a sample used for measuring a diffusion depth.

FIG. 6 is a diagram showing the relationship between the depth from the Si film surface and the impurity concentration.

FIG. 7 is a diagram showing a manufacturing process of a MOS transistor using amorphous Si as a diffusion source.

FIG. 8 is a diagram showing a manufacturing process of a polycrystalline SiMOS transistor.

FIG. 9A is a diagram showing the first half of the example relating to the manufacture of the bipolar transistor.

FIG. 9B is a diagram showing the second half of the example relating to the manufacture of the bipolar transistor.

FIG. 10A is a diagram showing a first half of another example of the bipolar transistor.

FIG. 10B is a diagram showing the latter half of another embodiment of the bipolar transistor.

FIG. 11 is a process drawing showing an embodiment relating to manufacturing of a DRAM.

FIG. 12 is a diagram showing the relationship between W film thickness and replacement time.

FIG. 13A is a diagram showing a first step of an example of manufacturing a MOS transistor.

FIG. 13B is a diagram showing a step in the middle of an example of manufacturing a MOS transistor.

FIG. 13C is a diagram showing a final step of the example relating to the manufacture of the MOS transistor.

FIG. 14A is a process drawing showing the first half of another embodiment of a MOS transistor.

FIG. 14B is a second-half process drawing of another embodiment of the MOS transistor.

FIG. 15 is a diagram showing a method for forming a W-Si alloy film.

FIG. 16 is a diagram showing a circuit short circuit due to laser beam irradiation.

[Explanation of symbols]

10 ... Quartz tube, 20 ... Heater, 30 ... Jig, 40 ... Sample substrate, 50, 60, 70 ... Valve, 80 ... Exhaust system, 10
1 ... Si substrate, 102 ... Thermal oxide film, 103 ... Groove, 104
... oxide film, 201, 201 '... Si substrate, 202, 20
2 ', 202 "... oxide film, 203 ... polycrystalline Si film, 20
4 ... Source / drain region, 205, 205 '... CVD
SiO ₂ film, 206 ... BPSG film, 207 ... TiN film,
208 ... Amorphous Si film, 209 ... Photoresist film, 21
0 ... W film, 211 ... Al film, 212 ... Molybdenum silicide film, 213 ... Plasma SiO / SOG / plasma S
iO film, 214 ... Polycrystalline Si film containing boron, 21
5 ... Amorphous Si film, 216 ... Polycrystalline Si film, 217 ... Interlayer insulating film, 218 ... Insulating film, h, h '... Contact hole,
301 ... Si substrate, 302, 302 '... Three-layer insulating film,
303, 303 '... Al film, 304 ... TiN film, 305
... Amorphous Si film, 306 ... Laser beam spot, 3
07 ... Polycrystalline Si film, 401 ... Si substrate, 402 ... Si
₃ N ₄ film, 403 ... Groove, 404 ... Amorphous Si film, 405 ...
Polycrystalline Si film, 406 ... BF ₂ ions, 408 ... Polycrystalline Si film, 409 ... Diffusion layer, 501 ... Si substrate, 502 ...
Antimony buried layer, 503 ... Epitaxial growth layer, 5
04, 504 ', 504 ", 504'" ... oxide film, 50
5 ... Si ₃ N ₄ film, 506 ... Polycrystalline Si film, 507 ... Collector region, 508 ... External base region, 509 ... Amorphous S
i film, 510 ... Base region, 511 ... Polycrystalline Si film, 5
12 ... Amorphous Si film, 513 ... Emitter region, 514 ...
Polycrystalline Si film, 515 ... Al film, 516 ... Boron buried layer, 601 ... Si substrate, 602 ... Oxide film, 603 ... Amorphous Si film, 604 ... Polycrystalline Si film, 606 ... Polycrystalline Si
Film, 607 ... W film, 608 ... W-Si alloy film, 701 ...
Si substrate, 702, 711 ... SiO ₂ film, 703, 70
7 ... Diffusion layer, 704, 706, 709 ... Polycrystalline Si film,
705 ... Silicon nitride film / oxide film laminated film, 708 ... Oxide film, 710 ... Source / drain region.

Continuation of front page (51) Int.Cl. ⁵ Identification number Office reference number FI Technical indication location H01L 21/28 A 7738-4M 301 R 7738-4M 21/82 21/3205 27/04 C 8427-4M 21 / 331 29/73 21/336 29/784 7377-4M H01L 29/72 8225-4M 29/78 301 P 9056-4M 311 Y (72) Inventor Nobuyoshi Kobayashi 1-280 Higashi Renegakubo, Kokubunji, Tokyo Hitachi, Ltd. Central Research Laboratory (72) Inventor Mitsuo Namba 1-280 Higashi Koikekubo, Kokubunji City, Tokyo Inside Hitachi Central Research Laboratory (72) Inventor Takashi Hashimoto 1-280 Higashi Koikeku, Tokyo Kokubunji City Central Research Laboratory, Hitachi Ltd.

Claims (14)

[Claims] 1. At least one selected from the group consisting of disilane and trisilane and diborane are introduced into a reaction vessel, and a chemical vapor deposition method is performed under the conditions of a pressure of 1 atm or less and a temperature of 200 ° C. or higher and lower than 400 ° C. A method of manufacturing a semiconductor device, comprising the step of forming an amorphous silicon film containing boron on a surface of a substrate placed in a reaction container. 2. The amorphous silicon film containing boron is formed on an exposed surface of a semiconductor substrate, and the amorphous silicon film containing boron is formed and then heat-treated to form the amorphous silicon film. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of diffusing the boron into the semiconductor region from a crystalline silicon film to form a p-type region in the surface region of the semiconductor substrate. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the p-type region is a source or drain region of a MOS transistor. 4. The method of manufacturing a semiconductor device according to claim 2, wherein the p-type region is an emitter or a base of a bipolar transistor. 5. The semiconductor device according to claim 2, further comprising a step of heat-treating the amorphous silicon film in an inert atmosphere to form a polycrystalline silicon film. Manufacturing method. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the temperature of the heat treatment is 700 ° C. or lower. 7. The amorphous silicon film containing boron is formed in an opening of an insulating film formed on the semiconductor substrate, and the amorphous silicon film in the opening is replaced with tungsten. The method of manufacturing a semiconductor device according to claim 1, wherein: 8. The method of manufacturing a semiconductor device according to claim 7, wherein the replacement with tungsten is performed by bringing the amorphous silicon film containing boron into contact with a gas containing tungsten. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the gas containing tungsten is WF ₆ . 10. The amorphous silicon film containing boron is
One selected from the group consisting of a transition metal film, a transition metal densification or silicide film, an aluminum nitride film, a cobalt silicide film, and a titanium-tungsten alloy film formed on the surface of the semiconductor substrate in the opening. The method for manufacturing a semiconductor device according to claim 7, wherein the method is formed on one film. 11. The replacement with tungsten is performed after forming a film for preventing precipitation of tungsten on the surface of the amorphous silicon film. A method of manufacturing a semiconductor device according to item 1. 12. The method of manufacturing a semiconductor device according to claim 11, wherein the film for preventing the precipitation of tungsten is a silicon dioxide film. 13. The silicon dioxide film has a thickness of 1 to 3 n.
13. The method for manufacturing a semiconductor device according to claim 12, wherein m is m. 14. A step of forming a wiring having a predetermined shape on a semiconductor substrate, a step of forming an amorphous silicon film containing boron connecting desired plural portions of the wiring, and the amorphous silicon film. 2. Amorphous silicon film is formed by the chemical vapor deposition method according to claim 1, further comprising the step of irradiating a desired portion of the wiring with an energy beam to conduct or open a desired plurality of portions of the wiring. A method for manufacturing a semiconductor device, comprising: