JPH0520767B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a power control circuit system for controlling power to a power supply unit group of a main unit and peripheral devices of an electronic device.

(b) Conventional Background In recent years, as the performance and functionality of electronic equipment such as information processing equipment and information communication processing equipment has improved, the power control systems of electronic equipment have also become more sophisticated and sophisticated. The power supply control of these electronic device power control systems varies depending on the configuration scale of the electronic device, but it includes everything from power on/off control, monitoring control of power supply voltage and current, and security alarms for power supply systems, peripheral devices, input/output devices, etc. As the number of peripheral devices, input/output devices, etc. to be controlled increases, power supply control becomes more complex and high performance is required.

For large models of electronic equipment, a method is often adopted in which the power supply control system is divided into a main control system and a subordinate control system, but for small and medium-sized models, it is important to consider the cost of capital investment and profitability. Considering,
Generally, a method is adopted in which power is controlled all at once, and the power on/off of the main power supply unit of the main device and the peripheral device power supply unit of the peripheral device is also controlled all at once.

(c) Prior Art and Problems The conventional power control system for small and medium-sized models of this type will be explained below. FIG. 1 shows a block diagram of a conventional power on/off control circuit configuration. Main unit power supply unit group 1a...1n (hereinafter referred to as MF-PWR1a
...1n) and peripheral device power supply unit groups 2a...2n (hereinafter abbreviated as I/OPWR2a...2n). an off interface unit 3 (hereinafter abbreviated as ON/OFFINF-3); and an on/off reception gate circuit 4 (hereinafter abbreviated as GATE-4) that creates a power on/off signal based on the received power on/off instruction signal. ,
Mode flip-flop circuit 5 (hereinafter referred to as
(abbreviated as FF-5) and MF-PWR1a...1n
Shift register 6 (hereinafter referred to as REG
6), the main body power supply unit interface section 7 (hereinafter abbreviated as MFPWR-INF7) that transmits and receives signals to the MF-PWR1a...1n, and the I/OPWR2a...2n that transmits and receives signals. A peripheral device power supply unit interface unit 8 (hereinafter abbreviated as I/OPWR-INF-8), a basic clock generation circuit 9 that creates a sequence clock for REG6, and a counter
Consists of 0.

In Figure 1, in response to the power-on instruction command of MF-PWR1a...1n and I/ORWR2a...2n, the power-on instruction signal is sent from ON/OFFINF-3.
A power-on signal is sent to GATE-4, and a power-on signal is sent from GATE-4 to which the power-on instruction signal is input.
This power-on signal is held in FF-5, and the power-on signal from FF-5 activates the power-on sequence control of REG6.
...1n each power supply unit and I/OPWR-INF
-8, power is sequentially applied to each power supply unit of I/OPWR2a...2n.

Next, ON/OFFINF is activated by the power-off instruction command.
-3 sends a power-off instruction signal to GATE-4, and GATE-4 receives the power-off instruction signal.
sends a power-off signal from the
Hold with FF-5, cut signal from FF-5
Activate the REG6 power-off sequence control,
By sequence control of REG6, I/OPWR-
Each power supply unit of I/OPWR2a...2n is connected via INF-8, and MF-
Turn off the power to each power supply unit of PWR1a...1n in sequence.

FIG. 3 shows a time chart of power on/off in a conventional circuit. The MF side is the main unit's MF
-PWR1a...1n, I/O side is I/OPWR2a
...2n time chart is shown, and when the power is turned on and the command is turned on, MF-PWR1a → MF-PWR1b,
Turn on the power sequentially by sequence control of REG6, and after turning on the power of MF-PWR1n, turn on the I/
The power is turned on in sequence from OPWR2a to I/OPWR2b, and the last I/OPWR2n is turned on to put the device into operation. Next, with the power off command, I/OPWR2n → I/OPWR2
Turn off the power in the order of n-1, and after turning off the power to I/OPWR2a, MF-PWR1n → MF-PWR
Turn off the power in the order of 1b, and finally MF-PWR1
Turn off the power to a and stop the operation of all devices.

Therefore, in this conventional power on/off circuit, since the main unit functions such as the processing function and the main memory function of the main unit are checked independently, even when you want to use only the main unit in the operating state, peripheral devices cannot be checked. This had the disadvantage that power was turned on to all power supply units, consuming power in vain.

(d) Object of the invention The present invention aims to solve this conventional drawback.

(e) Structure of the invention Powering on the power supply unit groups 1a to 1n of the main body/
Main body shift register with function to sequence control disconnection and power supply unit groups 2a to 2 of peripheral devices
The peripheral device shift register has a function of sequentially controlling the power on/off of the main unit, and means for creating a power control signal to instruct these control units to operate. When receiving a power-on instruction, the main body shift register immediately powers on the main power supply unit groups 1a to 1n in this order, and then sends a signal to the peripheral device shift register to turn on the power supply unit groups 1a to 1n in this order. When the main body shift register 17 is set to a startable state and an instruction to turn off the power to the main body device is received, the main body shift register immediately sends a signal to the peripheral device shift register to place the peripheral device shift register 17 in a startable state. At the same time, the main power supply unit groups 1n to 1a are turned off in this order, and when the peripheral device power supply unit groups 2a to 2n are powered on, the peripheral device shift register is changed to a state in which it is not possible to start. , the peripheral device shift register immediately switches to the peripheral device power supply unit group 2.
n to 2a are turned off in this order, and when an instruction to turn on the power to the peripheral device is received, the peripheral device shift register is activated. When the device power supply unit groups 2a to 2n are powered on in this order, and an instruction to power off the peripheral device is received, the peripheral device shift register immediately turns off the power to the peripheral device power supply unit groups 2n to 2a in this order. A power supply control circuit system characterized by:

That is, the power control signal generation means that generates whether to power on/off the power supply unit group of the main unit or the power supply unit group of the peripheral device issues an instruction to power on/off the power supply unit group of the main unit and the peripheral device. If they occur at the same time, turn on the power to the main unit power unit group, then turn on the power to the peripheral device power unit group, and when disconnecting, turn off the main unit power unit group and the peripheral device power unit group at the same time, so that the main unit power unit group Power on/off of the power supply unit group of the peripheral device is enabled only when the power supply unit group of the peripheral device is turned on, and when an instruction to disconnect the main power supply unit group is received, both the main body power supply unit group and the peripheral device power supply unit group are controlled to be disconnected. Therefore, it is possible to check various functions of the main unit without supplying power to multiple power supply unit groups of peripheral devices, thereby providing a power saving method that does not consume power from the power supply unit groups of peripheral devices. be.

(f) Embodiment of the Invention An embodiment of the present invention will be described below. Second
The figure shows a block diagram of a control circuit for power on/off according to the present invention, and in this figure, the same objects are designated by the same symbols as in FIG. 1. 11 is a counter, 12 is an on/off interface section (hereinafter ON/off interface section)
13 is an on/off reception gate circuit (hereinafter abbreviated as GATE13), 1
4 is a main body mode flip-flop circuit (hereinafter referred to as MF)
-FF-14), 15 is a main power supply unit shift register (hereinafter referred to as MF-REG15), 16 is a peripheral device mode flip-flop circuit (hereinafter referred to as I/O-FF16), and 17 is a Peripheral power supply unit shift register (hereinafter referred to as I/
(abbreviated as OREG17). The sequence signal from the counter 11 is connected to the MF-REG15 and I/
It is supplied to OREG17.

In Fig. 2, in response to a power-on instruction command to MF-PWR1a...1n and I/OPWR2a...2n, ON/OFFINF12 sends a main body power-on instruction signal and a peripheral device power-on instruction signal to GATE13.
Send to. In response to the main body power-on instruction signal input to GATE13, GATE13 sends a main body power-on signal to MF-FF-14, this main body power-on signal is held in MF-FF-14, and
Send input signal to REG15, MF-FF-14
Activates the power-on sequence control of the MF-REG15 by the power-on signal from the MF-REG15, and sequentially powers on each power supply unit of the MF-PWR1a...1n via the MFPWR-INF7 by the sequence control of the MF-REG15. The peripheral device power-on instruction signal input to GATE13 causes GATE
Peripheral device power-on signal from 13 to I/O-FF1
6 and sends this peripheral device power-on signal to the I/O
- held by FF16, sends a turn-on signal to I/OOEG17, activates power-on sequence control of I/OREG17 by the detection signal from I/O-FF16, and by sequence control of I/OREG17,
After turning on the power to MF-PWR1a...1n,
I/OPWR2a via I/OPWR-INF-8
...Turn on power to each power supply unit of 2n in sequence. Next, MF-PWR1a...1n and I/OPWR2
a... 2n power off instruction command turns on/off.
The main unit power disconnection instruction signal is sent from OFFFINF12.
The MF-FF-14
Sends the main unit power disconnection signal to MF-FF-14
holds the main body power-off signal, activates the power-off sequence control of MF-REG15, and MF-REG1
5 sequence control, MFPWR-INF7
The power to each power supply unit of MF-PWR1a...1n is sequentially cut off via Also, at the same time, ON/
Peripheral device power-off instruction signal is sent from OFFFINF12.
By the peripheral device power-off instruction signal sent to GATE13 and input to GATE13, I/O
Sends a peripheral device power-off signal to I/O-16.
FF16 holds the peripheral device power-off signal and
Activate the power-off sequence control of OREG17,
By sequence control of I/OREG17, I/
I/OPWR2a...2 via OPWR-INF-8
Turn off the power to each of the n power supply units in turn.

FIG. 4 shows a time chart when the main unit power supply unit group 1a...1n and the peripheral device power supply unit group 2a...2n are instructed to turn on or off the power at the same time. A time chart of the same object as the figure is shown. With the power-on command, the MF-REG15 sequence control turns on the power sequentially starting with the MF-PWR1a, and after the power-on of the MF-PWR1n is completed, the I/
By sequence control of ORES17, I/
The power is turned on in sequence from OPWR2a to I/OPWR2n-1, and the last I/OPWR2n is turned on, and the device enters the operating state. Next, with the power off command, the power on the MF-PWR1a...1n side is cut off by the sequence control of the MF-REG15.
Turn off the power in sequence from MF-PWR1n, and finally turn off the MF
-Turn off the power to PWR1a. At the same time, the I/OPWR2a...2n side power is cut off.
By sequence control of OREG17, I/
The power is turned off in order from OPWR2n to I/OPWR2n-1, and finally the power is turned off to I/OPWR2a.

As described above, in the circuit configuration according to the present invention,
MF-PWR1a...1n and I/OPWR2a...2n
MF-REG1 when power-on instructions come at the same time.
MF-PWR1a → MF- with sequence control of 5
Turn on the power in the order of PWR1n, then MF-PWR1a
...After turning on the power of 1n, the sequence control of I/OREG17 is activated, and I/OPWR2a → I/OPWR
Turn on the power in the order of 2n. If the power-off instructions come at the same time, use the sequence control of MF-REG15.
A sequence is built in so that the power is cut off in the order of MF-PWR1n→MF-PWR1a, and at the same time, the power is cut off in the order of I/OPWR2n→I/OPWR2a under sequence control of the I/OREG17.

FIG. 5 shows the main unit power supply unit groups 1a...1n in the power-on state and the peripheral device power supply unit groups 2a...2.
This shows a time chart when a power-on or power-off instruction is received for I/OPWR2a...2n only when MF-PWR1a...1n is powered on, and sequence control of I/OREG17. is activated, and the power is turned on or off in the same order as described above.

Figure 6 shows a time chart when the main unit power supply unit group 1a...1n and the peripheral device power supply unit group 2a...2n are powered on and an instruction to turn off the main unit power is received.
- There is no meaning unless the power of PWR1a...1n is turned on, so the MF
- Sequence control of REG 15 and I/OREG 17 is activated simultaneously, and the power is turned off in the same order as described above.

(g) Effects of the Invention As explained above, power on/off control of a power supply control device having a main unit power supply unit group and a peripheral device power supply unit group can be performed by controlling the peripheral device power supply unit group using the power supply control signal generating means. The circuit of the present invention, which is configured to operate with priority given to controlling the power supply unit group of the main unit, allows the power supply unit of only the main unit to be operated without turning on power to the power supply unit group of peripheral devices when checking the functions of the main unit. Since the power supply unit can be turned on and used, there is no need to wastefully supply power to the peripheral device power supply unit group, which has the effect of saving power.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional control circuit for powering on/off, FIG. 2 is a block diagram of a control circuit for powering on/off according to the present invention, FIG. 3 is a time chart for powering on/off by a conventional circuit, and FIG. 6 to 6 show time charts for various power on/off instructions according to the circuit configuration of the present invention. In the drawings, 1a...1n are main unit power supply unit groups, 2a...2n are peripheral device power supply unit groups,
3 and 12 are on/off interface parts, 4 and 1
3 is an on/off reception gate circuit, 5 is a mode flip-flop circuit, 6 is a shift register, 7 is a main body power supply unit interface section, 8 is a peripheral device power supply unit interface section, 9 is a basic clock generation circuit, 10 and 11 are counters, 14 is a main body mode flip-flop circuit, 15 is a main body shift register, 16 is a peripheral device mode flip-flop circuit, and 17 is a peripheral device shift register.

Claims (1)

[Scope of Claims] 1. A main body shift register 15 having a function of sequentially controlling the power on/off of the power supply unit groups 1a to 1n of the main body, and a sequence control of power on/off of the power supply unit groups 2a to 2n of the peripheral devices. The peripheral device shift register 17 includes a peripheral device shift register 17 having the function of , the main body shift register 15 immediately turns on the main power supply unit groups 1a to 1n in this order, and then sends a signal to the peripheral device shift register 17 to make the peripheral device shift register 17 ready for activation. When the main unit shift register 15 receives an instruction to turn off the power to the main unit, the main unit shift register 15 immediately sends a signal to the peripheral device shift register 17 to set the peripheral device shift register 17 to a state in which it cannot be activated. At the same time, the main power supply unit groups 1n to 1a are turned off in this order, and when the peripheral device power supply unit groups 2a to 2n are powered on, the peripheral device shift register 17 is turned off.
When the peripheral device shift register 17 is changed to a state where the peripheral device cannot be started, the peripheral device shift register 17 immediately turns off the power to the peripheral device power supply unit groups 2n to 2a in this order, and when receiving a power-on instruction for the peripheral device, The peripheral device shift register 17 is activated by the peripheral device power supply unit groups 2a to 2 only when the peripheral device shift register 17 is set to be activated.
n in this order, and upon receiving an instruction to turn off the power to the peripheral device, the peripheral device shift register 17 immediately turns off the power to the peripheral device power supply unit groups 2n to 2a in this order. Power supply control circuit system.