JPH0519920A - Bus fight preventing circuit - Google Patents

Abstract

PURPOSE:To prevent a through current between bus drivers by eliminating bus fight caused by the plural bus drivers. CONSTITUTION:A control signal generating circuit 20 detects that more than two enable signals are simultaneously made active and at such a time, control signals S1-Sn+1 are generated to enable only a bus driver 2n+1 fixing the input signal, for example. According to this signal, a bus 10 is clamped to the fixed input level of the bus driver 2n+1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus fight prevention circuit, and more particularly to a bus fight of a bus system having a plurality of bus drivers each of which is controlled to an enable state by an enable signal and derives a corresponding input signal to a common bus. Regarding the prevention circuit.

[0002]

2. Description of the Related Art In a conventional bus system configuration, as shown in FIG. 7, input signals 11 to 1n are input and bus drivers 21 to 2n are controlled to be in an enabled state by corresponding enable signals 31 to 3n, respectively. These bus driver 2
Common bus 10 commonly driven by all outputs 1 to 2n
Includes and.

In such a conventional bus configuration, each control of the bus drivers 21 to 2n can be performed randomly regardless of the states of other enable signals. That is, data transfer to the bus 10 may be performed by two or more bus drivers. Therefore, if different data are sent to the bus at two or more locations, a bus fight will occur, which will increase the current consumption and destroy the device.

[0004]

SUMMARY OF THE INVENTION Therefore, the present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object of the present invention is to prevent a bus fight by preventing two or more bus drivers from being enabled at the same time. To provide a circuit.

[0005]

According to the present invention, there is provided a bus fight prevention circuit in a system having a plurality of bus drivers, each of which is controlled to an enable state by an enable signal to derive a corresponding input signal to a common bus. In addition to the plurality of bus drivers, an additional bus driver having an input signal fixed and an output connected to the common bus and an enable signal for all of these bus drivers are used as inputs. When the enable signal is activated alternatively, the activated enable signal is supplied to the corresponding bus driver, and when the enable signal is activated more than two times, only the predetermined bus driver is provided with the above-mentioned. A control means for controlling to supply an activated enable signal. That bus fight prevention circuit is obtained.

[0006]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and the same parts as those in FIG. 7 are designated by the same reference numerals. The enable signals 31 to 3n of the bus drivers 21 to 2n are all input to the control signal generation circuit 20, and logical operation processing is performed to generate n + 1 control signals S1 to Sn + 1.

Of the control signals, n signals S1 to Sn are used as enable signals for the bus drivers 21 to 2n, and the other signals S1 to Sn are used.
The book signal Sn + 1 serves as an enable signal for the added bus driver 2n + 1. This additional bus driver 2n
It is assumed that the +1 input signal is fixed to the logic "0" or "1".

The control signal generation circuit 20 generates control signals S1 to Sn + 1 for enabling only a specific bus driver when two or more enable signals are activated at the same time. ing. Specific examples of the control signal generating circuit 20 are shown in FIGS. 2 to 6, respectively.

Referring to FIG. 2, this circuit is an example of high enable, and an adder circuit 41 for adding control inputs D1 to Dn (31 to 3n) and a logic "1" when this addition output is "1". And a comparator circuit 51 that outputs "0" at other times.

Further, it is turned on / off by this comparison output,
It includes AND gates 61 to 6n to which corresponding enable signals D1 to Dn are input, and a NOT gate 71 to output a negative logic of the output of the comparison circuit 51, and the outputs of the AND gates and the NOT gates are control signals S1 to Sn +. It is 1.

In this structure, the control inputs D1 to Dn
When only one of them becomes "1" and becomes active, the output of the adder circuit 41 becomes "1". Therefore, the comparison circuit 51
Of the AND gates 61 to 6 since the comparison output of is "1".
All n are turned on, and as a result, an active control signal is derived to enable the corresponding bus driver.

When more than one control signal is active,
Since the output of the comparison circuit 51 is "0", all the AND gates 61 to 6n are turned off and all the control signals D1 to Dn are not output. However, the output S of the knot gate 71
Only n + 1 becomes "1", so that only the corresponding bus driver 2n + 1 is enabled.

When all the control signals are "0", the output of the comparison circuit 51 is "0". Therefore, as in the case where two or more control signals are activated, the input signal becomes Only the fixed bus driver 2n + 1 is enabled and the potential of the bus 10 is clamped to the fixed input potential.

Referring to FIG. 3, this circuit is an example of low enable. Therefore, OR gates 81 to 8n are used instead of the AND gate of FIG. 2, and the comparison circuit 52 determines that the addition result of the addition circuit 41 is "n". When it is -1, it outputs a logic "0", and otherwise outputs "1". Other configurations are shown in FIG.
Is the same as that of.

In such a configuration, the control signals 31 to 3n
When only one of them becomes "0" and becomes active, the addition result of the adding circuit 41 becomes "n-1", and therefore the output of the comparing circuit 52 becomes "0". Therefore, the OR gate 81
All of 8n are turned on, the active control signal is derived, and the corresponding bus driver is selectively enabled.

Otherwise, the output of the comparison circuit 52 is "1".
Therefore, all of the OR gates 81 to 8n are turned off, and only the output Sn + 1 of the NOT gate 71 becomes “0”,
Becomes low active. Therefore, only the bus driver 2n + 1 whose input is fixed is enabled in FIG.
Is the same as the example.

Referring to FIG. 4, this example is a high enable circuit. The half adders 91 to 9n have an n-stage cascade structure, and the input A of the half adder 91 at the first stage is "0" and the input B is the control signal D1. After the next stage, the output S of the previous stage becomes the input A, and the control signal Di corresponding to the input B is applied.

Each carry output C is input to the NOR gate 101, and the NOR gate outputs are AND gates 61 to 6n.
And the inputs to the NOT gate 71, and the others are the same as the examples of FIGS.

In such a configuration, when two or more control signals D1 to Dn become "1", the carry output C of one of the half adders becomes "1", and the output of the NOR gate 101 becomes "0". Become. Therefore all AND gates 61
6n are turned off, only the output of the knot gate 71 becomes "1", and the bus driver 2n + whose input is fixed
Only 1 is enabled.

Referring to FIG. 5, there is shown a high-enable circuit example in which one of the inputs receives a corresponding control signal of the control signals D1 to Dn, and the other input has two "0" in the first stage. The OR gates 181 to 18n which receive the logical sum output from the preceding stage as the input from the second stage onwards and "0" as the input to the first stage and the OR gates 181 to 18n from the previous stage after the second stage
Not gates 171 to 17n + 1 having the output of n as an input are included.

The outputs of the NOT gates 171 to 17n serve as the control inputs of the corresponding AND gates 61 to 6n. The output of the knot gate 17n + 1 is the signal S as it is.
It is n + 1.

When two or more control signals D1 to Dn become "1", each OR gate gives a priority order such that D1>D2>...> Dn and only one enable signal is generated. Is 0, only the bus driver 2n + 1 whose input signal is fixed is enabled.

Referring to FIG. 6, there is shown a low-enable circuit example. AND gates 361 to 36n are used instead of the OR gates 181 to 18n of FIG. 5, and the AND gate 61 of FIG.
OR gates 81 to 8n are used instead of .about.6n. The other structure is the same as that of FIG. 5, and the operation is also the same.

[0025]

As described above, according to the present invention, it is possible to selectively enable and control only one bus driver which has detected that two or more enable signals for the bus driver have become active. Since more than one bus driver is not enabled at the same time,
There is an effect that it is possible to prevent a through current between the bus drivers.

[Brief description of drawings]

FIG. 1 is a block diagram showing the principle of the present invention.

FIG. 2 is a circuit diagram showing an example of a control signal generation circuit of FIG.

FIG. 3 is a circuit diagram showing another example of the control signal generation circuit of FIG.

FIG. 4 is a circuit diagram showing still another example of the control signal generation circuit of FIG.

5 is a circuit diagram showing another example of the control signal generation circuit of FIG.

FIG. 6 is a circuit diagram showing still another example of the control signal generation circuit of FIG.

FIG. 7 is a configuration diagram of a conventional bus system.

[Explanation of symbols]

10 bus 20 Control signal generation circuit 21-2n + 1 bus driver

Claims (3)

[Claims] 1. A bus fight prevention circuit in a system having a plurality of bus drivers each of which is controlled to an enable state by an enable signal and is configured to derive a corresponding input signal to a common bus. An additional bus driver, which is additionally provided in addition to the driver and has an input signal fixed and an output connected to the common bus, and the enable signal is selectively supplied with the enable signals to all the bus drivers as inputs. When the enable signal becomes active, the enable signal is supplied to the corresponding bus driver, and when the enable signal becomes 2 or more active, the enable signal becomes active only in a predetermined bus driver. And a control means for controlling so as to supply Stop circuit. 2. The bus fight prevention circuit according to claim 1, wherein the predetermined bus driver is the additional bus driver. 3. The bus fight prevention circuit according to claim 1, wherein the predetermined bus driver is a bus driver having a higher priority.