JPH05189380A - Common data management system - Google Patents

Abstract

PURPOSE:To simplify common data management without lowering reliability in a common data management system in a multiprocessor system connecting plural processors in a ring form with a transmission line. CONSTITUTION:The system is provided with a transfer means 100 making common data shared by respective processors 1 to circulate between the respective processors in one direction by way of the transmission line 3 and making the respective processors to transfer common data coming from another processor to another processor without making a change, an obtaining means 200 obtaining coming common data in accordance with necessity and a change means 300 transferring changed common data in stead of unchanged common data. Besides, the system is provided with a transfer means 100, a holding means 400 obtaining coming common data every cycle which is previously specified to hold it and a change means 300.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a common data management system in a multiprocessor system in which a plurality of processors are connected in a ring by transmission lines.

[0002]

2. Description of the Related Art FIG. 6 is a diagram showing an example of a conventional multiprocessor system, and FIG. 7 is a diagram showing an example of transfer data in FIG.

The multiprocessor system shown in FIG. 6 has three sets of processors 1 (individual processors 1-1,
1-2 and the like) and a set of common data management processors 2 are connected by a transmission line 3 in a ring shape.

The transmission line 3 is connected to each processor 1.
Allows communication in a clockwise direction. In the multiprocessor system, a unique address A is given to each processor 1 and the common data management processor 2, and a global address GA is provided as an address common to each processor 1 and the common data management processor 2.

In each processor 1, a data transfer unit 1
1, the fixed memory 12 and the processing unit 13 are provided, but in FIG. 6, only the inside of the processor 1-2 is shown and the insides of the other processors 1-1 and 1-3 are omitted.

Further, in the common data management processor 2,
A data transfer unit 21, a fixed memory 22, and a data management unit 23 are provided. The data transfer unit 11 in each processor 1 and the data transfer unit 21 in the common data management processor 2 are connected to other processors 1 via the transmission line 3.
The address A given to the data transfer destination processor 1 (or the common data management processor 2) is added as a destination address RA to the data to be transferred to (or the common data management processor 2) and the own processor 1 (or the common data). The address A given to the management processor 2) is given as the source address SA and transmitted to the transmission line 3.

Further, the data transfer units 11 and 21 analyze the destination address RA added to the data arriving via the transmission path 3 and add the destination address RA or the global address GA which matches the own address A. The data that has been processed is received in the own processor 1 (or the common data management processor 2), and the data that does not match the own address A is transferred to another processor 1 via the same transmission line 3.

Common data CD shared by each processor 1
Are held in the fixed memory 22 in the common data management processor 2. Further, each processor 1 stores and holds the common data CD transferred from the common data management processor 2 in the fixed memory 12, respectively.
3 is a common data CD held in the fixed memory 12
Use to perform the required processing.

The common data CD can be changed only by the data management unit 23 in the common data management processor 2,
When the data management unit 23 changes a part of the common data CD held in the fixed memory 22 (hereinafter referred to as the common data changing unit VD), the common data changing unit VD is included.
The transfer data TD as shown in FIG.
To the processor 1-1 via the transmission line 3-1.

The transfer data TD includes a global address GA as a destination address RA and a source address SA.
Address A ₂₀ of the common data management processor 2 as
Further, the common data changing unit VD is included as data to be transferred.

The transfer data TD arrives at the processor 1-1 via the transmission line 3-1. In the processor 1-1, when the data transfer unit 11 identifies that the destination address RA of the transfer data TD is the global address GA, the transfer data TD is transmitted to the processing unit 13, and
Transfer to the transmission line 3-2.

The processing unit 13 includes a common data changing unit VD included in the transfer data TD transmitted from the data transfer unit 11.
Thus, the corresponding portion of the common data CD held in the fixed memory 12 is changed.

When the transfer data TD arrives from the transmission line 3-2 or 3-3, the processors 1-2 and 1-3 also hold the data in each fixed memory 12 in the same process as the processor 1-1. The corresponding part of the common data CD is changed and the transfer data TD is transferred to another processor 1 or the common data management processor 2.

In the common data management processor 2,
Since the transmission source address SA of the transfer data TD that the data transfer unit 21 arrives from the transmission path 3-4 is the address A ₂₀ of the own common data management processor 2, the transfer data TD transmitted by the own common data management processor 2 If it is identified, the received transfer data TD is discarded.

[0015]

As is apparent from the above description, in the conventional multiprocessor system, when the common data management processor 2 changes the common data CD, the common data change unit VD transfers the transfer data TD.
To each processor 1, and to the common data CD held by each processor 1, the transferred common data changing unit V
Since the common data CD modified by each processor 1 is completely matched with the common data CD of the common data management processor 2 because the modification by D has been made, the common data management is required. It's complicated.

In order to solve such a problem, each processor 1 does not hold the common data CD and the common data C is sent to the common data management processor 2 each time the common data CD is required.
Although it may be considered to use the common data CD that requests the transfer of D and is returned from the common data management processor 2, in the unlikely event that the common data management processor 2 fails,
If normal common data CD cannot be transferred to each processor 1, all the processors 1 cannot be processed, and the reliability of the multiprocessor system is deteriorated.

It is an object of the present invention to simplify common data management of the multiprocessor system without lowering reliability.

[0018]

FIG. 1 is a diagram showing the principle of the present invention. FIG. 1 (a) shows the principle of the present invention (claim 1), and FIG. 1 (b) shows the present invention (claim 1). The principle of item 2) will be shown.

In FIG. 1, 1 is a processor,
Reference numeral 3 is a transmission line, and a multiprocessor system is configured by connecting a plurality of processors 1 in a loop by the transmission line 3.

Reference numeral 100 is a transfer means provided in each processor 1 according to the present invention (claims 1 and 2). Reference numeral 200 is an acquisition means provided in each processor 1 according to the present invention (claim 1).

Reference numeral 300 is a changing means provided in each processor 1 according to the present invention (claims 1 and 2). Reference numeral 400 is a holding unit provided in each processor 1 according to the present invention (claim 2).

[0022]

Operation: Each processor 1 is a multiprocessor system.
Common data that is shared by each processor is unidirectionally circulated between the processors 1 via the transmission path 3.

The transfer means 100 transfers the common data arriving from the other processor 1 via the transmission line 3 to the other processor 1 via the transmission line 3 without any change.

The acquisition means 200 acquires common data that arrives from another processor 1 via the transmission path 3 as required. When changing the common data arriving from another processor 1 via the transmission line 3, the changing unit 300 transmits the changed common data via the transmission line 3 instead of the common data before the change. Transfer to another processor 1.

The holding means 400 acquires and holds the common data arriving from the other processor 1 via the transmission path 3 at every predetermined cycle. Therefore, according to the present invention (Claim 1), each processor acquires the common data constantly circulating through the transmission path as necessary, and each processor changes the common data as necessary. According to the present invention (Claim 2), each processor periodically holds the common data constantly circulating through the transmission path, and each processor stores the common data as necessary. Since it can be changed, common data matching processing is not required, and there is no fear that common data cannot be acquired unless the transmission path becomes incommunicable, common data management of the multiprocessor system is simple, and reliable. The property is also improved.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 2 is a diagram showing a multiprocessor system according to an embodiment of the present invention (claim 1), FIG. 3 is a diagram showing an example of transfer data in FIG. 2, and FIG. 4 is a diagram showing the present invention (claim 2). 5 is a diagram showing a multiprocessor system according to one embodiment, and FIG. 5 is a diagram showing an example of transfer data in FIG. 4. The same reference numerals denote the same objects throughout the drawings.

First, an embodiment of the present invention (claim 1) will be described with reference to FIGS. In FIG. 2, FIG.
A data transfer unit 14 is provided in each processor 1 as the transfer unit 100 in (a), and a data acquisition unit 161 is provided in the processing unit 16 as the acquisition unit 200 in FIG. 1 (a). The data changing unit 162 is provided in the processing unit 16 as the changing unit 300 in FIG.

2 and 3, transfer data TD as shown in FIG. 3 constantly circulates on each transmission line 3 every predetermined period. As shown in FIG. 3, in the transfer data TD, the cyclic data CA is added as the destination address RA and the invalid address is added as the source address SA to the common data CD shared by the processors 1.

In each processor 1, when the processing unit 16 does not use the common data CD, the data acquisition unit 1
Since 61 has not been started, the data acquisition instruction da is not transmitted to the data transfer unit 14, and the processing unit 16 does not need to change the common data CD.
Since the data change unit 162 is not activated, the data change instruction dv is not transmitted to the data transfer unit 14.

Taking the processor 1-2 as an example, the data transfer section 14 is in a state where the data acquisition instruction da and the data change instruction dv are not received, and the other processor 1-via the transmission line 3-2. Transfer data TD transferred from 1
Is transferred to another processor 1-3 via the transmission path 3-3 without being changed.

As described above, the transfer data TD circulates to each processor 1 via the transmission path 3 at every predetermined cycle. When it becomes necessary for the processing unit 16 of an arbitrary processor 1 (for example, 1-2) to execute the required processing by using the common data CD, the processing unit 16 determines the data acquisition unit 16
Start 1.

The activated data acquisition unit 161 transfers the data acquisition instruction da to the data transfer unit 14. The data transfer unit 14 which has received the data acquisition instruction da transmits the data to the transmission line 3
When the transfer data TD arriving from the processor 1-1 via -2 is received and it is identified that the cyclic address CA is added as the destination address RA, the transfer data T
D through processor 3 through transmission line 3-3 as usual
-3 and transfers the received transfer data TD to the processing unit 16.

The processing unit 16 extracts the common data CD from the transfer data TD transmitted from the data transfer unit 14, temporarily stores it in the buffer memory 15, and then uses the common data CD to execute a required process.

Next, an arbitrary processor 1 (for example, 1-
When it becomes necessary to change the common data CD in the processing unit 16 of 2), the processing unit 16 activates the data changing unit 162. The activated data change unit 162 transmits the data change instruction dv to the data transfer unit 14.

The data transfer section 14 includes a data changing section 162.
When the data change instruction dv is transmitted from the normal transmission line 3
Of the transfer data TD transferred from the processor 1-1 via the -2 to the processor 1-3 via the transmission line 3-3.
The transfer to the processing unit 16 is stopped, and it is transmitted to the processing unit 16.

In the same way as described above, the processing unit 16 receives the common data C from the transfer data TD transmitted from the data transfer unit 14.
After extracting D, temporarily storing it in the buffer memory 15, making a necessary change, and assembling the transfer data TD as shown in FIG. 3 in which the cyclic address CA is added as the destination address RA to the changed common data CD. After that, the data transfer unit 1
Communicate to 4.

Instead, the data transfer section 14 transfers the transfer data TD including the changed common data CD transmitted from the processing section 16 via the transmission path 3-3 to the processor 1-.
Transfer to 3.

Thereafter, each processor 1 includes a processor 1-
Transfer data TD including common data CD changed by 2
However, each processor 1 uses the modified common data CD by acquiring the cyclic transfer data TD.

As is apparent from the above description, according to the embodiment shown in FIGS. 2 and 3, the transfer data TD including the common data CD is constantly circulated on the transmission line 3, and each processor 1 is When the common data CD is needed, the cyclic transfer data TD is acquired and the common data CD is used, and any processor 1 that needs to change the common data CD replaces the common data CD before the change. Since the changed common data CD is circulated, the same common data CD can always be used without each processor 1 holding the common data CD.

Next, an embodiment of the present invention (claim 2) will be described with reference to FIGS. In FIG. 4, FIG.
The data transfer unit 14 is provided in each processor 1 as the transfer unit 100 in (b), and the data holding unit 163 is provided in the processing unit 16 as the holding unit 400 in FIG. 1 (b). The data changing unit 162 is provided in the processing unit 16 as the changing unit 300 in FIG.

4 and 5, transfer data TD as shown in FIG. 5 constantly circulates on each transmission line 3. As shown in FIG. 5, the transfer data TD has the destination address RA in the common data CD shared by the processors 1.
Is added as a global address GA, and an invalid address is added as a source address SA.

In each processor 1, the processor 1
2 is taken as an example, in the state where the data acquisition instruction da and the data change instruction dv have not been transmitted from the processing unit 16, the data transfer unit 14 transmits another data via the transmission line 3-2 as described above. The transfer data TD transferred from the processor 1-1 is transferred to another processor 1-3 via the transmission path 3-3 without being changed.

As described above, the transfer data TD circulates in each processor 1 via the transmission path 3.
In each processor 1, the processing unit 16 activates the data holding unit 163 every predetermined period.

Taking the processor 1-2 as an example, the data holding unit 163 transmits the data acquisition instruction da to the data transfer unit 14 each time it is activated. The data transfer unit 14 to which the data acquisition instruction da has been transmitted receives the transfer data TD arriving from the processor 1-1 via the transmission path 3-2,
When it is identified that the global address GA is added as the destination address RA, the transfer data TD is transferred to the processor 1-3 via the transmission path 3-3 as usual, and the received transfer data TD is transferred. It is transmitted to the processing unit 16.

The processing unit 16 extracts the common data CD from the transfer data TD transmitted from the data transfer unit 14, and stores and holds it in the fixed memory 12. As described above, in the fixed memory 12 of the processor 1-2, the common data CD similar to that included in the transfer data TD circulating on each transmission line 3
However, it is updated every predetermined period and held.

Similarly, in the processors 1 other than the processor 1-2, the common data CD is held in the fixed memory 12. Processing unit 16 of arbitrary processor 1
When it becomes necessary to execute the required processing using the common data CD, the processing unit 16 extracts the common data CD held in the fixed memory 12 and executes the required processing.

Next, an arbitrary processor 1 (for example, 1-
When it becomes necessary to change the common data CD in the processing unit 16 of 2), the processing unit 16 activates the data changing unit 162. The activated data change unit 162 transmits the data change instruction dv to the data transfer unit 14.

The data transfer section 14 includes a data changing section 162.
When the data change instruction dv is transmitted from the normal transmission line 3
Of the transfer data TD transferred from the processor 1-1 via the -2 to the processor 1-3 via the transmission line 3-3.
The transfer to the processing unit 16 is stopped, and it is transmitted to the processing unit 16.

In the same way as described above, the processing section 16 receives the common data C from the transfer data TD transmitted from the data transfer section 14.
After D is extracted and stored in the fixed memory 12, the necessary change is made and then stored again in the fixed memory 12, and the changed common data CD is added with the global address GA as the destination address RA. After assembling the transfer data TD as shown in (4), it is transmitted to the data transfer unit 14.

The data transfer unit 14 transfers the transfer data TD including the changed common data CD transmitted from the processing unit 16,
Transfer to the processor 1-3 via the transmission path 3-3.
Thereafter, the transfer data TD including the common data CD changed by the processor 1-2 is transmitted to each processor 1 by the transmission line 3
Each processor 1 acquires the cyclic transfer data TD and stores the cyclic transfer data TD in the fixed memory 12 at every predetermined cycle, so that the modified common data CD in each fixed memory 12 is stored. Will be held.

The source address SA of the transfer data TD
Is an invalid address that is not any address A,
Unless one of the processors 1 assembles the transfer data TD including the changed common data CD, the processor 1 keeps circulating among the processors 1.

As is apparent from the above description, according to the embodiment shown in FIGS. 4 and 5, the transfer data TD including the common data CD is constantly circulated on the transmission line 3, and each processor 1 is An arbitrary processor 1 that periodically updates the common data CD held therein by the circulating common data CD and needs to change the common data CD,
Since the modified common data CD is circulated instead of the unmodified common data CD, each processor 1 can periodically use the updated common data CD.

It is to be noted that FIGS. 2 to 5 are merely examples of the present invention (claims 1 and 2), and for example, the number of processors 1 constituting a multiprocessor system is not limited to four. However, many other modifications can be considered, but in any case, the effect of the present invention does not change. Further, the configuration in each processor 1 is not limited to that shown in the drawing, and many other modifications may be considered, but in any case, the effect of the present invention does not change.

[0054]

As described above, according to the present invention (Claim 1), each processor acquires, as necessary, the common data constantly circulating through the transmission line, and each processor also receives the common data. According to the present invention (Claim 2), each processor periodically holds the common data that constantly circulates via the transmission line, and each processor needs it. Since the common data can be changed accordingly, there is no need to perform common data matching processing, and there is no risk that common data cannot be acquired unless the transmission path becomes incommunicable, and common data management of the multiprocessor system is also possible. It will be simpler and more reliable.

[Brief description of drawings]

FIG. 1 is a diagram showing the principle of the present invention, wherein FIG. 1 (a) shows the principle of the present invention (claim 1), and FIG. 1 (b) shows the principle of the present invention (claim 2).

FIG. 2 is a diagram showing a multiprocessor system according to an embodiment of the present invention (claim 1).

FIG. 3 is a diagram showing an example of transfer data in FIG.

FIG. 4 is a diagram showing a multiprocessor system according to an embodiment of the present invention (claim 2).

5 is a diagram showing an example of transfer data in FIG.

FIG. 6 is a diagram showing an example of a conventional multiprocessor system.

7 is a diagram showing an example of transfer data in FIG.

[Explanation of symbols]

 1 Processor 2 Common Data Management Processor 3 Transmission Lines 11, 14, 21 Data Transfer Section 12, 22 Fixed Memory 13, 16 Processing Section 15 Buffer Memory 23 Data Management Section 100 Transfer Means 161 Data Acquisition Section 162 Data Change Section 163 Data Holding Section 200 acquisition means 300 changing means 400 holding means

Front page continuation (72) Inventor Haruhiko Sekizawa 3-9-18 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa Fujitsu Communication Systems Limited

Claims (2)

[Claims] 1. In a multiprocessor system in which a plurality of processors (1) are connected in a loop by a transmission line (3), common data shared by each processor (1) is passed through the transmission line (3). And makes a change in the common data that arrives at each processor (1) from another processor (1) via the transmission path (3). Transfer means (100) for transferring to another processor (1) without passing through the transmission path (3)
An acquisition unit (200) for acquiring common data, which arrives from the other processor (1) via the transmission path (3), as necessary, and the transmission path (3) from the other processor (1). ), The changed common data is transferred to another processor (1) via the transmission line (3) instead of the common data before the change when the common data arriving via And a changing means (300) for changing the common data management method. 2. In a multiprocessor system in which a plurality of processors (1) are connected in a loop by a transmission line (3), common data shared by each processor (1) is passed through the transmission line (3). To make a change in the common data arriving from each of the processors (1) from the other processor (1) via the transmission path (3). Transfer means (100) for transferring to another processor (1) without passing through the transmission path (3)
A holding unit (400) for acquiring and holding the common data arriving from the other processor (1) via the transmission path (3) at a predetermined cycle, and the other processor (1) ) To the common data arriving via the transmission line (3), the changed common data is replaced with other common data via the transmission line (3) instead of the common data before the change. A common data management system, characterized in that a change means (300) for transferring to the processor (1) is provided.