JPH05182473A - Programmable read only memory - Google Patents

Abstract

PURPOSE:To reduce a drain turn-on leakage current flowing into a nonselective cell and to improve write efficiency by applying a negative voltage to a nonselective word line at a write mode. CONSTITUTION:A selective cell CL22 applied by a positive bit line voltage VBT2 and a positive high word line voltage VWD2 becomes a data writing state. On the other hand, the nonselective cell CLl2 connected to a bit line LB2 and which the word line voltage VWD1 of a negative voltage is applied by a word line LW1 is charged to a negative voltage. Thus, the drain turn-on leakage current is reduced since a floating gate is charged to a negative voltage even when the cell CL22 is an erasing cell and whose threshold value is low. Thus, the leakage current flows into the nonselective cell unwantedly at the time of writing the data on the selective cell is suppressed and the write efficiency is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable read only memory, and more particularly to an erasable programmable read only memory,
EPROM), batch electrically erasable programmable read-only memory (flash electrically erasable programa)
ble read only memory, flash EEPROM) and is suitable for writing data.

[0002]

2. Description of the Related Art Conventionally, as a so-called 1-cell 1-transistor type EPROM or flash EEPROM, for example, flash EEPROM 1, there are n-channel MOS transistors each having a floating gate FG and a control gate CG, as shown in FIG.
The drain D is sequentially connected to the first, second, ... bit lines L _B1 , L
_A plurality of cell groups connected to _B2 , ..., That is, cells (CL11, CL21, ...), (CL12, CL2
, ...), and the first, second, ... th cells (CL11, CL12, ...) Of each cell group (CL21, C).
L22, ...) the control gates CG forward as soon as 1 ..., second ... th word line L _W1, L _W2 by connecting to ..., bit line L _B1 cells as a whole in a matrix, L _B2 ... And word lines L _W1 , L _W2 .

The flash EEPROM 1 has a plurality of bit lines L _B1 , L _B2, ..., Bit line voltages V _BT1 , V _{BT2 ,.}
Is applied to one of them or the word line voltage V _WD1 , V _WD2 is applied to the word lines L _W1 , L _W2 ,. A cell is selected, and thus, channel photoelectrons are injected according to the data to be written into the floating gate FG of the selected cell in the write mode, so that the data is held in the cell as the injected charge amount of the floating gate FG. Has been done.

For example, as shown in FIG. 5, when a positive voltage is applied to the bit line L _B2 and a positive high voltage is applied to the word line L _W2 , the channel is applied to the floating gate FG of the MOS transistor forming the cell CL22. Hot electrons are injected.

[0005]

In this way, however, a plurality of bit lines L _B1 , L _B2 ... And word lines L _W1 , L _{W1 are formed} .
_When one cell, for example cell CL22, is selected from _W2 ... To inject channel photoelectrons, the positive bit line voltage V _BT2 applied to select the bit line L _B2 is the selected cell. CL22 drain D
Is also supplied to the drains D of the other non-selected cells CL12, CL32, ... Connected to the bit line L _B2. If this happens, the drain turn-on leak current I _DT0 will flow unnecessarily in this cell.

Incidentally, as shown in FIG. 6, a non-selected cell CL
12, CL32 ... Is given a positive drain voltage V _D to the drain and 0 to the control gate CG.
The control gate voltage V _CG of [V] is applied and the source voltage V of the ground voltage (0 [V]) is applied to the source.
_S is given. Under such a voltage condition, a positive charge is induced in the floating gate through capacitive coupling between the drain D and the floating gate,
When the cell is an erased cell, the drain turn-on leak current I is low because the threshold voltage is low.
_DT0 flows between the drain D and the source S.

When the drain turn-on leak current I _DT0 flowing in the non-selected cell becomes large, this means that the write efficiency is not good because the current required for writing in the selected cell becomes large.

The present invention has been made in consideration of the above points, and an object thereof is to propose a programmable read only memory capable of effectively suppressing a leak current flowing in a non-selected cell.

[0009]

In order to solve the above problems, in the present invention, each floating gate F
Multiple erase type M having G and control gate CG
A plurality of cells are formed by connecting the OS transistors to a common bit line, and the floating gate FG is charged by applying a selection voltage through the word lines respectively connected to the control gates CG of the plurality of erase type MOS transistors. In a programmable read-only memory configured to inject the memory cell with the memory cell and thereby write the stored data, during the write operation, the control gate CG of the second cell other than the first cell to which the selection voltage is applied is passed through the word line to the control gate CG. A suppression voltage that suppresses the drain turn-on leak current I _DT0 is applied to the second cell.

[0010]

[Operation] In the programmable read-only memory,
A negative voltage is applied to the unselected word line in the write mode. Therefore, the drain turn-on leak current _IDT0 flowing into the non-selected cell can be sufficiently reduced in practical use.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail with reference to the drawings.

In FIG. 1 in which parts corresponding to those in FIG. 4 are designated by the same reference numerals, the flash EEPROM 11 has a word line voltage V of 0 [V] for the non-selected word lines L _W1 , L _W3 , ... In FIG. Other parts are configured in the same manner as in the case of FIG. 5, except that instead of giving _WD1 , V _WD3 , ..., Negative voltage of a value up to about −1 [V] is given, for example. ing.

In the above structure, the selected cell CL22, to which the positive bit line voltage V _BT2 and the positive high voltage V _WD2 are applied, is connected to the floating gate FG in the same manner as described above with reference to FIG. Channel photoelectrons are injected, so that data is written.

On the other hand, the non-selected cells CL1 connected to the bit line L _B2 and _{supplied with the} negative word line voltages V _WD1 , V _WD3, ... By the word lines L _W1 , L _W3 .
2, CL32 ... As shown in FIG. 2, the drain _D is given a positive drain voltage V D, and the floating gate FG is positively charged through the capacitance between the drain D and the floating gate FG. Induce an electric charge. At the same time, a negative charge is induced in the floating gate FG through the capacitance between the control gate CG and the floating gate FG, which neutralizes the positive charge induced from the drain D, and a negative voltage. Charge up to.

Therefore, at this time, even if the selected cell CL22 is an erased cell and the threshold value is low, the drain turn-on leakage current I _DT0 is further increased because the floating gate FG is charged to a negative voltage. Reduce. As a result, when writing data to the selected cell CL22, it is possible to further suppress the leak current that flows unnecessarily in the non-selected cells CL12, CL32, ..., It is possible to further improve the writing efficiency of the flash EEPROM 11.

According to the above construction, the flash EEPR
Since the drain turn-on leakage current I _DT0 flowing in the MOS transistors of the non-selected cells CL12, CL32, ... Other than the selected cell CL22 during the writing of the OM11 can be reduced, the overall writing efficiency can be further improved.

In addition to this, since the drain turn-on leak current can be suppressed, the threshold voltage of the MOS transistor constituting each cell can be lowered, so that the read current of the flash EEPROM 11 as a whole can be remarkably increased as compared with the conventional case. Can be increased.

The row decoder circuit 21 of FIG. 3 can be applied to apply a positive high voltage or a negative voltage to a desired word line among the word lines L _W1 , L _W2 ....

The negative voltage decoder 22 includes word lines L _W1 and L _W2.
... so that a negative voltage can be applied to each word line as needed, and the word lines L _W1 , L
_W2 ... Positive high voltage decoder 24 via negative voltage blocking transistor circuit 23 of PMOS transistor configuration
Are connected.

In the configuration of FIG. 3, when an arbitrary cell, for example, the cell CL22 is selected as the selected cell, the positive high voltage decoder 24 applies a positive high voltage to the word line L _W2 connected to the selected cell CL22. Apply. At the same time, the negative voltage decoder 22 applies a negative voltage to the word lines L _W1 , L _W3, ... Connected to the non-selected cells CL12, CL32. Here, while a negative voltage is applied to L _W1 , L _W3, ... To the non-selected word lines, the corresponding transistor of the negative voltage blocking transistor circuit 23 operates to cut off the negative voltage to the positive high voltage decoder 24. It is designed not to be applied.

According to the row decoder circuit 21 having the configuration of FIG. 3, it is possible to select a desired cell as necessary and surely apply a positive high voltage or a negative voltage.

In the above embodiment, each cell is 1
The case where the present invention is applied to the flash EEPROM of the cell 1 transistor has been described, but the present invention is not limited to this, and can be similarly applied to the EPROM.

Further, in the above-mentioned embodiment, the word line selection signal of the negative voltage is applied to all of the non-selected cells CL12, CL32 ... However, the present invention is not limited to this, and some non-selected cells are selected. It is possible to obtain the same effect as in the above case by dividing the block into two and applying it to only a part thereof.

Further, in the above-described embodiment, the positive and negative voltages are applied to the selected cell and the non-selected cell, respectively. However, in the case of using the MOS transistor of the conduction type opposite to the above case, The polarity of the applied voltage may be reversed.

[0025]

As described above, according to the present invention, the negative voltage is applied to the non-selected word line in the write mode, so that the drain turn-on leak current flowing into the non-selected cell is practically sufficient. A programmable read-only memory that can be reduced can be easily realized.

[Brief description of drawings]

FIG. 1 is a flash EEPRO according to an embodiment of the present invention.
It is a connection diagram showing an equivalent circuit of M.

FIG. 2 is a connection diagram for explaining the operation.

FIG. 3 is a connection diagram showing a configuration of a row decoder circuit.

FIG. 4 is a connection diagram showing an equivalent circuit of a conventional flash EEPROM.

5 is a connection diagram for explaining the operation of the selected cell in FIG. 1. FIG.

FIG. 6 is a connection diagram for explaining the operation of the non-selected cell in FIG.

[Explanation of symbols]

1, 11 ... Flash EEPROM, 21 ... Row decoder circuit, 22 ... Negative voltage decoder, 23 ... Negative voltage blocking transistor circuit, 24 ... Positive high voltage decoder,
CL11, CL12, CL21, CL22 ... Cell, L
_B1 , L _B2 ... Bit line, L _W1 , L _W2 ... Word line.

Claims (1)

[Claims] 1. A plurality of erase type MOS transistors each having a floating gate and a control gate are connected to a common bit line to form a plurality of cells, and the cells are connected to the control gates of the plurality of erase type MOS transistors. In a programmable read-only memory configured to inject charges into the floating gate by applying a selection voltage through the selected word line and thereby write stored data, the first voltage applied with the selection voltage during a write operation A programmable read-only memory that applies a suppression voltage that suppresses a drain turn-on leak current to the second cell through the word line to the control gate of the second cell other than the second cell.