JPH05181445A - Horizontal synchronizing signal polarity discriminating circuit - Google Patents

Abstract

PURPOSE:To discriminate the polarity of a horizontal synchronizing signal by a multifrequency adaptive display synchronizing circuit. CONSTITUTION:The output of a delay circuit 1 which consists of a simple logic gate and inputs a vertical synchronizing signal fV is inputted to the CK of a D flip-flop 2 and the horizontal synchronizing signal fH is inputted to the D of the D flip-flop 2. The circuit is composed of simple logic gates without using any capacitor and only the synchronizing signal is inputted, so the IC- implementation is facilitated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing circuit for a multi-frequency display, and more particularly to a circuit for determining the polarity of a horizontal synchronizing signal.

[0002]

2. Description of the Related Art A conventional circuit is disclosed in JP-A-59-21077.
As described in No. 2, the polarity of the sync signal is determined by converting the sync signal into direct current by an integrator composed of a resistor and a capacitor.

[0003]

In the above-mentioned prior art, it is necessary to use a capacitor because the synchronizing signal is converted into a DC signal by an integrator. Therefore, there is a problem that it is difficult to form a circuit into an IC.

An object of the present invention is to facilitate the integration of a circuit into an IC without using a capacitor.

[0005]

The above object is to provide a delay circuit constituted by a simple logic gate having a vertical synchronizing signal as an input, and a D having an output of the delay circuit and a horizontal synchronizing signal as an input.
This is achieved by providing a flip-flop.

[0006]

The vertical synchronizing signal is input to the delay circuit composed of simple logic gates. By inputting the vertical synchronizing signal delayed by the delay circuit to the CK of the D flip-flop and inputting the horizontal synchronizing signal to D, an H or L level DC signal corresponding to the polarity of the horizontal synchronizing signal can be obtained. it can.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS.
This will be described with reference to FIG.

In FIG. 1, 1 is a delay circuit and 2 is a D flip-flop. The delay circuit 1 is composed of simple logic gates such as several stages of buffers or inverters.
A positive vertical synchronizing signal (hereinafter abbreviated as fV) shown in FIG. 2A is input to the delay circuit 1. The delay circuit 1 delays fV as shown in FIG. Here, the delay time is the horizontal synchronization signal shown in FIG.
Abbreviated as H. ) Pulse width. Next, the fV delayed by the delay circuit 1 is input to the CK of the D flip-flop 2, and the positive fH shown in FIG. Here, the pulse width of fV is an integral multiple of horizontal synchronization. Therefore, since both the rising and falling edges of fV delayed by the delay circuit 1 are when fH is at the H level as shown in FIG. 2, the D flip-flop 2
2 becomes high level as shown in FIG. 2D, and Q-N output becomes low level as shown in FIG. Similar results are obtained when a negative fV is input.

Similarly, when the negative fH is input as shown in FIG. 3, the positive fV shown in FIG. 3A is delayed by the delay circuit 1 as shown in FIG. 3C. And D
It is input to CK of the flip-flop 2. FH is input to D. Since fH is at the L level at both the rising and falling edges of the delayed fV, the QP output of FIG.
As shown in (D), it becomes L level, and Q-N output is shown in Fig. 3.
As shown in (E) of FIG. Similar results are obtained when a negative fV is input. Therefore, since the outputs Q-P and Q-N of the D flip-flop 2 change depending on whether the input fH is positive or negative, the polarity of fH can be determined.

As a second embodiment, as shown in FIG. 4, the Q-N output of the D flip-flop 2 and fH are set to E-O.
When input to the R gate 3, it is possible to always obtain a positive horizontal synchronizing signal regardless of the polarity of fH. Also, E
By connecting one input of the -OR gate 3 to the QP output of the D flip-flop 2, it is possible to always obtain a negative horizontal sync signal.

According to this embodiment, the polarity of the horizontal synchronizing signal can be determined without using a capacitor. Further, by using the horizontal sync signal polarity determination signal, it is possible to obtain a horizontal sync signal that is always positive or negative regardless of the polarity of the input horizontal sync signal.

[0012]

According to the present invention, the circuit configuration is a combination of simple logic gates without using a capacitor, and the input is only a synchronizing signal, so that it can be easily integrated into an IC.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is an operation waveform diagram of a circuit diagram showing a first embodiment of the present invention.

FIG. 3 is an operation waveform diagram of a circuit diagram showing a first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

[Explanation of symbols]

1 ... Delay circuit, 2 ... D flip-flop, 3 ... E-OR
Gate

Claims (2)

[Claims] 1. A gate for delaying a vertical synchronizing signal, and a D flip-flop for generating a DC signal corresponding to the polarity of the horizontal synchronizing signal, the gate output and the horizontal synchronizing signal being input. Horizontal sync signal polarity determination circuit. 2. An EO for always generating a positive or negative horizontal synchronizing signal from a DC signal corresponding to the polarity and the horizontal synchronizing signal regardless of the polarity of the horizontal synchronizing signal.
The horizontal synchronizing signal polarity discriminating circuit according to claim 1, further comprising an R gate.