JPH05175941A - Variable coding rate transmission system - Google Patents

Abstract

PURPOSE:To change an error rate in response to the importance of data in a frame with respect to the error correction system in the communication. CONSTITUTION:A coding section uses an S/P converter 11 to convert a serial signal into a parallel signal in K-bits, a coder 1 converts the parallel signal into a convolution code comprising N-bits of parallel data, n-sets of delay devices 2 delay n-bits in the parallel data in N-bits. Then (N-n) sets of FIFOs 3 delay (N-n) bits in N-bit parallel data by using a variable delay clock number, and n-sets of selectors 4 selects one of the delay devices 2 and one output of each FIFO3. Furthermore, a timing control section 34 controls write/read of the FIFO3 and the selection of the selector 4, an MUX35 multiplexes outputs of the n-sets of the selectors 4 and outputs the result to m-sets of transmission lines. A decoding section decodes the signal in the reverse order to that of the coding section to reproduce the original signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction method in communication, and when data having different importance levels are mixed in a frame, an error rate can be realized according to the importance level. It relates to a transmission method.

In a communication system using digital coded transmission, an error correction system in which a convolutional code is used to correct a code error on the receiving side is used in order to reduce a reception code error and improve the reliability of communication.

At this time, when data having different degrees of importance are mixed in a frame, it is required to realize an error rate according to the degree of importance in each data. this is,
This is because if the error rate in the frame is made uniform, the less important information is given more redundancy than necessary, and extra transmission power is required. Therefore, in recent years, the coding rate is changed according to the importance of information,
A variable coding rate transmission system is required.

In such a variable code rate transmission system, the number of encoders, decoders, and clock frequencies to be used does not increase even if the number of code rates increases, and therefore the circuit scale is large. It is demanded that it does not increase.

[0005]

2. Description of the Related Art FIG. 12 shows the structure of a conventional encoder, 11 is an S / P converter for converting an input serial signal into a parallel signal and outputting the parallel signal, and 12 is a K-bit input. R = K / N encoder for generating N-bit convolutional code with code rate R = K / N from signal, 13 _1, 13
_2, ..., 13 _J from N pieces of serial signal input having a uniform redundancy of the J to generate different J This serial signal redundancy _{Pankuchaddo, 14 1, 14 2, ...} , 14 J Is a FIFO, 15 is a 1 of J selector that selects one from J inputs and generates a serial output, and 16 is an S / P converter that converts a serial signal into m outputs.

In each punctured area, 17_1,1
7_2,… 17_NIs an L (1) bit input serial signal
S / P converter for converting to Larel signal, 18_1,18_2,… 、
18 _NSelects the H (1) bit from the L (1) bit signal
H1 of L1 selector to select, 19 input serial signal
It is a P / S converter that converts into a real signal.

An input serial signal of clock frequency f is
The S / P converter 11 converts each frame into a K-bit parallel signal at a clock frequency f / K, and R = K /
The N encoder 12 converts the K-bit signal into a coding rate R = K /
Convert to N, N-bit convolutional code. Where R
The coding rate R of the = K / N encoder 12 is selected to be smaller than the average coding rate r when the redundancy of the error correction code is variable.

Each punctured 13_1,Thirteen_2,…, 13_J
, R = K / N of N bits from encoder 12
The signals are received serially and the S / P converter 17_1,
17 _2,… 17_NAt the clock frequency f / {KL
(J)}, L (1) -bit parallel
Convert to a signal and output. Clock frequency f in this case
/ {KL (J)} is different for each punctured
There is.

H1ofL1 selector 18 _1, 18 _2, ..., 18 _N
Selects an L (1) -bit signal and outputs it, thereby generating an H (1) -bit output having redundancy according to the importance, and outputting each signal to the P / S converter 19 The clock frequency fNH (J) / {KL (J)} is converted into a serial signal and output. The clock frequency fNH (J) / {KL (J)} in this case also differs for each punctured.

Each punctured 13 _1, 13 _2, ..., 13 _J
Of the serial signal output of the FIFO 14 _1, 14 _2, ..., 14
_The serial signal shown in (A) is generated by writing to _J and reading at the clock frequency fn / K by first-in first-out and selecting one by one by the 1ofJ selector 15. Further, this serial signal is sent to the S / P converter 16
It is converted into m signals at the clock frequency (f / K) (n / m) and output.

FIG. 13 shows the structure of a conventional decoder. Reference numeral 21 is a P / S converter which converts an input parallel signal into a serial signal and outputs the serial signal, 22 is a FIFO and 23.
_1, 23 _2, ..., 23 _J from the serial signal input different J this redundancy, and outputs the N pieces serial signals having a uniform redundancy Pankuchaddo, 24 _1, ..., 24 _N is J
1 of J selector for selecting one from the input of books, 25 is an R = K / N Viterbi decoder for performing Viterbi decoding from a signal of code rate R = K / N, 26 is an R = K / N Viterbi decoder 25 It is a timing control unit that generates a computation prohibition signal.

FIG. 14 shows an example of a punctured structure in the decoder. In each punctured area, 27 is an S / P converter that converts an input serial signal into N sets of H (1) -bit parallel signals and outputs the parallel signals.
28 _1, ..., 28 _N are P / S converters for converting L (1) -bit parallel inputs into serial signals.

In the P / S converter 21, the input parallel signals 1 to m of the clock frequency (f / K) (n / m) are input.
Converted to serial signal at clock frequency fn / K, and
By writing to the IFO 22 and reading out at the clock frequency fNH (J) / {KL (J)} by first-in first-out,
Allocate and input to each of the J Punctures. Clock frequency fNH (J) / {KL (J)} in this case
Is different for each punctured.

Each punctured 23 _1, 23 _2, ..., 23 _J
, Serially receives signals having different degrees of redundancy from the FIFO 22, and the S / P converter 27 outputs N by the clock frequency f / {KL (J)}.
It is converted into an H (1) -bit parallel signal of a book and output. , H (1) +1, ..., L (1) are added to the respective H (1) -bit signals, and the H (1) -bit signals are respectively converted into P / S converters 28 _1, , 28 _N , and N serial signals having a uniform redundancy by the clock frequency f / K and output. The clock frequency f / {KL (J)} in this case also differs for each punctured.

Each punctured 23 _1, 23 _2, ..., 23 _J
In each of the N serial signal outputs of the above, one of the 1 signals is selected by the 1ofJ selector 24 ₁ , and one of the 2 signals is selected by the 1ofJ selector 24 ₂ , and each of the N signals is selected. The N signals obtained by selecting one from the signal of 1 by the 1ofJ selector 24 _N are input to the R = K / N Viterbi decoder 25.
1, in2, ..., inN added. In the R = K / N Viterbi decoder 25, by prohibiting the metric calculation of the erased bit portion of the punctured code according to the operation prohibition signals 1, 2, ... Performs the decoding operation to obtain the clock frequency f
Decode the original signal consisting of.

FIG. 15 is a diagram for explaining the encoding operation in the conventional system, and shows the case where the average encoding rate r = K / n. One frame of data before encoding is X
It consists of bits. This is an X / 2 bit A
When the importance of A is higher than that of B when divided into B and B, A is encoded at an encoding rate R = K / (n + a) and B is encoded at an encoding rate R = K / (n− When encoded in a), A after encoding has a surplus bit per K bits and B has b empty bits per K bit.

Therefore, in the coded data shown in (a) of FIG. 12, as shown in the figure, a portion having a small coding rate corresponding to A has {(n + a) / K} (X / 2) bits. And the part of the coding rate corresponding to B is
It is {(na) / K} (X / 2) bits, and it is shown that the data length changes.

[0018]

In the conventional method shown in FIGS. 12 to 15, a code generated by punctured coding when changing the redundancy of the error correction code according to the importance of information. The converted data is output as it is without changing the transmission order.

In this case, the clock frequency required in each part of the encoder and the decoder is different. Especially, in each punctured area, different clock frequencies are required for different coding rates.
Further, the length of data to be handled also differs depending on the coding rate.

Therefore, the components of the encoder and the decoder are required only for the type of coding rate, and the clock frequency is different, so that the number of clock generation circuits also increases according to the type of coding rate. Therefore, there has been a problem that the circuit scale is unavoidably increased.

The present invention is intended to solve such a problem of the prior art, and even if a method of changing the redundancy of the error correction code according to the degree of importance is used, the circuit scale is greatly increased. It is an object of the present invention to provide a variable coding rate transmission system which does not exist.

[0022]

FIG. 1 shows a principle configuration (1) of the present invention. According to the present invention, in a coding unit of a coding transmission system in which an input signal is converted into a convolutional code at a transmission side and is transmitted, and a convolutional code is received at a reception side by Viterbi decoding, digital data composed of serial signals is transmitted. To a K-bit parallel signal, an encoder 1 for converting the K-bit parallel signal to a convolutional code composed of N-bit parallel data, and an N-bit parallel data Of the N delay devices 2 that delay the n bits respectively, and (N−
(n) (N−n) FIFOs 3 each of which delays each bit with a variable delay clock number; and n selectors 4 that select one from any one of the delay devices 2 and the output of each FIFO 3, The timing control unit 34 that controls writing and reading in the FIFO 3 and the selection in the selector 4 and the MUX 35 that multiplexes the outputs from the n selectors 4 and outputs the multiplexed signals to the m transmission lines are provided. The timing control unit 34 dynamically controls the erasure bits in the code generated in the device 1, so that the surplus bits of the information portion having the coding rate smaller than the average coding rate in the frame are larger than the average coding rate. The coding rate information is embedded in the empty bits.

In this case, the timing controller 34 counts from the beginning of the frame at the operating clock frequency of the encoder 1, the output of the counter 36 as an address to write and read to each FIFO 3, and each selector. 4 and the ROM 37 which respectively generate the signals controlling the selection.

FIG. 2 shows the basic configuration (2) of the present invention. According to the present invention, in a decoding unit of a coded transmission system in which an input signal is converted into a convolutional code on the transmitting side and transmitted, and the convolutional code is Viterbi-decoded on the receiving side to receive the convolutional code. DEMUX 41 for converting a signal into n-bit parallel data, n selectors 5 for selecting one from the n-bit parallel data, and n FIFOs 6 for delaying the output of the selector 5 with a variable delay clock number. And a decoder 7 that Viterbi-decodes an input composed of a convolutional code, a writing and reading in the FIFO 6, and a timing control unit 26 that controls the selection in the selector 5, and the erasure in the code decoded in the decoder 7 The bit is controlled according to the erased bit on the encoder side.

In this case, the timing control unit 26 uses the n
A synchronization detector 44 that detects the beginning of a frame in a bit input signal, a counter 45 that counts from the beginning of this frame at the operating clock frequency of the decoder 4, and a write and read operation for each FIFO 6 using the output of the counter 45 as an address. , ROM 46 which respectively generate a signal for controlling selection in each selector 5.

[0026]

After converting the digital data consisting of the serial signal into the K-bit parallel signal, it is converted into the convolutional code consisting of the N-bit parallel data. A delay device delays each n bits of the N-bit parallel data, and a FIFO delays the N bits.
(N−n) bits of the parallel data of bits are delayed by varying the number of delay clocks. Then, one of the delay devices and one of the outputs of the respective FIFOs are selected, and this output is multiplexed and output to m transmission lines. At this time, in the convolutional code composed of N-bit parallel data, the surplus bits of the information portion having the coding rate smaller than the average coding rate in the frame are dynamically controlled by dynamically controlling the timing of the erasing bit. It is embedded in the empty bits of the information of the coding rate higher than the coding rate. Writing and reading in the FIFO and selection in the selector are controlled by the timing controller.

In this case, the timing control section reads and writes to each FIFO and selection by each selector by reading the output counted from the head of the frame at the operation clock frequency of the encoder as an address from the ROM. Generates respective signals to control.

Data obtained by converting signals from m transmission lines into n-bit parallel data, and 1 from this data
The convolutional code input, which is composed of data delayed by the variable number of delay clocks in the FIFO, is Viterbi-decoded in the decoder, and the erased bits in the decoded code are converted into erased bits in the encoder side. By doing so, the original signal is decoded. At this time, FI
Writing and reading in the FO and selection in the selector are controlled by the timing controller.

In this case, the timing control section detects the head of the frame in the input signal and counts from the head of the frame at the operation clock frequency of the decoder,
By reading the count output from the ROM as an address, writing and reading to and from each FIFO,
Signals are generated to control the selection in each selector.

[0030]

FIG. 3 shows the configuration of an encoder according to an embodiment of the present invention, in which the same elements as those in FIG. 12 are designated by the same reference numerals, 31 _1, 312 _2, ... _, 31 _n Is a delay device, 32
_1, 32 _2, ... _, 32 _Nn is a FIFO, 33 _1, 33 _2, ... _, 3
3 _n selects one from (N-n + 1) of signal 1of
(N-n + 1) selector, 34 is a timing control unit that generates a write signal (Write enable) and a read signal (Read enable) of each FIFO, and a select signal (Select signal) of each selector, and 35 is 1of (N -N + 1) MUX that multiplexes the output of the selector.

The input serial signal of clock frequency f is
The clock frequency f / for each frame in the S / P converter 11
Converted to a K-bit parallel signal by K, and R = K /
In the N encoder 12, the coding rate R = K from the K-bit signal
/ N, N-bit convolutional code y1, y2, ..., Y
Convert to n, y (n + 1), y (n + 2), ..., YN. Here, the coding rate R of the R = K / N encoder 12 is the average coding rate r when the redundancy of the error correction code is changed.
Selected to a smaller value.

The delay units 31 _1, 312 _2, ..., 31 _n are signals of low importance y1, y2 ,.
Are delayed by a fixed amount, for example, the same amount of delay. On the other hand, FI
FO32 _1, 32 _2, ..., 32 _Nn are highly important signals y (n + 1), y (n + 2), which are generated as a result of encoding.
, YN are delayed with a variable number of delay clocks and transmitted.

1 of (N-n + 1) selectors 33 _1, 33 _2, ...
_, 33 _n are each delay unit 31 _1, 31 _2, ..., 31 and the output of _n, the FIFO 32 _1, 32 _2, ..., 32 consisting of the output of _Nn (Nn + 1) of signal, one By selecting and outputting the signal of, the output out1, out2, ..., which consists of the data in which the surplus bits of the data with high redundancy are removed and the data in which the surplus data is embedded in the empty bits of the data with low redundancy generate outn. The timing control unit 34 uses the FIF at this time.
Writing and reading of O32 _1, 32 _2, ..., 32 _Nn ,
1 of (N-n + 1) selectors 33 _1, 33 _2, ... _, 33 _n are controlled.

The MUX 35 multiplexes the outputs of the 1of (N-n + 1) selectors 33 _1, 332 _, ... _, 33 _n , and outputs m number of outputs 1, 2, ..., Corresponding to the number m of channels of the communication path. generate m.

FIG. 4 is a diagram for explaining the encoding operation in the present invention, and shows the case where the average encoding rate r = K / n. When the pre-encoding data in which one frame consists of X bits is divided into A and B consisting of X / 2 bits, the importance of A is higher than the importance of B, and A is code rate R = When encoded with K / (n + a) and B is encoded with a coding rate R = K / (n−a), A after encoding is K
There are a surplus bits per bit, and B has a free bits per K bits.

In the present invention, as a result of inserting the surplus bits in the bits derived from A indicated by ● into the empty bits in the bits derived from B indicated by ○, the data derived from A and the data derived from B are inserted. Both data and (n / K) (X /
2) Bits, which are shown to have equal data length.

FIG. 5 shows an example of the structure of the timing control section in FIG. 36 is a counter,
Frequency f / K reset by frame pulse
Count the clock. 37 is a read only memory (ROM), which outputs the contents of the FI by using the count value of the counter 36 as an address.
Write signals (Writ of FO 32 _1, 32 _2, ..., 32 _Nn )
e enable) 1, 2, ..., N-n and read signal (Read
enable) 1, 2, ..., N-n, and 1 of (N-n +
1) Select signals of the selectors 33 _1, 33 _2, ... _, 33 _n (Select
signal) and are output.

FIG. 6 is a block diagram of a decoder according to an embodiment of the present invention.
The same as in FIG.
The same number, 41 is the multiplexing of m inputs 1, 2, ..., M
To generate n outputs 1, 2, ..., N
X, 42_1,42_2,…_,42_nIs a signal from n signals
1ofn selector for selecting signals, 43_1,43_2,…, 43 _n
Is a FIFO.

, M by the clock frequency (f / K) (n / m) are separated in the DEMUX 41 and output 1, 2, ..., N at the clock frequency f / K.
To generate R = K / N input of Viterbi decoder 25 in1,
Input in2, ..., in. On the other hand, the 1ofn selector 42 _1,
42 _{2, ...,} 42 _n, respectively FIFO 43 _1, 43 ₂ selects one signal from the n signal, ..., are input to 43 _n, by delaying the delay clock number variable, encoder The surplus bit inserted in the empty bit on the side is stored and read when decoding the information of the coding rate smaller than the average coding rate from the inputs in1, in2, ...
= Input of the K / N Viterbi decoder 25 in (n + 1), in (n
+2), ..., InN.

In the R = K / N Viterbi decoder 25,
Calculation prohibition signals 1, 2, ... From the timing control unit 26
Depending on N, the well-known Viterbi decoding operation is performed by prohibiting the metric calculation of the part of the erasure bit of the punctured code in the inputs in1, in2, ..., InN.
The original signal consisting of the clock frequency f is decoded. Figure 6
The input of the R = K / N Viterbi decoder 25 in FIG.
Is the same as in the conventional circuit shown in FIG.
The configuration of the K / N Viterbi decoder 25 is the same as in the case of FIG.

R = K / N operation prohibition signals 1, 2, ..., N in the Viterbi decoder 25 and the respective FIFOs 43 _1, 43
_2, ..., 43 _n Signals that specify the read / write timing,
, And selection signals of the _{1-of- n} selectors 42 _1, 42 _2, ... _, 42 _n are created in advance in accordance with the timing of encoding and stored in the ROM or the like.

FIG. 7 shows an example of the structure of the timing control section in FIG. Reference numeral 44 denotes a synchronization detector, which detects a frame pulse from n inputs 1, 2, ..., N. A counter 45 is reset by a frame pulse and counts a clock of frequency f / K. Reference numeral 37 is a read only memory (ROM), which outputs the contents of the count value of the counter 36 as an address so that the FIFO 43 _1, 432 _,
..., 43 _n write signals (Write enable) 1, 2,
..., N-n and read signals (Read enable) 1, 2,
..., N-n, and 1ofn selector 42 _1, 42 _2, ... _, 42
_n of the selection signal (Select signal) 1,2, ..., to generate a N-n.

FIG. 8 shows an encoder according to an embodiment of the present invention.
And the coding rate R = 1 /
3, the average coding rate r = 1/2, and the transmission path is QPS
An example in the case of 2 channels like K is shown. 51 is R
= 1/3 encoder, 52_1,52 ₂Is a delay device, 53 is FI
FO, 54_1,54₂Is 1 of 2 selector, 55 is timing
It is a control unit.

The R = 1/3 encoder 51 converts the input serial signal into 3-bit signals 1, 2 and 3 having different coding rates R = 1/3 and outputs the signals. Delay device 52 _1, 52
₂ delays the less important signals 1 and 2 resulting from the encoding. On the other hand, the FIFO 53 delays the highly important signal 3 generated as a result of the encoding by changing the number of delay clocks.

1of2 selector 54_1,54₂Are each slow
Postponer 52_1,52₂From the output of and the output of FIFO53
Select and output one signal from the two signals
Generates two signals consisting of Ich and Qch
It The timing control unit 55 is stored in the ROM or the like.
Writing to the FIFO 53 by reading the contents
Signal (Write enable) and read signal (Read enable),
And 1of2 selector 54 _1,54₂Select signal (Select si
gnal) and generate.

FIG. 9 shows a decoder according to an embodiment of the present invention, and corresponds to the encoder shown in FIG. 56 is a 1 of 2 selector, 57 is a FIFO, and 58 is R =
The 1/3 Viterbi decoder, 59 is a timing control unit.

Two signals consisting of Ich and Qch are converted into R = 1.
Input to the inputs in1 and in2 of the / 3 Viterbi decoder 58. On the other hand, in the 1of2 selector 56, one signal is selected from the two signals and is input to the FIFO 57 to delay the variable number of delay clocks so that the excess bits inserted into the empty bits on the encoder side are stored. And input in1,
When decoding the information of the coding rate smaller than the average coding rate from in2, it is read out and added to the input in3 of the R = 1/3 Viterbi decoder 58.

In the R = 1/3 Viterbi decoder 58,
In response to the operation prohibition signals 1, 2, 3 from the timing control unit 59, Viterbi decoding is performed to obtain the decoded signal by prohibiting the metric calculation of the erased bit portion of the punctured code at the inputs in1, in2, in3. Occur.
The timing control unit 59 reads out the contents stored in the ROM or the like to select the 1of2 selector 56.
(Select signal) and the write signal (Wr
ite enable) and read signal (Read enable).

FIG. 10 shows an example in which the importance of the data in the frame is different. As shown in the figure, the data a, b, c, d, e of each part constituting one frame,
f and g have different degrees of importance.

FIG. 11 illustrates an example of deleting surplus bits and inserting them into empty bits, and corresponds to the case of encoding the data shown in FIG. Also,
The specific examples shown in FIGS. 8 and 9 also correspond to this case.

In this example, seven types of data a, b, c, d, and
e, f, g are included, and the respective coding rates (1),
Let (2), (3), (4), (5), (6), (7) be as follows. R (1) = 2/3, R (2) = 3/5, R (3) = 6/11,
R (4) = 1/2, R (5) = 6/13, R (6) = 3/7,
R (7) = 2/5

(A), (b), and (c) show the coding results of the data a, b, and c, which are 2-bit, 3-bit, and 6-bit data, respectively, 3-bit, 5-bit, and 11-bit. It is shown that the empty bits indicated by the black circles are generated as a result of the encoding. In addition, (e), (f), and (g) indicate the encoded results of the data e, f, and g, which encode 6-bit, 3-bit, and 2-bit data into 13-bit, 7-bit, and 5-bit, respectively. As a result of the conversion, it is indicated that a surplus bit indicated by a star is generated.

In the specific example shown in FIGS. 8 and 9, the surplus bits in the encoded data (g), (f) and (e) are converted into the encoded data (a), (b) and (c). ) Is inserted in each free bit. Therefore, the bit length of each information after encoding does not change.

The encoder and decoder according to the present invention can be implemented independently of each other, and the encoders according to other methods are the same as the above-mentioned encoder according to the present invention. Anything that can generate a code output can be decoded by the decoder of the present invention. On the contrary, it goes without saying that any decoder that can decode the same code as the encoder of the present invention can be implemented in combination with the encoder of the present invention.

[0055]

As described above, according to the present invention, in the Viterbi error correction system, when the redundancy of the error correction code is changed according to the importance of the information in the frame of the information to be transmitted, the code By inserting the surplus bits generated according to the encoding into the empty bits so that the data length of each part after encoding does not change, the coding rate of the convolutional code is dynamically changed only by the external timing signal. Can be changed. Therefore, it is possible to prevent the number of types of clock frequencies required for the processing of each unit from increasing and to prevent the number of encoders and decoders from increasing, so that the circuit scale does not increase significantly, An economical error correction method can be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing a principle configuration (1) of the present invention.

FIG. 2 is a diagram showing a basic configuration (2) of the present invention.

FIG. 3 is a diagram showing the configuration of an encoder according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating an encoding operation according to the present invention.

5 is a diagram showing a configuration example of a timing control unit in FIG.

FIG. 6 is a diagram showing the configuration of a decoder according to an embodiment of the present invention.

7 is a diagram showing a configuration example of a timing control unit in FIG.

FIG. 8 is a diagram showing an encoder according to an embodiment of the present invention.

FIG. 9 is a diagram showing a decoder according to an embodiment of the present invention.

FIG. 10 is a diagram illustrating an example in which the importance of data in a frame is different.

FIG. 11 is a diagram illustrating an example of deleting surplus bits and inserting them into empty bits.

FIG. 12 is a diagram showing a configuration of a conventional encoder.

FIG. 13 is a diagram showing a configuration of a conventional decoder.

[Fig. 14] Fig. 14 is a diagram illustrating a configuration example of punctured in a decoder.

[Fig. 15] Fig. 15 is a diagram for describing an encoding operation in a conventional method.

[Explanation of symbols]

 1 Encoder 2 Delay Device 3 FIFO 4 Selector 5 Selector 6 FIFO 7 Decoder 26 Timing Control Unit 34 Timing Control Unit 35 MUX 36 Counter 37 ROM 41 DEMUX 44 Sync Detector 45 Counter 46 ROM

Claims (4)

[Claims] 1. An encoding unit of an encoding transmission system, wherein an input signal is converted into a convolutional code at a transmission side and is transmitted, and a convolutional code is Viterbi-decoded at a reception side to be received, and a digital signal composed of a serial signal is used. An S / P converter (11) for converting data into a K-bit parallel signal; an encoder (1) for converting the K-bit parallel signal into a convolutional code composed of N-bit parallel data; N delay devices (2) for respectively delaying n bits of the parallel data of bits and (N−n) bits of the parallel data of N bits are respectively delayed by a variable delay clock number (N− n)
FIFOs (3), n selectors (4) for selecting one from the delayer (2) and the output of each FIFO (3), and in the FIFO (3) A timing control unit (34) for controlling writing and reading and selection in a selector (4), and a MUX (MUX) that multiplexes outputs from the n selectors (4) and outputs them to m transmission lines. 35), the erasure bit in the code generated in the encoder (1) is dynamically controlled by the timing control unit (34), so that the coding rate is smaller than the average coding rate in the frame. The coding rate variable transmission system is characterized in that the surplus bits of the information part are embedded in empty bits of information having a coding rate higher than the average coding rate. 2. A counter (36) for the timing control section (34) to count from the beginning of a frame at the operating clock frequency of the encoder (1), and the counter (36).
Of the ROM (3) for generating a signal for controlling writing and reading to and from the FIFO (3) and selection in each of the selectors (4) by using the output of
7. The variable code rate transmission system according to claim 1, further comprising: 7). 3. A decoding unit of a coded transmission system in which an input signal is converted into a convolutional code at the transmission side and transmitted, and the convolutional code is Viterbi-decoded at the reception side to be received, from m transmission lines. DEMUX (41) for converting the signal of n to parallel data of n bits, n selectors (5) for selecting one from the parallel data of n bits, and a delay clock for the output of the selector (5). A variable number of n-delays (6), a decoder (7) for Viterbi decoding an input consisting of a convolutional code, writing and reading in the FIFO (6), and selection in the selector (5) And a timing control unit (26) for controlling the erasure bit and controlling the erasure bit in the code decoded by the decoder (7) in accordance with the erasure bit on the encoder side. Code Karitsu variable transmission system according to claim. 4. The timing control unit (26) uses a synchronization detector (44) for detecting a head of a frame in an n-bit input signal and an operation clock frequency of the decoder (7) from the head of the frame. Counter (4
5), writing and reading to and from each of the FIFOs (6) using the output of the counter (45) as an address, and a ROM (46) for generating a signal for controlling selection in each of the selectors (5). The variable coding rate transmission system according to claim 3, wherein.