JPH05167449A - Successive comparison a/d converter - Google Patents

Abstract

PURPOSE:To provide the successive comparison A/D converter implementing analog digital conversion at a high speed with high accuracy regardless of a small size. CONSTITUTION:A comparator 20 compares an input analog signal with a comparison signal. A code generating logic circuit 22 revises digital data in response to an output signal from the comparator 20. Output data from the code generation logic circuit 22 are converted into an analog signal by a unit capacitance type C array D/A converter 21 and it gives a comparison signal to the comparator 20. A control circuit 13 and an adder 15 obtain a difference between each capacitor being a component of the unit capacitance type C array D/A converter 21 and a prescribed reference capacitor CB, obtain a calibration value Hm corresponding to each output data of an A/D converter circuit 50 based on the difference and stores the value to a memory circuit 14. The calibration value Hm is read in response to an output of the code generating logic circuit 22, the calibration value Hm is D/A-converted and added to an output signal of the unit capacitance type C array D/A converter 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a successive approximation type AD (analog / digital) converter used in various electronic devices, and more particularly, to a unit capacitance type C array DA converter and a successive approximation type AD having a self-calibration function. Regarding the converter.

[0002]

2. Description of the Related Art Conventional AD converters include various types such as an integration type, a parallel type, a successive approximation type, and a Σ-Δ modulation type. Most high-speed and high-precision AD conversion is performed by a successive approximation type AD converter.

As a document relating to a successive approximation type AD converter, Tetsya Iida, et al "AC
MOS 10bit ACCURACY AND 5μs
SPEED AD CONVERTER "CICC p
p. There are 9,2,1-9,2,4,1988.

The AD converter described in the above document is
As shown in FIG. 10, it is a successive approximation type, and the C array is composed of unit capacitances. By selecting the capacitances using the centroid algorithm, the influence of the variation in the capacitance value on the accuracy of AD conversion is affected. I'm making it small.

[0005]

However, in the case of configuring an AD converter with higher precision and higher resolution, it is necessary to increase the capacitance value of the unit capacitance and reduce the influence of random variation of the capacitance value. Along with this, the number of bits in the C array must be increased. However, for example, when an AD converter with a resolution of 16 bits is to be constructed by the successive approximation method, the area occupied by the C array DA converter (chip size) is 2 times that of the AD converter with a resolution of 10 bits.
⁶ (= 64) times. Further, the total capacitance value of the C-array type DA converter also becomes 64 times, the sampling time of the analog input signal becomes long, and the operating speed becomes about 1/64. The present invention has been made in view of the above circumstances, and an object thereof is to provide a small-scale successive approximation type AD converter that performs high-speed and highly accurate AD conversion.

[0006]

A successive approximation type analog-digital converter is a comparator for comparing an input analog signal and a comparison signal, and a code for updating and outputting digital data in response to the output of the comparator. An analog-digital conversion circuit comprising a generation logic circuit and a unit capacitance type C array digital-analog converter which converts the output data of the code generation logic circuit into an analog signal and supplies the analog signal as the comparison signal. The difference between the individual capacitors forming the unit capacitance type C array digital-analog converter and a predetermined reference capacitor is obtained, and the calibration value corresponding to each digital data output from the analog-digital conversion circuit is calculated based on this difference. A first circuit to be obtained, a memory circuit for storing the obtained calibration value, and the memory circuit for storing the obtained calibration value, A second circuit for reading the calibration value stored in the memory circuit, converting the calibration value to digital-analog, adding the calibration value to the output signal of the unit capacitance type C array / digital-analog converter, and supplying the second circuit to the comparator. It is equipped with a self-calibration function.

[0007]

For example, after the power is turned on, the first circuit finds the difference between the individual capacitors forming the unit capacitance type C array digital-analog converter and a predetermined reference capacitance, and based on this difference, the analog-digital conversion is performed. The calibration value corresponding to each digital data output from the circuit is obtained. The calculated calibration value is stored in the memory circuit.

Next, the comparator compares the input analog signal with the comparison signal. In response to the output indicating the comparison result from the comparator, the code generation logic circuit updates and outputs the digital data. The unit capacitance type C array digital-analog converter receives the output data of the code generation logic circuit, converts the output data into an analog signal, and supplies the analog signal to the comparator as the comparison signal. At the same time, in response to the output of the code generation logic circuit, the second
Circuit reads the calibration value stored in the memory circuit, converts the calibration value into a digital-analog value, adds the calibration value to the output signal of the C-array / digital-analog converter, and supplies the output signal to the comparator. The analog input signal, the output of the unit capacitance type C array digital-analog converter, and the second
The output of the code generation logic circuit when the addition signals of the outputs of the above circuits 1 and 2 become the digital data corresponding to the analog input signal.

With such a structure, the influence of the variation in the capacity of the unit capacitance type C array digital-analog converter is reduced, and the analog-digital conversion can be accurately performed.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A successive approximation type AD (analog-digital) converter having a self-calibration function according to a first embodiment of the present invention will be described below with reference to the drawings.

AD converter, successive approximation type AD conversion circuit 50
And a calibration circuit 10. The successive approximation type AD conversion circuit 50 has a comparator (comparator) 20, a code generation logic circuit 22, and a unit capacity type C array DA converter 21 like the conventional successive approximation AD converter.

An analog signal is supplied to the first input terminal of the comparator 20, and an analog output signal of the unit capacitance type C array DA (digital analog) converter 21 is supplied to the second input terminal. .. The comparator 20 compares the signal levels of these two analog input signals and outputs a signal indicating the comparison result. Further, the comparator 20 has a function of internally short-circuiting the two input terminals according to a control signal from the control circuit 13 described later.

The code generation logic circuit 22 outputs digital data in response to the comparison result from the comparator 20. As shown in FIG. 2, the unit capacity type C array DA converter 21 includes a plurality of unit capacity capacitors C connected in parallel.
1 to Cn, the connection state of the capacitors C1 to Cn to the first or second power supply is switched according to the digital signal from the code generation logic circuit 22, and the digital signal is DA-converted.

The self-calibration circuit 10 has a control circuit 13, a memory circuit 14, an adder 15, a local DA converter 11, a capacitive element CH and a reference capacitor CB. Control circuit 13
Controls the overall operation of this system. Memory circuit 1
Reference numeral 4 denotes a RAM, which stores a capacitance difference Di and a calibration value Hm, which will be described later, under the control of the control circuit 13.

Under the control of the control circuit 13, the adder 15 calculates an average value Dx, a calibration value Hm, etc., which will be described later. The local DA converter 11 uses the calibration value Hm supplied from the memory circuit 14.
Is DA converted and supplied to the comparator 20 via the capacitor CH.

The reference capacitor CB has the same capacity as the capacitors C1 to Cn forming the unit capacity type C array DA converter 21, one end thereof is connected to the input end of the comparator 20, and the other end thereof is switched. Is connected to the first power source or the second power source. Next, the operation of the successive approximation type AD converter of FIG. 1 will be described.

As shown in the timing chart of FIG. 3, the circuit of FIG. 1 measures the capacitance difference Di (process 1) after the power is turned on, calculates the calibration value Hm (process 2), and then performs the AD conversion operation. (Process 3). The operation will be described below in the order of processes.

First, the control circuit 13 controls the comparator 20 to short-circuit its two inputs in order to obtain the capacitance difference Di between each capacitor Ci and the reference capacitor CB constituting the unit capacitance type C array DA converter 21. .. Further, the analog input terminal is fixed at a predetermined potential.

In this state, the control circuit 13 connects the reference capacitor CB to the second power source, the capacitor C1 to be measured to the first power source, and the other capacitors C2 to Cn to the second power source. Connect to. Further, the control circuit 13
Causes the local DA converter 11 to generate a voltage having an intermediate value between the first power supply and the second power supply.

After a lapse of a predetermined time (after completion of charging / discharging of each capacitor), the control circuit 13 connects the reference capacitor CB to the first power source and the capacitor C1 to the second power source. Note that the capacitors C2 to Cn remain connected to the second power supply.

In this state, the code generation logic circuit 22 performs a successive approximation operation and updates the output data according to the output of the comparator 20. The control circuit 13 supplies the output data of the code generation logic circuit 22 to the local DA converter 11, converts it into an analog signal, and feeds it back to the input terminal of the comparator 20 via the capacitor CH.

The control circuit 13 stores the output digital data of the code generation logic circuit 22 when the output of the comparator 20 becomes an intermediate level in the memory circuit 14 as the difference D1 between the capacitances of the reference capacitor CB and the capacitor C1. ..

Next, in order to obtain the capacitance difference D2 between the reference capacitor CB and the capacitor C2, the control circuit 13 connects the reference capacitor CB to the second power source, and the capacitor C2
Is connected to the first power supply, another capacitor is connected to the second power supply, and the local DA converter 11 is caused to generate a voltage having an intermediate value between the first power supply and the second power supply.

After the elapse of a predetermined time, the control circuit 13 connects the reference capacitor CB to the first power supply and the capacitor C2 to the second power supply. In this state, the code generation logic circuit 22 performs the successive approximation operation, and the control circuit 13 causes the comparator 20 to operate.
Code generation logic circuit 2 when the output of the
The output data of 2 is the reference capacitor CB and the capacitor C2.
It is stored in the memory circuit 14 as the capacity difference D2. After that, similarly, the capacitance differences D3, D4, ... Between the capacitors C3, C4 ,.
Store in 4.

When the above-described operation (process 1) for all the capacitors C1 to Cn is completed, the control circuit 13
Reads the data stored in the memory circuit 14,
The calibration value Hm is obtained by controlling the adder 15 based on the equation (1), and the obtained calibration value Hm is written in the memory circuit 14. In the equation (1), m is the code generation logic circuit 22.
Represents the digital code of the output, and Dx represents the average value (D1 + D2 + ... Dn) / n of D1 to Dn.

[0026]

[Equation 2]

When the calibration value Hm of each of the output data of the code generation logic circuit 22 (for example, 00000000 to 11111111 when the output data of the code generation logic circuit 22 is 8 bits) is obtained, the process 2 shown in FIG.
Ends. Next, the operation of A / D converting the input analog signal using the calibration value Hm will be described.

The control circuit 13 supplies a control signal to the comparator 20, releases the two-input short-circuit state, separates the analog input terminal from the predetermined voltage, and inputs A to the input terminal of the comparator 20.
An analog signal to be D-converted is supplied.

The comparator 20 compares the analog input signal with the analog data supplied to the second input terminal and outputs a signal corresponding to the comparison result. The code generation logic circuit 22 updates (up and down) the output digital data according to the comparison result. This output digital data is a unit capacitance type C array DA.
The analog signal is converted by the converter 21, and the comparator 20
Is supplied to.

At the same time, the control circuit 13 reads the calibration value Hm corresponding to the digital data output by the code generation logic circuit 22 from the memory circuit 14 and supplies it to the local DA converter 11. The local DA converter 11 converts this digital data into analog data, adds it to the output analog signal of the unit capacitance type C array DA converter 21 in an analog manner, and supplies it to the comparator 20. Thereafter, similarly, digital data corresponding to the analog input signal is output from the code generation logic circuit 22. The calculation and storage of the calibration value Hm in processes 1 and 2 may be performed once after the power is turned on. Second Embodiment Next, a second embodiment of the present invention will be described with reference to FIGS. In FIG. 4, the same parts as those in FIG. 1 are designated by the same reference numerals.

The structure of FIG. 4 differs from that of FIG. 1 in that
The chopper comparator 20a is used as a comparator, and the analog input signal is a unit capacitance type C array DA.
The point is that it is supplied to the converter 21.

Also in the second embodiment, as shown in FIG. 5, after the power is turned on, each capacitor C constituting the C array is
1 to Cn and the difference Di between the capacitances of the reference capacitors CB are sequentially obtained (process 1), the calibration value Hm is obtained (process 2), and then the calibration value Hm stored in the memory circuit 14 is obtained.
A / D conversion operation using is performed (process 3). However, since the chopper comparator 20a is used, the measurement of the difference Di and the AD conversion are achieved in two modes of the auto-zero mode and the comparison mode, respectively.

The operation of the circuit of FIG. 4 will be described below with reference to FIGS.
Will be described in order. First, the unit capacitance type C array D
The difference Di in capacitance between the capacitors C1 to Cn and the reference capacitor CB that form the A converter is sequentially obtained from D1 (process 1).

To determine the difference D1, the control circuit 13 sets the system in the autozero mode. In this mode, as shown in FIG. 6, the control circuit 13 turns on the switch SW of the chopper comparator 20a to short-circuit the input end and the output end of the comparator, and connects the reference capacitor CB to the second power supply. The capacitor C1 to be measured is connected to the first power supply, and the other capacitors C2 to Cn are connected to the second power supply.
Connect to the power supply. Further, the control circuit 13 causes the local DA converter 11 to generate a voltage having an intermediate value between the first voltage and the second voltage. In this state, when the charging and discharging of each capacitor are completed, the potentials at the input end and the output end of the chopper comparator 20a become the same value, and no current flows through the switch SW, the initial state of the chopper comparator 20a is set.

Next, since the control circuit 13 enters the comparison mode, the switch SW is turned off as shown in FIG.
The reference capacitor CB is connected to the first power supply and the capacitor C1 is connected to the second power supply. The capacitors C2 to Cn are connected to the second power source. In this state, the code generation logic circuit 22 performs the successive approximation operation,
The output data is updated according to the output of the chopper comparator 20a. The output data of the code generation logic circuit 22 is converted into an analog signal by the local DA converter 11,
Via the capacitor CH, the chopper comparator 20a
Is fed back to the input of. Code generation logic circuit 22
Output data of the chopper comparator 20a is updated.
When the voltage at the input terminal of ∑ substantially coincides with the threshold value, the output of the chopper comparator 20a also becomes the intermediate level. The control circuit 13 stores the output data of the code generation logic circuit 22 at this point in the memory circuit 14 as the difference D1 in capacitance between the reference capacitor CB and the capacitor C1.

Next, in order to obtain the difference D2 in capacitance between the reference capacitor CB and the capacitor C2, the control circuit 13 sets the auto zero mode, turns on the switch SW of the chopper comparator 20a, and sets the reference capacitor CB to the second power source. Connected, the capacitor C2 is connected to the first power supply, the capacitors C1, C3 to Cn are connected to the second power supply, and the local DA converter 11 is caused to generate a voltage of an intermediate value between the first power supply and the second power supply. .. After a lapse of a predetermined time, the control circuit 13 enters the comparison mode, so that the switch SW is turned off, the reference capacitor CB is connected to the first power supply, and the capacitor C2 is connected to the second power supply. In this state, the successive approximation operation is performed, and the output data of the code generation logic circuit 22 at the time when the output of the chopper comparator 20a becomes the intermediate level is stored in the memory circuit 14 as the difference D2 between the capacitances of the reference capacitor CB and the capacitor C2. Remembered. Thereafter, similarly, the difference D in capacitance between the capacitors C3, C4 ... And the reference capacitor CB.
3, D4 ... Are obtained and stored in the memory circuit 14.

When the above-mentioned operations for all the capacitors C1 to Cn are completed, the control circuit 13 causes the memory circuit 1 to operate.
The calibration value Hm is obtained by controlling the adder 15 based on the data stored in 4 and the equation (1), and the calibration value Hm is written in the memory circuit 14. This completes the operation (process 2) for obtaining the calibration value Hm. Next, the above calibration value Hm
The operation (process 3) of A / D converting the input analog signal using will be described.

First, the control circuit 13 sets the successive approximation type AD converter to the auto-zero mode shown in FIG. That is, the control circuit 13 turns on the switch SW of the chopper comparator 20a, supplies an analog input signal to the capacitors C1 to Cn, and causes the local DA converter 11 to generate a voltage having an intermediate value between the first power supply and the second power supply. .. The reference capacitor CB may be connected to either the first power supply or the second power supply.

Next, since the control circuit 13 enters the comparison mode shown in FIG. 9, the control circuit 13 turns off the switch SW and causes the code generation logic circuit 22 to perform the successive comparison operation. The code generation logic circuit 22 raises or lowers its output according to the output of the chopper comparator 20a. The connection state of the reference capacitor CB is not changed. The output data of the code generation logic circuit 22 is supplied to the unit capacitance type C array DA converter 21, and the capacitors C1 to Cn are supplied according to the digital output.
Is connected to the first or second power supply. Further, the output data of the code generation logic circuit 22 is supplied to the memory circuit 14 via the control circuit 13, and the calibration value Hm stored in the memory circuit 14 is read out. The read calibration value Hm is supplied to the local DA converter 11, converted into an analog signal by the local DA converter 11, and fed back to the input terminal of the chopper comparator 20a via the capacitor CH.

The output data of the code generation logic circuit 22 is updated, and when the input voltage of the chopper comparator 20a becomes substantially equal to its threshold value, the output of the chopper comparator 20a becomes an intermediate level. The output data of the circuit 22 becomes a digital signal corresponding to the input analog signal. The auto-zero mode and the comparison mode described above are repeated to sequentially convert the continuously supplied analog signals into digital data. Further, in the first and second embodiments, the difference Di is calculated in order from D1, but the order does not matter.

According to the above-mentioned configuration, when used in the above-mentioned embodiment, the self-calibration circuit is added, but the occupied area does not become 64 times as in the previous example, and the structure can be made about 4 times.
High speed and high accuracy (high resolution) can be achieved.

The unit capacitance type C array DA converter 21
Since the unit capacitance is used for the calibration and the calibration is performed with respect to the random variation of the capacitance value of the capacitor, the calibration amount becomes small, and the local DA converter 11 can also be made small.

[0043]

With the above structure, it is possible to provide a successive approximation AD converter which can reduce the area occupied by the AD converter and the total capacitance value and can perform high-speed and highly accurate successive approximation AD conversion.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a successive approximation type AD converter according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a unit capacitance type C array type DA converter.

FIG. 3 is a timing chart of the operation of the successive approximation type AD converter shown in FIG.

FIG. 4 is a block diagram showing a configuration of a successive approximation type AD converter according to a second embodiment of the present invention.

5 is a timing chart of the operation of the successive approximation type AD converter shown in FIG.

FIG. 6 is a diagram showing a connection state of each unit in an auto zero mode for obtaining a difference in capacitance between a capacitor forming a C array and a reference capacitor.

FIG. 7 is a diagram showing a connection state of each part in a comparison mode for obtaining a difference in capacitance between a capacitor forming a C array and a reference capacitor.

FIG. 8 is a diagram showing a connection state of each unit in an auto zero mode in an AD conversion operation.

FIG. 9 is a diagram showing a connection state of each unit in a comparison mode in an AD conversion operation.

FIG. 10 is a block diagram showing a configuration of a conventional successive approximation type AD converter.

[Explanation of symbols]

10 ... Self-calibration circuit, 11 ... Local DA converter, 13 ... Control circuit, 14 ... Memory circuit, 15 ... Adder, 20a ... Chopper comparator, 21 ... Unit capacitance type C array DA converter, 22 ... Code generation logic circuit , 50 ... Successive approximation type AD
Conversion circuit.

Claims (5)

[Claims] 1. A comparator for comparing an input analog signal with a comparison signal, a code generation logic circuit for updating and outputting digital data in response to an output of the comparator, and output data for the code generation logic circuit. To an analog signal and supplies the comparator as a signal for comparison to the unit capacitance type C array / digital / analog converter; and the unit capacitance type C array / digital / analog converter. Find the difference between the individual capacitors that are configured and the predetermined reference capacitance,
Means for obtaining a calibration value corresponding to each digital data output from the analog-to-digital conversion circuit based on this difference, storage means for storing the obtained calibration value, and in response to the output of the code generation logic circuit, The calibration value stored in the storage means is read, and the calibration value is digital-analog converted, added to the output signal of the unit capacitance type C array digital-analog converter, and supplied to the comparison circuit. A successive approximation type analog-digital converter having a self-calibration function. 2. The calibration value Hm corresponding to the m-th digital data is calculated according to the following equation based on the difference Di between the capacitors (C1 to Cn) and the reference capacitance (CB) and its average value Dx. The successive approximation type analog-digital converter according to claim 1, wherein [Equation 1] 3. The successive approximation type analog-digital converter according to claim 1, wherein the comparator is composed of a two-input comparator or a chopper type comparator. 4. The successive approximation type analog-digital converter according to claim 1, wherein the supplying means supplies the output signal to the second input terminal of the comparator via a capacitive element. 5. A comparator for comparing an input analog signal with a comparison signal, a code generation logic circuit for updating digital data in response to an output of the comparator, and an analog signal for outputting the output digital data of the code generation circuit. And a unit capacitance type C array, which is supplied to the comparator as the comparison signal.
A digital-analog converter, and a calibration value corresponding to each of the digital data output from the analog-digital conversion circuit, which is obtained based on the difference between the reference capacitors and the capacitors forming the C-array digital-analog converter, are stored. In response to the output of the storage means and the code generation circuit, the calibration value stored in the storage means is read out, digital-to-analog converted and added to the output signal of the C array / digital-analog converter. A successive approximation type analog-to-digital converter comprising a self-calibration circuit having a means for supplying to a comparator.