JPH05166689A - Method for joining semiconductor substrates - Google Patents

Method for joining semiconductor substrates

Info

Publication number
JPH05166689A
JPH05166689A JP32997491A JP32997491A JPH05166689A JP H05166689 A JPH05166689 A JP H05166689A JP 32997491 A JP32997491 A JP 32997491A JP 32997491 A JP32997491 A JP 32997491A JP H05166689 A JPH05166689 A JP H05166689A
Authority
JP
Japan
Prior art keywords
substrate
film
substrates
stress
hot plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32997491A
Other languages
Japanese (ja)
Inventor
Haruo Shiratori
治男 白鳥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Metal Mining Co Ltd
Original Assignee
Sumitomo Metal Mining Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal Mining Co Ltd filed Critical Sumitomo Metal Mining Co Ltd
Priority to JP32997491A priority Critical patent/JPH05166689A/en
Publication of JPH05166689A publication Critical patent/JPH05166689A/en
Pending legal-status Critical Current

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  • Element Separation (AREA)

Abstract

PURPOSE:To introduce proper internal stress into the firms of substrates for formation of semiconductor elements by bringing two substrates of different temperatures into contact with each other. CONSTITUTION:Two silicon substrates (or wafers) are prepared, and a thermal oxide film 2 is made on each surface. One substrate 1 is put so that the surface may turn up on the surface of the hot plate placed inside a clean room at room temperature, keeping the surface of said hot plate at approximately 60 deg.C. Just as the substrate 1 gets to fit the temperature of the hot plate, another wafer 1 is placed on it, and they are joined temporally. This is put in a furnace to do heat treatment in a nitrogen atmosphere. Hereby, it becomes possible to introduce internal stress of optional magnitude into the film of the substrate manufactured by lamination method.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、張り合わせ法を用いた
半導体素子形成用基板(以下基板と称す)の製造方法に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a substrate for forming a semiconductor element (hereinafter referred to as a substrate) using a laminating method.

【0002】[0002]

【従来の技術】大面積で良質なシリコン薄膜単結晶を有
するSOI(Silicon onInsulator)基板を得る方法と
して、あるいは表面から深い位置に急峻な不純物濃度勾
配を持つ基板を得る方法として、直接接合法が利用され
る。SOI基板を得るには、図2に示すようにまず表面
を鏡面に仕上げたシリコン基板1を2枚用意し、一方ま
たは両方の基板表面に絶縁膜となる酸化膜2を形成す
る。次に基板の絶縁膜(鏡面)同士を軽く接触させ仮接
合状態にし、これを高温で熱処理して一体化させ接合を
完了する。最後に一方の基板を研磨、エッチングなどに
より所望の厚さを残して除去しSOI膜3を形成すると
SOI基板が完成する。急峻な不純物濃度勾配を目的と
する場合には、所望の不純物分布の基板を用意し、絶縁
膜を形成することなく上述の手順で基板同士を直接接合
する。
2. Description of the Related Art A direct bonding method is used as a method for obtaining an SOI (Silicon on Insulator) substrate having a large area and good quality silicon thin film single crystal, or as a method for obtaining a substrate having a steep impurity concentration gradient from a surface to a deep position. Used. In order to obtain an SOI substrate, first, two silicon substrates 1 whose surfaces are mirror-finished are prepared as shown in FIG. 2, and an oxide film 2 serving as an insulating film is formed on the surface of one or both substrates. Next, the insulating films (mirror surfaces) of the substrates are lightly contacted with each other to make a temporary bonding state, and this is heat-treated at high temperature to be integrated to complete the bonding. Finally, one substrate is removed by polishing, etching, etc., leaving a desired thickness, and the SOI film 3 is formed, whereby the SOI substrate is completed. When a steep impurity concentration gradient is intended, a substrate having a desired impurity distribution is prepared, and the substrates are directly bonded to each other by the procedure described above without forming an insulating film.

【0003】[0003]

【発明が解決しようとする課題】このようにして製作し
た基板に素子を形成するとき、薄膜化した基板(以下、
膜と称す)の内部応力が素子の性能や製造歩留りを左右
する場合がある。膜の内部応力の問題はとくにダイヤフ
ラムや梁などの構造をもつ素子においてより深刻であ
る。たとえば膜内に圧縮応力が存在すると、膜を利用し
て形成したダイヤフラムや梁にたわみが生じ、これを利
用するセンサーなどでは原点付近で大きな不感帯を持
つ。引っ張り応力はダイヤフラム用途に限らず一般に好
ましいと考えられるが、これが極端に大きいと基板の反
りなどを生じ素子製造プロセスの障害となる。また膜内
で応力が不均一に分布しているとそれが素子特性のばら
つきとなって現れる。従来の方法においては膜に内部応
力を導入することは不可能であった。このため膜内の応
力分布は、基板の反りや表面の凸凹、またはハンドリン
グに伴う基板の変形などの不安定な要因が支配的となっ
ていた。本発明は、張り合わせ法により製作する基板の
膜に適度な内部応力を導入する方法を提供する。
When an element is formed on the substrate thus manufactured, a thinned substrate (hereinafter, referred to as
The internal stress of a film) may affect the performance of the device and the manufacturing yield. The problem of the internal stress of the film is more serious in a device having a structure such as a diaphragm or a beam. For example, when a compressive stress is present in the film, the diaphragm or beam formed by using the film is bent, and a sensor or the like using this has a large dead zone near the origin. It is generally considered that the tensile stress is not limited to the diaphragm application, but if it is extremely large, the substrate warps or the like, which becomes an obstacle to the element manufacturing process. Further, if the stress is unevenly distributed in the film, it appears as variations in device characteristics. In the conventional method, it was impossible to introduce internal stress into the film. For this reason, the stress distribution in the film is dominated by unstable factors such as warpage of the substrate, unevenness of the surface, or deformation of the substrate due to handling. The present invention provides a method of introducing an appropriate internal stress into a film of a substrate manufactured by a laminating method.

【0004】[0004]

【課題を解決するための手段】実験によれば、製作した
基板の膜の内部応力は仮接合時の状態で決まり、これに
続く熱処理および薄膜化のための加工工程における応力
の緩和はほとんどない。すなわち、仮接合状態の各々の
基板に引っ張りと圧縮の応力を与えることで、最終的に
仕上げた膜に応力を残すことが可能である。膜の内部応
力の大きさは2枚の基板のはじめの厚さと残す膜の厚さ
および当初の応力とから決まるとの知見をえ、本発明で
はこのような仮接合を行うために基板の熱膨張を利用す
ることにし、温度差を持たせた2枚の基板を仮接合する
ものである。本発明は、表面を鏡面に仕上げた2枚の半
導体素子形成用基板を、その鏡面同士を接触させ仮接合
した後、熱処理して接合一体化させる直接接合法におい
て、仮接合にさいして2枚の半導体素子形成用基板に温
度差を持たせて接触させ、内部に応力を導入せしめるこ
とを特徴とする半導体素子形成用基板の接合方法であ
る。
According to the experiment, the internal stress of the film of the manufactured substrate is determined by the state at the time of temporary joining, and there is almost no relaxation of stress in the subsequent heat treatment and processing steps for thinning. .. That is, by applying tensile and compressive stress to each of the temporarily bonded substrates, the stress can be left in the finally finished film. It has been found that the magnitude of the internal stress of the film is determined by the initial thickness of the two substrates, the thickness of the remaining film and the initial stress, and in the present invention, the heat of the substrate is used to perform such temporary bonding. The expansion is used to temporarily bond two substrates having different temperatures. The present invention is a direct bonding method in which two semiconductor element-forming substrates whose surfaces are mirror-finished are temporarily bonded by bringing their mirror surfaces into contact with each other, and then heat-bonded to be integrated into one. The method for joining semiconductor element formation substrates is characterized in that the semiconductor element formation substrates are brought into contact with each other with a temperature difference and stress is introduced inside.

【0005】[0005]

【作用】2枚の基板に温度差を与えると、一方の基板は
他方に対して熱膨張係数と温度差に比例した量だけ伸長
する。この状態で両者を接触させると互いに吸着しあい
瞬時に仮接合が完了する。接触から仮接合完了までの間
の基板間の熱の移動は無視できるから、これらが熱平衡
状態に達した時点で、仮接合前の基板の伸長量に相当す
る応力が仮接合基板に導入されたことになる。このとき
各基板には引っ張りと圧縮の応力がその厚さに応じて存
在し、この分布は接合一体化の熱処理後も保存される。
一方の基板を薄膜化して目的の薄膜に仕上げると、応力
は薄膜に集中し、膜厚が基板全厚さに対して十分小さい
場合は、仮接合前の一方の基板の伸長量に相当する応力
が膜に導入される。膜に導入される応力は基板の最初の
伸長量、即ち仮接合前の基板の温度差のみで決まるから
応力の大きさの制御は容易である。また膜の厚みが無視
できない場合でも、最終膜厚、基板厚さおよび導入すべ
き応力の大きさから、仮接合時に必要な温度差は容易に
設計できる。
When a temperature difference is applied to the two substrates, one of the substrates expands with respect to the other by an amount proportional to the coefficient of thermal expansion and the temperature difference. When both are brought into contact with each other in this state, they are adsorbed to each other and the temporary joining is instantly completed. Since the heat transfer between the substrates from the contact to the completion of the temporary bonding can be ignored, the stress equivalent to the extension amount of the substrate before the temporary bonding was introduced into the temporary bonded substrate when these reached the thermal equilibrium state. It will be. At this time, tensile and compressive stresses are present in each substrate depending on its thickness, and this distribution is preserved even after the heat treatment for joining and unifying.
When one of the substrates is thinned to the target thin film, the stress concentrates on the thin film, and if the film thickness is sufficiently smaller than the total thickness of the substrate, the stress equivalent to the extension amount of one substrate before temporary bonding Are introduced into the membrane. Since the stress introduced into the film is determined only by the initial extension amount of the substrate, that is, the temperature difference between the substrates before temporary bonding, it is easy to control the magnitude of the stress. Further, even when the film thickness cannot be ignored, the temperature difference required for temporary bonding can be easily designed from the final film thickness, the substrate thickness, and the magnitude of stress to be introduced.

【0006】本方法との比較のため、従来の方法で製作
した場合に張り合わせ基板の膜の内部応力を概算する。
まず材料の熱膨張によって膜に導入される応力を見積も
る。モデルとして径100mm、厚さ500μm のシリコ
ン基板2枚に各々厚さ0.5μm の熱酸化膜を形成し、
これらを接合して一方を厚さ1μm の膜に仕上げたSO
I構造を考える。用いる基板の表面は完全に平坦で、酸
化温度(10000C)では応力はないものと仮定する。
このとき膜の内部応力は引っ張りで、その大きさは2.
9×106 dyn/cm2 と見積もられる。次に基板表面の凸
凹によって膜に導入される応力を見積もる。モデルとし
て径100mm、厚さ500μm で表面が曲率半径10m
の凸状の基板に、完全に平坦な表面を持つ十分に厚い基
板を接合しこれを厚さ1μm の膜に仕上げた構造を考え
る。この膜の内部応力は5.5×106 dyn/cm2 と見積
もられる。ここで本方法により導入しうる応力の大きさ
を示す。径100mm、厚さ500μm の平坦な基板を2
枚用意し、基板間に温度差ΔTを与えて接合し、高温に
あった基板を薄膜化して厚さ1μm の膜に仕上げるとす
ると、膜の内部応力は引っ張りでその大きさはΔT×
3.3×106 dyn/cm2 となる。たとえば仮接合時の基
板の温度差を30℃とすると膜に約108 dyn/cm2 の引
っ張り応力が導入される。これは先に見積もった、従来
法の接合法で膜に残りうる応力を無視するに十分な大き
さである。
For comparison with this method, the internal stress of the film of the bonded substrate when the conventional method is used will be estimated.
First, the stress introduced into the film by the thermal expansion of the material is estimated. As a model, two 0.5 mm thick thermal oxide films were formed on two silicon substrates with a diameter of 100 mm and a thickness of 500 μm.
An SO with one of these joined to form a film with a thickness of 1 μm
Consider the I structure. It is assumed that the surface of the substrate used is perfectly flat and there is no stress at the oxidation temperature (1000 0 C).
At this time, the internal stress of the film is tensile and its magnitude is 2.
It is estimated to be 9 × 10 6 dyn / cm 2 . Next, the stress introduced into the film by the unevenness of the substrate surface is estimated. The model has a diameter of 100 mm and a thickness of 500 μm, and the surface has a radius of curvature of 10 m.
Consider a structure in which a sufficiently thick substrate with a completely flat surface is bonded to the convex substrate of and the film is finished to a thickness of 1 μm. The internal stress of this film is estimated to be 5.5 × 10 6 dyn / cm 2 . Here, the magnitude of stress that can be introduced by this method is shown. 2 flat substrates with a diameter of 100 mm and a thickness of 500 μm
If one substrate is prepared and bonded with a temperature difference ΔT between the substrates, and the substrates that were at high temperature are thinned to a film with a thickness of 1 μm, the internal stress of the film is tensile and the size is ΔT ×
It becomes 3.3 × 10 6 dyn / cm 2 . For example, when the temperature difference between the substrates at the time of temporary bonding is 30 ° C., a tensile stress of about 10 8 dyn / cm 2 is introduced into the film. This is large enough to neglect the stress estimated in the previous method that may remain in the film by the conventional bonding method.

【0007】[0007]

【実施例】【Example】

(実施例1)本発明による実施例を図1にしたがって説
明する。 1)径100mm、厚さ500μm のシリコン基板(また
はウエハ)を2枚用意し、各々表面に厚さ0,5μm の
熱酸化膜2を形成した(図1(a)、(b)参照)。 2)室温23℃のクリーンルーム内に置いたホットプレ
ートの表面を約60℃に保ち、この上に1枚の基板を表
面が上を向くように載せた(図1(c)参照)。 3)基板がホットプレートの温度になじんだところで、
もう1枚のウエハを上から重ね、仮接合を行った(図1
(d)参照)。 4)室温に放置した応力による剥離がないことを確認し
たうえで、これを熱処理炉に挿入し窒素雰囲気中、11
00℃、2時間の熱処理を行った。 5)この基板を先にホットプレートに置いた基板の側か
ら研磨し厚さ2μm の膜を残しSOI膜3を形成した
(図1(e)参照)。 6)比較のため従来法で作製した試料を用意し、両者を
支持基板の側から徐々に薄くしていったところいずれも
薄膜が凸に変形した。この変形はシリコンと熱酸化膜の
熱膨張係数の差に起因して生じる酸化膜内の圧縮応力に
よるものである。変形の度合いは本方法により製作した
試料の方が明らかに小さく、膜に引っ張りの応力が入っ
ていたことが確認された。
(Embodiment 1) An embodiment according to the present invention will be described with reference to FIG. 1) Two silicon substrates (or wafers) each having a diameter of 100 mm and a thickness of 500 μm were prepared, and a thermal oxide film 2 having a thickness of 0.5 μm was formed on each surface (see FIGS. 1A and 1B). 2) The surface of a hot plate placed in a clean room at room temperature of 23 ° C. was kept at about 60 ° C., and one substrate was placed on the hot plate so that the surface thereof faced upward (see FIG. 1 (c)). 3) Where the substrate has been adjusted to the temperature of the hot plate,
Another wafer was stacked from above and temporary bonding was performed (Fig. 1
(See (d)). 4) After confirming that there is no peeling due to stress when left at room temperature, insert this into a heat treatment furnace and place it in a nitrogen atmosphere for 11
Heat treatment was performed at 00 ° C. for 2 hours. 5) This substrate was polished from the side of the substrate previously placed on the hot plate to form the SOI film 3 while leaving a film having a thickness of 2 μm (see FIG. 1 (e)). 6) For comparison, a sample prepared by the conventional method was prepared, and when both were gradually thinned from the supporting substrate side, the thin film was deformed to be convex. This deformation is due to the compressive stress in the oxide film caused by the difference in thermal expansion coefficient between silicon and the thermal oxide film. The degree of deformation was obviously smaller in the sample produced by this method, and it was confirmed that the film had tensile stress.

【0008】(実施例2)本発明の効果を定量的に評価
した実施例を記す。 1) 径100mm、厚さ500μm のシリコン基板(また
はウエハ)を2枚用意し、実施例1の2)〜5)の手順
で試料を製作した。ただしホットプレートの表面温度は
40、60、80℃の3種類とした。 2)試料の支持基板を加工し厚さ200μm まで薄くし
たところ膜面が凹に変形した。その状態でウエハの曲率
半径を測定し、試料寸法、物質定数とから膜の内部応力
を計算したところ表1のようであった。仮接合時の基板
温度差によって膜の内部応力が制御されていることがわ
かる。
Example 2 An example of quantitatively evaluating the effect of the present invention will be described. 1) Two silicon substrates (or wafers) having a diameter of 100 mm and a thickness of 500 μm were prepared, and a sample was manufactured by the procedure of 2) to 5) of Example 1. However, the surface temperature of the hot plate was set to three types of 40, 60 and 80 ° C. 2) When the supporting substrate of the sample was processed and thinned to a thickness of 200 μm, the film surface was deformed concavely. In that state, the radius of curvature of the wafer was measured, and the internal stress of the film was calculated from the sample size and the material constant. It can be seen that the internal stress of the film is controlled by the substrate temperature difference during temporary bonding.

【0009】[0009]

【表1】 [Table 1]

【0010】[0010]

【発明の効果】本発明によれば、張り合わせ法により製
作する基板の膜内部に任意の大きさの内部応力を導入す
ることが可能となる。そしてこの基板を用いることで基
板上の素子特性の均一化が図られ歩留り、生産性が向上
する。
According to the present invention, it becomes possible to introduce an arbitrary amount of internal stress into the inside of the film of the substrate manufactured by the bonding method. By using this substrate, the element characteristics on the substrate are made uniform, and the yield and productivity are improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例を説明する製作工程図。FIG. 1 is a manufacturing process diagram illustrating an embodiment of the present invention.

【図2】従来法による張り合わせ基板の製作工程を示す
説明図。
FIG. 2 is an explanatory view showing a manufacturing process of a bonded substrate by a conventional method.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 酸化膜 3 SOI膜 4 ホットプレート 1 Silicon substrate 2 Oxide film 3 SOI film 4 Hot plate

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 表面を鏡面に仕上げた2枚の半導体素子
形成用基板を、その鏡面同士を接触させ仮接合した後、
熱処理して接合一体化させる直接接合法において、仮接
合にさいして2枚の半導体素子形成用基板に温度差を持
たせて接触させ、内部に応力を導入せしめることを特徴
とする半導体素子形成用基板の接合方法。
1. After two mirror-finished substrates for semiconductor element formation are brought into contact with each other and the mirror-finished surfaces are temporarily joined,
In the direct bonding method of heat-treating and bonding-integrating, for temporary bonding, two semiconductor element forming substrates are brought into contact with each other with a temperature difference, and stress is introduced into the inside. Substrate bonding method.
JP32997491A 1991-11-19 1991-11-19 Method for joining semiconductor substrates Pending JPH05166689A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32997491A JPH05166689A (en) 1991-11-19 1991-11-19 Method for joining semiconductor substrates

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32997491A JPH05166689A (en) 1991-11-19 1991-11-19 Method for joining semiconductor substrates

Publications (1)

Publication Number Publication Date
JPH05166689A true JPH05166689A (en) 1993-07-02

Family

ID=18227357

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32997491A Pending JPH05166689A (en) 1991-11-19 1991-11-19 Method for joining semiconductor substrates

Country Status (1)

Country Link
JP (1) JPH05166689A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010518639A (en) * 2007-02-16 2010-05-27 エス. オー. アイ. テック シリコン オン インシュレーター テクノロジーズ Method for joining two substrates
JP2010161388A (en) * 2010-02-18 2010-07-22 Semiconductor Energy Lab Co Ltd Semiconductor device
US9070604B2 (en) 1998-09-04 2015-06-30 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9070604B2 (en) 1998-09-04 2015-06-30 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a semiconductor device
JP2010518639A (en) * 2007-02-16 2010-05-27 エス. オー. アイ. テック シリコン オン インシュレーター テクノロジーズ Method for joining two substrates
US8349703B2 (en) 2007-02-16 2013-01-08 Soitec Method of bonding two substrates
JP2010161388A (en) * 2010-02-18 2010-07-22 Semiconductor Energy Lab Co Ltd Semiconductor device

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