JPH05165705A - Memory controller - Google Patents

Abstract

PURPOSE:To improve the performance of CPU by removing the wait state of CPU. CONSTITUTION:A V-RAM controller 13 is provided with a CPU cycle continuation judgement circuit 31 receiving an access request signal from CPU 11, examining a low-order address and data size, which CPU 11 requests, and judging whether a CPU cycle is to be continued or not, a low-order address/data size generation circuit 32 which previously generates the low-order address of the CPU cycle and data size, which are to be generated next, and an access request generation circuit 34 which individually outputs an access request without waiting for the access request from CPU 11. A size signal, an address signal and the bus size of V-RAM 12 are examined while CPU 11 reads/accesses V-RAM. Thus, CPU access by dynamic bus sizing after this cycle is terminated is previously predicted, and the CPU cycle is individually restarted by providing for the access.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device for controlling a memory such as an image memory, and more particularly to a memory control device capable of continuously executing a read access from a CPU.

[0002]

2. Description of the Related Art FIG. 5 is a timing chart showing a read access from a conventional CPU. As shown in FIG. 5, when the access request from the CPU is asserted,
On the V-RAM controller (hereinafter, referred to as VRC) side, the access from the CPU is recognized at the timing of FIG. 5A and the CPU cycle (for example, operating at 5 clocks) is started at this timing. In response to this CPU cycle, the end signal is returned from the VRC side to the CPU at the timing shown in FIG. Then, the CPU recognizes the end signal returned during the CPU cycle. Here, for example, C
When a data request with a data size of 32 bits is issued from the PU (when the request from the CPU is a data size of 8 bits or 16 bits, there is no problem) If the bus width between the CPU and V-RAM is 16 bits, the read data is insufficient. Will be done. CPU recognizes this end signal and runs short 1
With respect to 6-bit data, read access to the V-RAM is started again in the second CPU cycle. However,
When this second access request is output (see FIG. 5C), the VRC is executing another cycle, so the access from the CPU is recognized at the timing shown in FIG. 5D. Therefore, the CPU waits for the cycle in which the VRC is being executed, and the "other cycle" shown in FIG. 5 becomes a complete wait time (for example, this side corresponds to a dozen or more clocks) for the CPU. .. The above problem is C
This occurs when the data size requested by the PU is larger than the bus width. For example, when the CPU requests a 32-bit data with a bus width of 8 bits, the above waiting time is required four times.

FIG. 6 is a flow chart showing the read access from the CPU divided into the CPU side and the VRC side and showing the respective operations. When data transfer is required twice (for example, in the case of word size (16 bits)). It is a flowchart of a long word (32 bit) read to V-RAM. The same applies when data transfer is required three times or more. Cycle 1 (Other Cycle) When the CPU makes a read access to the V-RAM (step P1), the VRC recognizes the access from the CPU (step S1). Cycle 2 (CPU cycle) VRC starts a CPU cycle (step S
2) The data in the V-RAM is read and transferred to the CPU (step S3). When the access to the V-RAM is completed, the VRC asserts an end signal to the CPU (step S4). Cycle 3 (other cycle) VRC starts another cycle (step S5),
The CPU recognizes the end signal in the next cycle 3 and determines whether the access is completed (step P2). When the access is completed (that is, when the requested data is sufficient), the CPU reads. When the access processing is terminated and the processing is advanced to another processing, and the access is not completed, step P
At 3, the V-RAM read cycle is restarted for insufficient data. For example, when the CPU requests data having a data size of 32 bits and the actually read data is only 16 bits, the data becomes insufficient. In such a case, since the remaining insufficient data is read, the CPU starts read access to the V-RAM again. Here, the restart of the V-RAM read cycle for the above-mentioned insufficient data is called dynamic bus sizing, and is due to CPU misalignment or C
It occurs due to the difference in bus width between PU and V-RAM.
When the second access request is output from the CPU, VR
C recognizes the CPU access (step S6). Cycle 4 (CPU cycle) VRC restarts the CPU cycle (step S
7) The data is read from the V-RAM and transferred to the CPU (step S8). When the access to the V-RAM is completed, the VRC asserts an end signal to the CPU (step S9). Cycle 5 (other cycle) VRC starts another cycle (step S1
0), the CPU recognizes the end signal in cycle 5 and determines whether or not the access is completed (step P4), and when all the insufficient data is read (YES in P4), the V-RAM is executed in step P5. Complete read access.
When the access is not completed, the third data transfer is executed in the same manner as above. The flowchart of FIG. 6 is
As an example, the case where the data transfer is required twice is shown, but similarly, when the transfer is required three times or more, the CPU cycle is executed every other cycle.

[0004]

Therefore, when the actually read data is insufficient for the data size requested by the CPU, C is used to read the remaining data.
The PU will again access the V-RAM, but by the time this second access request is issued,
Since the VRC is executing another cycle, the CPU must wait for the current cycle to finish (see cycle 4 in FIG. 6). That is, these CP
Although the U cycle (cycle 2 and cycle 4 in FIG. 6) is a series of cycles, the conventional VRC cannot recognize it, and a cycle other than the CPU is executed on the way. It will lead to a decrease in CPU performance. Specifically, the cycle 3 between the cycle 2 and the cycle 4 of the CPU cycle is a complete wait time for the CPU, and in particular, one VRC cycle corresponds to the number of CPU clocks to a dozen or more clocks. In consideration of this, the above wait state significantly reduces the CPU performance. The wait time increases as the required transfer increases. As described above, it is considered that the VRC executes another cycle in spite of the continuous execution of the CPU cycle because the access request from the CPU is interrupted. If you try, CPU V
-While the RAM read access is being executed, its size signal,
If the address signal and the bus size of the V-RAM are discriminated and the access requests from the CPU are continuously issued, the CPU cycle is restarted without the VRC executing cycles other than the CPU. CP
It is obvious that the wait state of U can be removed and the performance of the CPU can be improved. An object of the present invention is to be able to continuously execute a series of CPU read cycles by dynamic bus sizing.

[0005]

The means of the present invention are as follows. The discriminating means 1 (see the functional block diagram of FIG. 1, the same applies hereinafter) is a circuit for discriminating that the data size of the data read from the memory is smaller than the data size required by the CPU. It is a circuit that receives an access request signal and examines the data size and bus width requested by the CPU to determine whether the CPU cycle is continued. The executing unit 2 starts a CPU cycle that enables data reading from the memory based on the determination result of the determining unit 1 and continuously executes read access from the CPU. For example, the executing unit 2 independently accesses the second and subsequent accesses. An access request circuit that outputs a request, a generation circuit that generates the next address of a CPU cycle that occurs next, and the like.

[0006]

The operation of the means of the present invention is as follows. When the discriminating means 1 discriminates that the data size of the data read from the memory is smaller than the data size required by the CPU, the executing means 2 independently starts the CPU cycle for enabling the data reading from the memory. , Next address, etc. are generated and read access from the CPU is continuously executed. Therefore, a series of CPU read cycles due to dynamic bus sizing can be continuously executed, and deterioration of CPU performance can be prevented.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment will be described below with reference to FIGS. 2 to 4 are views showing an embodiment of the memory control device. First, the configuration will be described. FIG. 2 is a block diagram of the memory controller. In this figure, 11 is a CPU (for example, MC68030) having a dynamic bus sizing function, and 12 is an image memory (hereinafter referred to as V-
RAM), 13 is V-by accessing the CPU 11.
V-RAM controller (VR that controls the RAM 12
C).

An address bus, a data bus and a signal line are connected to the CPU 11, and an upper address, a lower address, a data size and an access request signal are output from the CPU 11, and an end signal is input. , Read data from the V-RAM 11 is input. The V-RAM controller 13 is a V-RAM
V-RA in response to the CPU 11 access to 12
A V-RAM control signal for controlling M12 is output. Here, this V-RAM control signal is an address, a RAM (row address strobe), a CAS (column address strobe), a write enable signal, and the like.

The V-RAM controller 13 is a V-RAM controller.
The conventional VRC 21 having a RAM control function is provided with a CPU access continuous execution circuit 22 having a function described below. That is, the V-RAM controller 13 receives the access request signal from the CPU 11, examines the lower address and the data size requested by the CPU 11, and determines whether or not to continue the CPU cycle. Generate the lower address and data size of the CPU cycle that will occur next in advance (current CPU cycle is being executed),
Lower address and data size generation circuit 32 that holds the necessary period, address and size signals sent from CPU 11 and lower address and data size generation circuit 3
A selector 33 for selecting and outputting the address and size signal generated in 2, and a CPU cycle continuation determination circuit 3
When it is determined that the CPU cycle is continued in 1
An access request generation circuit 34 which outputs an access request signal independently without waiting for an access request from the PU 11, and a VR
An end signal generation circuit 35 that outputs an end signal when the end signal from C21 and the access request signal from the CPU 11 are both asserted, and the upper address during the execution of a series of CPU cycles for timing the lower address output. It is composed of a CPU access continuous execution circuit 22 having a high-order address latch 36 for holding it, and a VRC 21 for executing CPU access to the V-RAM 12 in accordance with the output of the CPU 11 input via the CPU access continuous execution circuit 22.

The CPU cycle continuation determination circuit 31 is
In response to the access request signal from the CPU 11, the lower address, the data size required by the CPU 11 and the bus width which is known in advance at the stage of circuit design are examined to determine whether or not the data is insufficient. If it is determined that the CPU access is insufficient, immediately after the end of the current CPU cycle, it is predicted in advance that a CPU access due to dynamic bus sizing will occur, and the access request generation circuit 34 issues an access request instead of the access request from the CPU 11. Output the determination signal.

The access request generation circuit 34 starts the first CPU cycle by an access request from the CPU 11, but the CPU cycle continuation determination circuit 31.
CPU with dynamic bus sizing in
When an access is predicted to occur, the access request generation circuit 34 does not wait for the access request from the CPU 11.
Independently outputs the second and subsequent access requests. That is, it is a circuit that takes the OR logic of the access request signal from the CPU 11 and the request signal from the CPU cycle continuation determination circuit 31.

The lower address and data size generation circuit 32 outputs the lower address and data size output from the CPU 11 to the VR 21 through the selector 33 as they are in the first data cycle, and the CPU cycle continuation determination circuit 31. If a CPU access is predicted to be generated by, the lower address and the data size of the CPU cycle that will occur next are generated in advance (during execution of the current CPU cycle) and held for a required period to hold the selector 33.
Output to.

The selector 33 selects data so that the VRC 21 operates on the basis of the address and size signals sent from the CPU 11 in the first CPU cycle, and the second and subsequent CPU cycles 22 by dynamic bus sizing. Selects the data so that the VRC21 operates according to the address and size signals generated by the lower address and data size generation circuit 32.

The end signal generating circuit 35 is the first CP
The end signal from the U cycle VRC21 is directly sent to the CPU 11
When the end signal from the VRC 21 and the request signal from the CPU 11 are both asserted in the second and subsequent CPU cycles, it is meaningless to return the end signal to the CPU 11 by returning the end signal to the CPU 11. This is because the cycle cannot be completed until there is an end signal from the VRC 21 even if there is an access request from the CPU 11.

Next, the operation of this embodiment will be described. FIG. 3 is a timing chart showing a read access from the CPU 11. As shown in FIG. 3, when the access request from the CPU 11 is asserted, the V-RAM controller 13 side recognizes the access from the CPU 11 at the timing of FIG. To work). That is,
The access request signal from the CPU 11 is ORed by the access request generation circuit 34 together with the output from the CPU cycle continuation determination circuit 31, and the access request generation circuit 3
The output of 4 serves as an access request signal to the VRC 21 (see FIG. 3A). The VRC 21 accesses the V-RAM 12 by the above access request signal, and the end signal generation circuit 35 takes an AND logic between the end signal from the VRC 21 and the access request from the CPU 11 and the end signal generation circuit 35.
Is returned to the CPU 11 as an end signal (see FIG. 3C). Then, the CPU 11 recognizes the end signal returned during the CPU cycle and once drops the request (see FIG. 3D). At this time, if the data requested by the CPU 11 is insufficient, it is necessary to access the insufficient data.
The V-RAM controller 13 uses the CPU cycle continuation determination circuit 31 in order to continuously execute the CPU cycle.
Signal (see FIG. 3E) is complemented to the CPU access request (OR logic is taken) and asserted. The CPU access request and CPU cycle continuation determination circuit 31
The access request signal from V.sub.1 is ORed to form an access request signal to the VRC 21, and the CPU cycle can be executed twice consecutively as shown in FIG. Also, CP
The upper address from U11 is latched and held by the upper address latch 36 (see FIG. 3C).

FIG. 4 shows the read access from the CPU 11 to the CPU 11 side and the V-RAM controller (VRC).
13 is a flowchart showing the respective operations separately for the 13 side, and is a flowchart when two data transfers are required. The same applies when data transfer is required three times or more.

Cycle 1 (Other Cycles) When the CPU 11 makes a read access to the V-RAM 12 (step P1), the V-RAM controller 13 causes C
Access from PU11 is recognized (step S1)
1).

Cycle 2 (CPU Cycle) The V-RAM controller 13 starts a CPU cycle (step S12), reads data from the V-RAM 12 and transfers it to the CPU 11 (step S13). In parallel with this, the V-RAM controller 13 recognizes the size signal from the CPU 11, the lower address, and the bus size of the V-RAM 12, and then C again after the current CPU cycle.
Predict that a PU cycle will occur. That is, V
-CP when reading data from RAM 12
Whether or not the U cycle is completed is compared with the transfer request data size from the CPU 11 and the bus width of the V-RAM 12, etc. For example, when the data bus is 16 bits for a data request of 16 bits, the insufficient data If not, the CPU cycle is completed (YES in step S14), and if the data is insufficient, or C
If it can be predicted in advance that data will be transmitted from the PU 11, the process proceeds to step S15 and the V-RAM controller 13 asserts an end signal to the CPU 11.

Cycle 3 (CPU cycle) Since the V-RAM controller 13 asserts the end signal, it reads the insufficient data from the V-RAM 12,
A new address is generated and the CPU cycle is restarted independently (step S16). On the other hand, the CPU 11 recognizes the incompleteness of the cycle by the received end signal similarly to the conventional example and determines whether or not the access is completed (step P2), and when the access is completed (that is, the requested data is insufficient). (When there is no data), the CPU 11 ends the read access process and proceeds to another process.
At 3, the V-RAM read cycle is restarted for insufficient data.

That is, in step S15, V-RA
When asserting the end signal, the M controller 13 predicts the next CPU cycle in advance and restarts the CPU cycle for the V-RAM 12 (step S1).
6) In parallel with this, the CPU 11 recognizes whether or not the data is sufficient, and when there is a shortage of data, VR
Access to AM (steps P2 and P3). The processing on the CPU 11 side is the same as the conventional example,
In the conventional example, the V-RAM controller 13 waited for an access request from the CPU at this time, but the V-RAM controller 13 predicts the next CPU cycle in advance as described above.
For 2, the CPU cycle is restarted independently.

The V-RAM controller 13 is C
Recognize access from PU11 (step S18)
It is determined whether the access is completed (step S1
9) When the access of the V-RAM controller 13 is completed, the end signal is asserted to the CPU 11 (step S20).

Cycle 4 (Other Cycle) The V-RAM controller 13 starts another cycle (step S21), and the CPU 11 recognizes the completion of the V-RAM read cycle in cycle 4 and access is completed. It is determined whether or not it has been completed (step P
4) When all the missing data is read (Y in P4)
ES) completes the V-RAM read access in step P5. When the access is not completed, the third data transfer is executed in the same manner as above.

As described above, the V-RAM controller 13 receives the access request signal from the CPU 11 and examines the lower address and the data size requested by the CPU 11 to determine whether to continue the CPU cycle. A CPU cycle continuation determination circuit 31, a lower address and data size generation circuit 32 that generates in advance a lower address and data size of a CPU cycle that will occur next, and an address and size signal sent from the CPU 11. A selector 33 that selects and outputs the generated address and size signal and an access request generation circuit 34 that independently outputs the access request without waiting for the access request from the CPU 11 are provided, and the VR of the CPU 11 is provided.
By examining the size signal, the address signal, and the bus size of the V-RAM 12 during the execution of the AM read access, it is predicted in advance that the CPU access due to the dynamic bus sizing will occur again after the end of this cycle. However, since the CPU cycle is restarted independently in preparation for it, the wait time of the CPU 11 can be eliminated and the performance can be improved. That is, in the case of the conventional example, as shown in FIG. 5 and FIG.
While the U read cycle is executed every other cycle, in the case of this embodiment, the CPU cycle can be continuously executed, and the wait cycle in this period can be deleted. In general, one cycle of VRC corresponds to the number of CPU clocks to several tens of clocks, and it is extremely effective to remove the wait state of the CPU during this period, and the greater the required number of transfers, the greater the effect. As a result, it is possible to minimize the decrease in the performance of the CPU 11 and improve the read access to the V-RAM 12.

In this embodiment, as the storage element, VR
Although the AM is used, it goes without saying that it is not limited to the V-RAM as long as it controls the memory according to the CPU access request. Needless to say, the number and types of circuits shown in this embodiment are not limited to those in the above embodiment.

[0025]

According to the present invention, a series of CPU leads
The cycle can be continuously executed, and the CPU performance can be improved by removing the wait state of the CPU.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of the present invention.

FIG. 2 is a block configuration diagram of a memory control device.

FIG. 3 is a timing chart showing a read access from the CPU of the memory control device.

FIG. 4 is a timing chart for explaining operations of a CPU and a V-RAM controller of the memory control device.

FIG. 5 is a timing chart showing a read access from a CPU of a conventional memory control device.

FIG. 6 is a timing chart for explaining operations of a CPU and a V-RAM controller of a conventional memory control device.

[Explanation of symbols]

 11 CPU 12 V-RAM 13 V-RAM controller (VRC) 22 CPU access continuous execution circuit 31 CPU cycle continuation determination circuit 32 Lower address and data size generation circuit 33 Selector 34 Access request generation circuit 35 End signal generation circuit 36 Upper address latch

Claims (2)

[Claims] 1. A memory control device for controlling a memory in response to an access request from a CPU, wherein the data size of data read from the memory is smaller than the data size requested by the CPU, and the determination means. A memory control device comprising: an execution unit that starts a CPU cycle that enables data reading from the memory based on a determination result of the unit, and continuously executes a read access from the CPU. .. 2. A memory control device for controlling a memory according to an access request from a CPU, wherein when data of a predetermined address is read from the memory,
If the data size of the memory is smaller than the data size of the CPU access, the next address is supplied to the memory after reading the first data, and the second read access is executed. apparatus.