JPH05158572A - Clock/voltage margin testing system - Google Patents

Abstract

PURPOSE:To remarkably curtail a testing process by executing automatically and continuously a clock/voltage margin test. CONSTITUTION:A test program is stored in advance in a disk device 9. A test pattern and an initial value of a clock/voltage at the time of starting a test are stored in a RAM 1a in a diagnostic device 1. To an output of the RAM 1a, a first decoder 4 for decoding the test pattern and a second decoder 5 for decoding the initial value of the clock/voltage at the time of starting the test are connected. By a first decoder 4 and a second decoder 5, a clock initial value setting part 6a, a clock fluctuating part 6b, a voltage initial value setting part 7a and a voltage fluctuating part 7b are selected. Also, the diagnostic device 1 is provided with a system-down check part 1b for monitoring an abnormal stop in the course of test, and the diagnostic device 1 instructs to store a value of the clock/voltage at the time of abnormal stop, its time and a test item in a limit point tracing circuit 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock / voltage margin test, and more particularly, it enables an automatic continuous margin test by fixing either the clock frequency or the voltage used in an information processing device and varying the other. The present invention relates to a clock / voltage margin test method for executing.

[0002]

2. Description of the Related Art In a conventional clock / voltage margin test, an external device for varying the clock frequency and voltage is first prepared outside the information processing device before the test, and the clock generation source actually used. And disconnect the power supply device and connect it to the information processing device. Next, after this connection, manually start the information processing device and start the test program, set either the clock frequency or voltage to a fixed value with the connected external device, and manually change the other. I will let you.

Since the information processing apparatus abnormally stops when it reaches a certain limit during the fluctuation, the values of the clock frequency and the voltage at this time are recorded. In addition, in order to collect a large number of different clock / voltage limit points, the information processing apparatus is restarted after each abnormal stop and the test program is started, and the above-described operation is repeated. Also, after collecting a large number of clock frequency / voltage limit points, by manually plotting this data in a graph, a clock / voltage margin characteristic graph is created to grasp the margin for the clock / voltage of the information processing device. Was.

[0004]

However, in such a conventional clock / voltage margin test method, the clock source and the power supply device which are actually used are separated from each other,
There is a drawback in that it is necessary to connect an external device for changing the clock frequency and the voltage. Further, when collecting a large number of limit points of the correlation between the clock and the voltage in this information processing apparatus, every time the sampling is attempted, the information processing apparatus is started up, the test program is activated, and either the clock or the voltage is fixed. And the fluctuations have to be done manually. Further, there is a drawback in that it is necessary to record the data collected during the test each time and create a clock / voltage margin characteristic graph based on the data.

The present invention has been made in view of the above points, and an object thereof is to eliminate the above-mentioned conventional drawbacks and to significantly reduce the man-hours spent for the test.

[0006]

In order to achieve the above object, a clock / voltage margin test system according to the present invention comprises:
The measurer should provide the test pattern for fixing the clock or voltage and changing the other to perform a margin test, and the combination data of the clock frequency or the initial value of the voltage at the start of the test that is fixed for each test pattern. A RAM for storing the generated one as a continuous margin test pattern, a first decoder for decoding the output of the test pattern data in the RAM, and an output of the initial value data at the start of the test in the RAM. A second decoder for decoding, a clock initial value setting unit for setting the clock frequency at the start of the test by the outputs of the first and second decoders, and a clock changing unit for changing the clock frequency by the output of the first decoder The clock setting circuit having the above and the outputs of the first decoder and the second decoder determine the voltage at the start of the test. Constituted by the voltage setting circuit having a voltage variation unit that varies the voltage by the output of the voltage initial value setting unit and said first decoder to Tsu and.

A clock / clock according to another invention of the present invention
The voltage margin test method in the above is equipped with a system down check unit in the diagnostic device that monitors the state when the information processing device abnormally stops when the clock frequency or voltage is changed, A limit point trace circuit that collects voltage and stops when the information processing device abnormally stops according to an instruction from the system down check unit, and retains the clock frequency, voltage value, time, and test pattern item information at that time. Is equipped with.

[0008]

Therefore, according to the present invention, the RA in the diagnostic device is
By storing in advance the test pattern and the initial value of the clock / voltage at the start of the test in M, a large number or continuous points of the clock / voltage limit points can be automatically collected. Further, according to another aspect of the present invention, it is possible to automatically collect a clock / voltage margin characteristic graph showing a clock frequency and a voltage value when the information processing apparatus is stopped.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment for realizing a clock / voltage margin test according to the present invention.
2 and 3 are examples of test patterns to be stored in the RAM shown in FIG. 1 and clock frequency, voltage, time, and sampling data of test pattern items when the system stored in the limit point trace circuit abnormally stops. Are shown respectively.

In FIG. 1, the test program is stored in a disk device 9 provided inside the information processing apparatus, and when the information processing apparatus starts up, the diagnostic apparatus 1 automatically loads the test program into the main storage device 10. Start running. The clock generation source 2 and the power supply device 3 are used during normal operation of the information processing device, and are distributed inside the information processing device via the clock setting circuit 6 and the power supply setting circuit 7, respectively. ..

Further, in the test apparatus 1, a RAM 1a for storing a test pattern and an initial value of a clock / voltage at the start of the test as a margin test item, and a system down check section 1b for monitoring an abnormal stop during the test. A first decoder 4 for decoding the test pattern and a second decoder 5 for decoding the initial value of the clock / voltage at the start of the test are connected to the output of the RAM 1a.

Further, the clock setting circuit 6 uses the outputs of the first decoder 4 and the second decoder 5 to set a clock frequency at the start of the test, which is a clock initial value setting section 6a.
And a clock changing unit 6b that changes the clock frequency by the output of the first decoder 4. The voltage setting circuit 7 is a voltage initial value setting unit 7 for setting the voltage at the start of the test by the outputs of the first decoder 4 and the second decoder 5.
a and a voltage fluctuating section 7b that fluctuates the voltage according to the output of the first decoder 4.

Further, the limit point trace circuit 8 constantly collects the clock frequency and voltage from the clock line 12 on the output side of the clock setting circuit 6 and the power line 13 on the output side of the voltage setting circuit 7, and the information processing apparatus is abnormal. When stopped, the system is stopped by an instruction from the trace stop line 11 of the system down check unit 1b, and the information of the clock frequency, voltage value, time and test pattern item at that time is held.

Next, the operation of the clock / voltage margin test will be described. Before starting this test, first determine the test pattern of whether clock or voltage is fixed and which is changed, and the initial value at the start of the test on the side where the fixed setting is selected, and then carry out this combination data. R in the diagnostic device 1 with the number of test times of
It is stored in AM1a (see FIG. 2).

However, at the start of the test, the diagnostic device 1 has a RAM.
The contents of 1a are output. Then, the first decoder 4 for decoding the test pattern and the second decoder 5 for decoding the initial value at the start of the test are connected to the output of the RAM 1a, whereby the items to be tested are judged. For example, when item 1 is selected in the test pattern in the RAM 1a shown in FIG. 2, the clock is set to the initial value A and the voltage is increased. In this case, the clock initial value setting unit 6a and the voltage changing unit 7b are controlled. When item 4 is selected, the voltage is set to the initial value b and the clock frequency is lowered. In this case, the voltage initial value setting unit 7a and the clock changing unit 6b are controlled.

When the clock or voltage limit point is reached and the system stops abnormally while the clock frequency or voltage is being changed, the system down check unit 1b in the diagnostic device 1 confirms that the diagnostic device 1 is running. At the same time as collecting the fault information at this time, trace stop line 1
1 instructs the limit point trace circuit 8 to store the clock frequency value, voltage value, time and test item at that time (see FIG. 3).

Subsequently, the diagnostic apparatus 1 refers to the test schedule in the RAM 1a and if there are remaining test items, resets the system and automatically restarts the system before executing the next test pattern. After that, the test program in the disk device 9 is activated to perform the clock / voltage margin test according to the schedule. The data collected for each test item will be held in the limit point trace circuit 8.

[0018]

As described above, according to the present invention, the test program is stored in the disk device and activated by the instruction of the diagnostic device, and the RAM for storing the test items is provided in the diagnostic device. Moreover, by having a decoder for reading and understanding the contents of RAM and a circuit for setting and changing the clock / voltage, it is possible to start the test program, restart the system, set and change the clock and voltage without human intervention. This makes it possible to collect a large number of clock / voltage limit points continuously.

Another aspect of the present invention is to provide a system down check section for monitoring an abnormal stop of the system and a limit point trace circuit for collecting a clock / voltage at the time of the abnormal stop so that a clock / voltage for each test is obtained. The relational limit points can be automatically recorded and edited as a clock / voltage margin characteristic graph.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a clock / voltage margin test system according to the present invention.

FIG. 2 is a diagram showing an example of a test pattern stored in a RAM shown in FIG.

3 is a diagram showing an example of sampling data of clock / voltage / time / test item stored in the limit point trace circuit of FIG. 1 at the time of system abnormal stop.

[Explanation of symbols]

 1 Diagnostic Device 1a RAM 1b System Down Check Unit 2 Clock Generation Source 3 Power Supply Device 4 First Decoder 5 Second Decoder 6 Clock Setting Circuit 6a Clock Initial Value Setting Unit 6b Clock Fluctuation Unit 7 Voltage Setting Circuit 7a Voltage Initial Value Setting Unit 7b Voltage fluctuation part 8 Limit point trace circuit 9 Disk device 10 Main memory device 11 Trace stop line 12 Clock line 13 Power line

Claims (2)

[Claims] 1. A test pattern in which either a clock frequency or a voltage used inside an information processing device is fixed and the other is varied to perform a margin test, and a test pattern on the side fixedly set for each test pattern at the start of the test. A RAM storing previously generated data in which initial values of clock frequency or voltage are combined as a continuous clock / voltage margin test item, and a first decoder for decoding the output of the test pattern data in the RAM. A second decoder for decoding the output of the initial value data at the start of the test in the RAM; and a clock initial value setting unit for setting the clock frequency at the start of the test by the outputs of the first and second decoders. And a clock setting circuit having a clock changing unit that changes the clock frequency by the output of the first decoder, The voltage setting circuit includes a voltage initial value setting unit for setting a voltage at the start of the test by outputs of the first decoder and the second decoder, and a voltage setting circuit having a voltage changing unit for changing the voltage by the output of the first decoder.
A clock / voltage margin test method that features automatic and continuous margin testing. 2. The clock / voltage margin test method according to claim 1, wherein a system down check unit for monitoring a state when the information processing device abnormally stops when the clock frequency or the voltage is changed is provided in the diagnostic device. In addition, the clock frequency and voltage are constantly collected, and when the information processing device stops abnormally, it is stopped by the instruction of the system down check unit, and the information of the clock frequency, voltage value, time and test pattern item at that time is held. A clock / voltage margin test method characterized in that a clock / voltage margin characteristic graph showing a clock frequency and a voltage value when the information processing apparatus is stopped is automatically provided with a limit point trace circuit.