JPH05153403A - Discrete cosine transformation device - Google Patents

Abstract

PURPOSE:To provide the discrete cosine transformation device whose configuration is simple with respect to the discrete cosine transformation device implementing the arithmetic operation of two-dimension discrete cosine transformation. CONSTITUTION:The discrete cosine transformation device is two-dimension discrete cosine transformation device having a 1st linear discrete cosine transformation circuit, a transposition circuit and a 2nd linear discrete cosine transformation circuit, and the 1st and 2nd linear discrete cosine transformation circuits have respectively the linear discrete cosine processing circuits (105,115) and a preprocessing circuit and a post-processing circuit connecting respectively to the input side and the output side, the pre-processing circuit of the 1st linear discrete cosine processing circuit and the post-processing circuit of the 2nd linear discrete cosine processing circuit include a 1st butterfly circuit (103) used in common/and the post-processing circuit of the 1st linear discrete cosine processing circuit and the pre-processing circuit of the 2nd linear discrete cosine processing circuit include a 2nd butterfly circuit (107) used in common.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a discrete cosine transform (D
CT), and more particularly to a discrete cosine transformer that performs a two-dimensional discrete cosine transform operation.

DCT is known as a conversion method suitable for compressing image data. There is a forward DCT that transforms image data into frequency components and a reverse DCT (IDCT) that restores image data by performing inverse transformation. In this specification, both are referred to as DCTs, and when only one is designated, These will be referred to as forward (forward) DCT and reverse (reverse) DCT.

[0003]

2. Description of the Related Art In recent years, DCT, which is one of orthogonal transform methods, has been widely adopted as a data compression method.

FIG. 3 shows an image data compression technique using DCT. As shown in FIG. 3A, the target screen 5
Divide 0 into small subsections 51. The small section 51 has a size of 8 pixels × 8 pixels, for example. That is, the subdivision 51 constitutes a square matrix of 8 rows and 8 columns including 64 elements. The image information of the screen 50 is processed for each small section 51.

As shown in FIG. 3B, the image data 52 of the small section 51 is processed by the forward DCT processor 53 to obtain a DCT coefficient (F) 54. This DCT coefficient 54
Are frequency-analyzed image information in the row and column directions. The DCT coefficient 54 is processed by the threshold processing device 55, and data below a certain value is truncated. Next, in order to shorten the non-zero data length, the normalization processing device 56 divides the data by a constant value to obtain shortened data 57.

The image data 57 thus obtained
, Both non-zero and zero are mixed, but the high frequency components are almost zero. For non-zero data, Huffman coding is performed and the data is further compressed. In addition, zero-length data is subjected to run-length coding, a block of zeros is treated as one piece of data, and Huffman coding is further performed.

When the original image is reproduced from the compressed data obtained in this way, the Huffman coding is first performed to reproduce the image data 57, and then the reverse process of the normalizing process is performed. Image information is reproduced by performing reverse DCT processing which is the reverse processing of directional DCT processing.

FIG. 3C shows the forward direction D shown in FIG.
The content of CT processing is shown. The image data f is sandwiched between the transposed cosine coefficient matrix D ^t and the cosine coefficient matrix D, and a DCT coefficient F is obtained by performing a matrix operation.

When the forward DCT process is further developed, it can be expressed as F = D ^t fD = {(fD) ^t D} ^t . That is, the image data f is multiplied by the cosine coefficient matrix D from the right side to perform the frequency analysis in the row direction, the obtained matrix is transposed to transform the row direction and the column direction, and then the cosine coefficient matrix D is again multiplied. By performing frequency analysis in the column direction and transposing, the row direction and the column direction are restored to the original state, and the DCT coefficient F obtained by frequency-analyzing the image information in the row direction and the column direction can be obtained. In order to perform such calculation, it is necessary to repeat matrix multiplication twice.

FIG. 4 shows a transform coefficient matrix used for the forward DCT transform and the inverse DCT transform when the block size is 8 × 8. FIG. 4A shows the cosine coefficient matrix D and the transposed cosine coefficient matrix D ^t .

When the forward DCT transform is performed according to the above formula, the cosine coefficient matrix D is stored in the memory,
The input signal and the cosine coefficient matrix D may be multiplied (sum of products operation).

[0012] Incidentally, the inverse DCT transform becomes a calculation to reproduce the image information f from the DCT coefficients F, is expressed as ^{f = DFD t = (F t} D t) t D t = {(FD t) t D t} t It

Therefore, in order to perform the inverse DCT transform,
The DCT coefficient F is multiplied by the transposed cosine coefficient matrix D ^t from the right, the obtained result is transposed to exchange rows and columns, the transposed cosine coefficient matrix D ^t is again multiplied from the right, and the obtained result is transposed. Then you can restore the rows and columns to their original state.

When both the image data f and the cosine coefficient matrix D are 8 × 8 matrices, the multiplication is an 8 × 8 matrix multiplication. To perform such forward DCT or inverse DCT processing, eight multipliers are used.

By the way, the cosine coefficient matrix D is observed.
And in each column, the 1st to 4th rows and the 5th to 8th rows are coded.
You can see that it has a symmetrical structure. sand
That is, the element of a column of the cosine coefficient matrix D is D₀~ D₇
Then, D₀= ± D₇, D ₁= ± D₆, D₂= ±
D_Five, D₃= ± D_FourHave a relationship. Also, this code is a column
Is determined by the plus, and odd columns are positive and even columns are my.
It becomes eggplant.

Therefore, it is possible to combine the multiplications of these coefficients that are equal to each other, and it is possible to execute the product-sum operation once by performing the multiplications four times. A DCT transform using a high-speed algorithm is also proposed by utilizing the symmetry of such a transform matrix.

By the way, the coefficient of the sum of products operation in the DCT transform is determined by the block size and is fixed. Therefore, the DCT operation can be performed by storing the operation result in the ROM and using it as a lookup table.

As one method of matrix multiplication, DA (Dist
Ribbed Arithmetic) algorithms are known. Consider a matrix multiplication of Y = A · X. X is m bits. The matrix operation for one column is expressed as follows.

[0019]

[Equation 1]

[0020] In this ^{case, X = -x (m-1} ) · 2 m-1 + Σ M x
^(M) · 2 ^M. Therefore, the equation (i) is Y _i = Σ _j A _ij X _j = Σ _j (−A _ij x _j ^(m-1) · 2 ^(m-1) + Σ _M A _ij x _j ^(M) · 2 ^M )… (Ii) However, x ^(M) represents the M-th bit of X, and its value is "0" or "1".

The equation (ii) is further expressed as Y _i = − (Σ _j A _ij x _j ^(m-1) ) × 2 ^m-1 + Σ _M (Σ _j A _ij x _j ^(M) ) × 2 ^M To be done. The first term on the right side shows the sign bit, and the second term shows the multiplication for each bit of X. Where x _j ^(M)
Is "0" or "1", and if A is a matrix of n rows and n columns, j = 0 to (n-1) of A _ij is added.

Therefore, if () is constructed by a look-up table by x _j , Y _i of matrix multiplication can be calculated by shift and addition / subtraction by bit position.
In the case of configuring the DCT operation by hardware, if a multiplier is used to increase the speed, the hardware becomes large. Therefore, it is not desirable to use the multiplier as much as possible. The DA algorithm is suitable as a method for performing multiplication without using a multiplier.

FIG. 5 shows an example of a two-dimensional DCT arithmetic circuit using such a DA algorithm. FIG. 5A shows D
The overall structure of the CT arithmetic circuit is schematically shown, FIG. 5B shows the structure of the one-dimensional processing unit, and FIG.
3 shows the configuration of a DA product-sum operation block in the dimensional processing unit.

In FIG. 5A, input data is input to the one-dimensional DCT processing unit 61, DCT conversion is performed using the look-up table, and the output is supplied to the shift / round circuit 62. The shift / round circuit 62 is D
The signal whose number of bits has been increased by the CT processing is aligned again with the desired number of bits, and rounding processing is performed.

The output of the shift / round circuit 62 is supplied to the transposing RAM 63, and rows and columns are exchanged. The transposed signal is supplied to another one-dimensional DCT processing unit 64, frequency analysis is performed in the other direction, and the signal is shifted / shifted.
It is supplied to the round circuit 65. The shift / round circuit 65 aligns the number of bits again and performs rounding processing to form output data.

FIG. 5B is a one-dimensional D shown in FIG.
1 schematically shows the configuration of each of the CT processing units 61 and 64. That is, in the one-dimensional DCT processing unit,
The input data is supplied to the preprocessing circuit 66 to form the appropriate input signal combination. The input signal thus converted is input to the DA product-sum operation blocks 67 and 68 which are divided into two sets.

For example, when the image signal is an 8 × 8 block, eight input signals are supplied as input data, four sets of signals supplied by the preprocessing circuit 66 are supplied to the DA product sum operation block 67, and others. 4 sets of DA product-sum operation block 6
8 are supplied.

As described above, it is preferable to divide the DA product-sum operation block into two because the size of the look-up table is not made too large and the symmetry of the DCT transformation matrix is utilized. The output signals of the DA product-sum operation blocks 67 and 68 are supplied to the post-processing circuit 69, where the number of bits is reduced and rounding processing is performed. In this way, output data is generated from the post-processing circuit 69.

FIG. 6 shows such a lookup table.
A basic configuration of a DCT arithmetic processing circuit using is shown. n
The input signal stores a look-up table for DCT transformation
Is supplied as an address to the coefficient ROM 81 for
Multiply-accumulate operation is performed by using a table. Looka
The output signal of the up table 81 is the input x_jIs a sign
In the case of G, the sign 8 is inverted by the signal Ts and
Output signal Y via 3 _iTo form.

The output signal Y _i is _supplied to the coefficient circuit 84.
Is multiplied by 1/2 and returned to the adder 83. Next, the input signal on 1 bit is the lookup table 81.
Is supplied to the adder 83, and the output signal is supplied to the adder 83. For this output signal, the coefficient circuit 84
The result of the previous calculation, which has been digit-matched via the, is added to form a new output signal Y _i . At this time, the coefficient circuit 84 is used to align the bit positions.

If each input signal has 15 bits, the operation usually requires 15 cycles. However, in order to process an 8 × 8 block in real time, even if a pipeline is used, the calculation must be completed within 8 cycles. Therefore, it is possible to complete the arithmetic processing in 8 cycles by extracting the input signal every 2 bits and doubling the lookup table.

By the way, as is apparent from the transformation matrix of FIG. 4A, the cosine coefficient matrix D has a configuration in which 1 to 4 rows and 5 to 8 rows of each column are symmetrical. Therefore, the same lookup table can be used for the first to fourth rows and the fifth to eighth rows of the conversion matrix. Therefore, enter 8
It is effective to divide each signal into groups of four and use a lookup table for each group.

In FIG. 7, in the DCT conversion of the 8 × 8 structure, the input signal is divided into groups of four and each signal is divided into two groups.
The structure of the DCT arithmetic circuit which supplies bit by bit is shown. The coefficient ROM 81a and the coefficient ROM 81b have look-up tables of the same structure, and input a set of upper bits and a set of lower bits of four input signals. The output signal of the look-up table 81b for inputting the lower bit is halved by the coefficient circuit 86, and is added to the output signal of the look-up table 81a for the upper bit in the adder 82.

When the input is a sign bit, the signal T
The sign is inverted by s, added, and forms the output signal Y _i via the adder 83. Also, this output signal Y
_i is fed back to the adder 83 via the coefficient circuit 87.
The coefficient circuit 87 multiplies the output signal Y _i by 1/4 and adds it to the adder 83.
Return to. This is to adjust that the same numerical value becomes four times larger in the subsequent calculation because the calculation is performed every two bits.

FIG. 5C is a one-dimensional DCT of FIG. 5B.
The structure of the DA product-sum operation block used in a processing unit is shown. Each DA product-sum operation block inputs four sets of input signals in units of 2 bits.

These four sets of input signals of 2 bits each are
It is divided into upper bits and lower bits, the lower bits are supplied to the lower bit lookup table 71a or 72a, and the upper bits are supplied to the upper bit lookup table 71b or 72b.

That is, the lower bit look-up tables 71a and 72a and the upper bit look-up tables 71b and 72b have different bit positions, but receive the same combination of input signals and perform the same conversion.

Look-up table 71 for lower bits
The output signals of a and 72a are supplied to the coefficient circuit 73, and 1
It is multiplied by 2 and supplied to the adder 74. The output signals of the high-order bit look-up tables 71b and 72b are directly supplied to the adder 74.

The coefficient circuit 73 aligns the numbers of digits of the high-order bits and the low-order bits, and the adders 74 add them. The output signal of the adder 74 is supplied to the accumulator 75 to form a cumulative sum. The accumulator 75 includes an adder 74, a register 78, and a shifter 7.
The output signal including 9 is bit-shifted by the shifter 79 and fed back to the adder 77.

In this way, the adder 77 adds the previous output signal and the present output signal and stores them in the register 78. For example, if you want to calculate from the least significant bit first,
The shifter 79 multiplies the output by 1/4 and aligns the digits with the next calculation. When the calculation is performed from the upper bits, the shifter 79 multiplies the output signal by 4 and performs digit alignment with the next calculation.

In this way, the DCT operation is performed using the DA product sum operation block of FIG. 5 (C). In the case of the inverse DCT calculation, the transformation matrix is the transposed matrix D ^t shown in FIG. D ^t does not have the symmetry like the transformation matrix D, but if the odd and even rows are considered separately, the first and eighth columns, the second and seventh columns, the third and third columns, respectively. The sixth row, the fourth row, and the fifth row each have a symmetrical configuration.

Therefore, in the case of the inverse DCT operation, the forward DCT is performed by separating the transform matrix into odd rows and even rows.
The lookup table can be reduced similarly to the conversion.
Table 1 shows the contents of the look-up table when the configuration of FIG.

[0043]

[Table 1]

[0044]

[Table 2]

[0045]

[Table 3]

[0046]

[Table 4]

[0047]

[Table 5]

[0048]

[Table 6]

[0049]

[Table 7]

[0050]

[Table 8]

The forward DCT lookup tables in Tables 1 to 8 correspond to the first to eighth columns of the transformation matrix, and the input signals x1 to x4 are the first row to the transformation matrix.
Corresponds to line 4.

The lookup table for inverse DCT is shown in Table 1.
No. 0 of No. 1 and No. 1 of Table 2 correspond to the first and eighth columns, No. 0 corresponds to odd rows, and No. 1 corresponds to even rows. Similarly, the lookup table for inverse DCT is shown in Table 3.
No. 2 of Table 4 and No. 3 of Table 4 correspond to the second and seventh rows, No. 4 of Table 5 and No. 5 of Table 6 correspond to the third and sixth columns,
No. 6 in Table 7 and No. 7 in Table 8 correspond to the 4th and 5th columns.

Looking at the values of the look-up tables shown in Tables 1 to 8, for No. 1, No. 3, No. 5 and No. 7, the forward DCT look-up table and the inverse DCT look-up table are shown. Are the same. Therefore, the lookup table can be shared for these.

Basically, for each of the eight DA product sum operation blocks in FIG. 5 (B), as shown in FIG.
One lookup table is required, and the one-dimensional DCT transform is performed using 4 × 8 = 32 lookup tables. 32 × 2 to perform the two-dimensional DCT transformation
= 64 lookup tables are required.

However, as shown in Tables 1 to 8,
The forward DCT operation and the inverse DCT operation have a part in which the lookup table can be shared, and when these are shared, the number of lookup tables required is 48.

Further, the look-up table shown in Table 1 has higher symmetry, and by utilizing these, the structure can be further simplified. Figure 8
An example in which the configuration of the DCT conversion circuit is further simplified by using the symmetry of the lookup table will be shown. As shown in FIG. 8A, for example, a forward DCT lookup table No.
As for 0, if 8192 is equally subtracted from the numerical value of the content, the upper half and the lower half of the table are symmetrical.

That is, the contents of the lookup table can be halved by ORing the other bits exclusively with bit x4 and inverting the sign. FIG. 8B shows the configuration of a DA product-sum operation block using such symmetry. The look-up tables 88a and 88b have half the contents of the look-up tables 81a and 81b shown in FIG. 7, and input three types of input signals formed by the exclusive OR circuit.

The signal x4 is further supplied to the sign inverter through the exclusive OR circuit. Other configurations are the same as in FIG. 7. As described above, in order to simplify the configuration of the DCT operation processing device, it is necessary to use the symmetry of the cosine coefficient matrix or the transposed cosine coefficient matrix to simplify the operation.

Therefore, it is necessary to group input signals that use the same transform coefficient. A butterfly circuit, which is a combination of adder / subtractor circuits, is used to form a plurality of desired combinations of input signals from a plurality of input signals.

FIG. 2 shows an example of the configuration of a two-dimensional DCT calculation processing device in which the calculation result of the DCT calculation is used as a table in the ROM. The input signal is input to the shift register 121 and is supplied to the butterfly circuit 122 and the switching unit 123 in parallel. The butterfly circuit 122 forms a desired combination of input signals from the plurality of input signals and supplies the output to the switching unit 123.

Switching unit 123 determines which input signal is selected by the forward / reverse switching signal, which indicates whether the DCT arithmetic processing unit performs the forward DCT operation or the inverse DCT operation. The input signal selected by the switching unit 123 is supplied to the calculation ROM unit 124, and matrix calculation is performed.

The output signal of the operation ROM section 124 is supplied in parallel to the switching section 126 and the butterfly circuit 125. The butterfly circuit 125 creates a desired combination of a plurality of sets of input signals from the plurality of input signals and supplies the output signal to the switching unit 126.

Switching unit 126 determines which input signal is selected according to the forward / reverse switching signal indicating whether to perform the forward DCT operation or the inverse DCT operation. The signal selected by the switching unit 126 is the accumulator 1
27, and the operation results for each bit, which are sequentially supplied, are added.

The output signal of the accumulator 127 is supplied to the transposition circuit 130 via the shift register 128,
Transpose rows and columns. The signal transposed by the transposition circuit 130 is another one-dimensional DCT having the same configuration as that described above.
The arithmetic processing unit is supplied.

That is, the other DCT arithmetic processing units include the shift register 131, the butterfly circuit 132, the switching unit 133, the arithmetic ROM 134, and the butterfly circuit 13.
5, a switching unit 136, an accumulator 137, a shift register 138, and corresponding constituent elements 121 to 128.
The same calculation is performed and the calculation result is supplied as an output signal.

[0066]

As described above,
When using the symmetry of the cosine coefficient matrix or the transposed cosine coefficient matrix for performing the DCT operation, two-dimensional D
Four butterfly circuits are required to perform the CT operation.

An object of the present invention is to provide a discrete cosine transformer having a simple structure.

[0068]

A discrete cosine transformer according to the present invention comprises a first one-dimensional discrete cosine transform circuit, a transposition circuit, and a second one-dimensional discrete cosine transform circuit.
A two-dimensional discrete cosine transformer, wherein the first and second
The one-dimensional discrete cosine transform circuit has a one-dimensional discrete cosine processing circuit, a pre-processing circuit and a post-processing circuit connected to the input side and the output side of the one-dimensional discrete cosine processing circuit, respectively. And a post-processing circuit of the second one-dimensional discrete cosine processing circuit, which includes a common first butterfly circuit, the post-processing circuit of the first one-dimensional discrete cosine processing circuit and the second butterfly circuit of the second one-dimensional discrete cosine processing circuit. The one-dimensional discrete cosine processing circuit is characterized by including a common second butterfly circuit with the processing circuit.

[0069]

When performing the forward DCT operation, the input signals input to the DCT operation circuit must form a desired combination by the butterfly circuit, but the output signal of the DCT operation circuit does not need to pass through the butterfly circuit. It can be supplied directly. Conversely, when performing the inverse DCT operation,
The input signal of the DCT arithmetic circuit does not need to pass through the butterfly circuit, and the output signal needs to be supplied to the butterfly circuit.

When performing a two-dimensional DCT operation, two of the four butterfly circuits are used, but the remaining two are not used. Therefore, when performing the two-dimensional DCT calculation, it is sufficient that two one-dimensional DCT calculation circuits and two butterfly circuits can be used.

In this way, when the two-dimensional discrete cosine transform is performed, the butterfly circuit is shared,
Two butterfly circuits can be omitted.

[0072]

1 shows the configuration of a two-dimensional DCT arithmetic processing unit according to an embodiment of the present invention. The plurality of input signals are supplied to the input buffer 101 and sent from the input buffer 101 to the selector 102.

The selector 102 directly supplies the input signal to the one-dimensional DCT arithmetic circuit 105, or the butterfly circuit 1
03 to supply. The output signal of the butterfly circuit 103 is supplied to the one-dimensional DCT circuit 105. That is, the input signal is one-dimensional DC by the selector 102.
It can be directly input to the T operation circuit 105 or can be input via the butterfly circuit 103.

The output signal of the one-dimensional DCT calculation circuit 105 is supplied to the selector 106. The selector 106 is
It is selected whether the input signal is directly supplied to the output buffer 108 or the butterfly circuit 107. The output signal of the buffer circuit 107 is supplied to the output buffer 108.

The output buffer 108 supplies the transposed circuit 110 with the signal subjected to the one-dimensional DCT operation processing. The transposition circuit 110 transposes the input signal and transforms the rows and columns of the matrix. The matrix signal whose rows and columns have been converted is the transposition circuit 110.
From the input buffer 111 to the selector 112.

The selector 112 directly supplies the input signal to the one-dimensional DCT arithmetic circuit 115 or the butterfly circuit 1
Select whether to supply to 07. The output signal of the butterfly circuit 107 is supplied to the one-dimensional DCT arithmetic circuit 115.

The output signal of the one-dimensional DCT calculation circuit 115 is supplied to the selector 116. The selector 116 is
It is selected whether the input signal is directly supplied to the output buffer 117 or the butterfly circuit 103. The output signal of the butterfly circuit 103 is supplied to the output buffer 117. The output buffer 117 supplies the output signal subjected to the two-dimensional DCT calculation process.

In the case of the forward DCT operation, the selector 102 supplies the input signal to the butterfly circuit 103, and the selector 1
06 supplies the input signal directly to the output buffer 108.
On the other hand, the selector 112 outputs the input signal to the butterfly circuit 10.
7, and the selector 116 supplies the input signal directly to the output buffer 117.

In this way, the butterfly circuit 103 forms the input signal of the first one-dimensional DCT arithmetic circuit 105, and the butterfly circuit 107 forms the input signal of the second one-dimensional DCT arithmetic circuit 115.

In the inverse DCT operation, the selector 102
Supplies the input signal directly to the one-dimensional DCT arithmetic circuit 105, and the selector 106 supplies the input signal to the butterfly circuit 107.
Supply to. In addition, the selector 112 directly inputs the input signal to 1
The three-dimensional DCT calculation circuit 115 is supplied, and the selector 116 supplies the input signal to the butterfly circuit 103.

As described above, the butterfly circuit 107 has the first
Of the output signal of the one-dimensional DCT arithmetic circuit 105 of
The butterfly circuit 103 is the second one-dimensional DCT arithmetic circuit 1
The output signals of 15 are added and subtracted.

In this way, the two butterfly circuits 1
A two-dimensional DCT arithmetic processing unit can be configured with 03 and 107. The one-dimensional DCT calculation circuits 105 and 11
Reference numeral 5 may be for matrix multiplication or use of a ROM table.

FIG. 9 shows the configuration of a two-dimensional DCT calculation processing device having a DCT calculation result as a table in ROM. The input signal is supplied to the parallel / serial conversion circuit 14 directly via the input buffer 11 or via the butterfly circuit 103, becomes a serial signal, and is supplied to the ROM accumulator 15a.

The ROM accumulator 15a carries out a product-sum operation from the combination of input signals and outputs the result. The output signal of the ROM accumulator 15a can be the direct or butterfly circuit 1
It is supplied to the output buffer 18 via 07, and is supplied from the output buffer 18 to the transposing RAM 20.

The transposing RAM 20 transposes the rows and columns of the input matrix signal and outputs a transposed matrix. The transposed output is supplied from the input buffer 21 via the butterfly circuit 107 or directly to the parallel / serial conversion circuit 24.

The signal converted into the serial signal is stored in the ROM.
It is supplied to the accumulator 15b and DCT operation is performed. R
Like the ROM accumulator 15a, the OM accumulator 6b outputs the result of the product-sum calculation from the input signal.

The output signal of the ROM accumulator 15b is sent to the output buffer 28 directly or via the butterfly circuit 103 to form an output signal. In the case of forward DCT conversion, the butterfly circuit 103 is used in the first one-dimensional DCT conversion, and the butterfly circuit 107 is used in the second one-dimensional DCT conversion, as indicated by forward and reverse characters in the figure. used. The selector for distributing signals is not shown.

In the inverse DCT transform, the butterfly circuit 103 is used in the second one-dimensional DCT transform, and the butterfly circuit 107 is used in the first one-dimensional DCT transform.
In this way, the two-dimensional DCT arithmetic processing device can be configured using the two butterfly circuits.

The configuration of each part for further simplifying the configuration of the two-dimensional DCT arithmetic processing device will be described below.
FIG. 10 schematically shows the configuration of the ROM accumulator 15. In this configuration, a plurality of input signals are grouped in pairs and a lookup table is created for each group. The look-up tables 1a and 1b have input signals I, respectively.
Two bits of 1, I2 and I3, I4 are input and the corresponding output is supplied to the adder 2.

Since the look-up tables 1a and 1b operate on the input signals at the same bit positions, the bit positions of their outputs are the same and are simply added by the adder 2. The output of the adder 2 is supplied to the accumulator 6 and the cumulative sum is calculated. The accumulator 6 includes an adder 3, a register 4,
The input signal is stored in the register 4 via the adder 3 including the shifter 5, and the output of the register 4 is fed back to the adder 3 via the shifter 5.

Therefore, the previous value stored in the register 4 is supplied to the adder 3 via the shifter 5 and added with a new signal. In this way, the cumulative sum is calculated.

Similarly to the lookup tables 1a and 1b, the lookup tables 1c and 1b each receive two signals, that is, two bits of I5, I6 and I7, I8, and supply corresponding output signals.

In this way, by constructing a lookup table for inputting each input signal by 2 bits and selecting a combination of signals, the same lookup table can be commonly used for forward DCT conversion and inverse DCT conversion. The possibilities increase.

The case where the block size is 8 × 8 will be described below. When the block size is 8 × 8, the transformation matrix is as shown in FIG. It should be noted that the numerical values in this table give values shifted by 3 bits when the two-dimensional DCT conversion is performed.

The transform matrix D used for the forward DCT transform has a configuration in which the upper half and the lower half are symmetrical in each column, as described above. Therefore, if four input signals are prepared for each column, the DCT conversion operation can be performed.

By the way, since the transformation matrix D ^t used for the inverse DCT transformation is the transformation matrix D and the matrix is inverted, the symmetry like D is lost. However, the first of D ^t
Focusing on the column, the even rows are 5681, 4816, 3218, 1130 as shown in the column on the left side of FIG.
And is the same as the upper half of the second column of the transformation matrix D used for the forward DCT transformation. Further, as shown in FIG. 4A, the numerical values in the even-numbered rows of the eighth column of D ^t are −5681 and −481.
6, −3218, and −1130, which are different in sign from the even-numbered row in the first column, but have the same absolute value.

Therefore, as shown in FIG. 4A, the upper and lower sides of the second column of the transform matrix D used for the forward DCT transform have a symmetrical structure, and they are respectively the transform matrix D ^t used for the inverse DCT transform. The even-numbered rows in the first and eighth columns have a symmetrical configuration. If this symmetry is used, the lookup table can be shared.

The second column of the transform matrix D used for the forward DCT transform and the first column of the transform matrix D ^t used for the inverse DCT,
Having described the eighth row of symmetry, the third column of the same symmetry second row and the seventh row in the fourth column and the D ^t of D, the sixth column of D and D ^t Eye and 6th row, 8th row of D and D ^t
It holds for the fourth and fifth columns of. These relationships are shown in FIG.

Further, the common part with D can be found even for odd rows of D ^t . For example, the first of D ^t
If odd-numbered rows are taken out for the column, they become 4096, 5352, 4096, and 2217 as shown in FIG. 4C. Of these, two 4096 are the first row of the first column of D,
Equal to the third row.

As for the odd-numbered row in the second column of D ^t , as shown in FIG. 4C, the third and seventh rows are D
Is the same as the second and fourth rows in the third column. Thus, D ^t
If only the odd rows of are taken out and compared with the elements of D, half of them have commonality.

As is clear from FIGS. 4B and 4C,
The transform matrix D ^t used for the inverse DCT transform is divided into odd-numbered rows and even-numbered rows, and when the number of rows is added to each, the commonality with the transform matrix used for the forward DCT transformation is clear.

Therefore, for the transformation matrix D of the forward DCT transformation, the first row and the third row of each column are formed, and the second row and the fourth row of the column are formed. Of 1
A set of the second line and the third line, a set of the second line and the fourth line, and a set of the first and third lines of even-numbered lines and a set of the second and fourth lines may be set as a combination of input signals. .. Tables 9 to 16 show conversion tables of 2 bits each by such a combination.

[0103]

[Table 9]

[0104]

[Table 10]

[0105]

[Table 11]

[0106]

[Table 12]

[0107]

[Table 13]

[0108]

[Table 14]

[0109]

[Table 15]

[0110]

[Table 16]

In Tables 9 to 16, No. 0 to No. 7 of the forward DCT lookup table correspond to the first to eighth columns of the transformation matrix D. Further, in the inverse DCT lookup table, No. 0 and No. 1 correspond to the first and second odd rows of D ^t , and similarly, No. 2 and No. 3 are the second row of D ^t . Corresponding to the odd and even rows of the eyes, No. 4 and No. 5 are D
Corresponds to the odd and even rows in the third column of ^t , No. 6 and No.
7 corresponds to the odd and even rows of the fourth column of D ^t .

In Tables 9 to 16, No. 0, lines 2 and 4, No. 0.
Lines 1 and 2 of No. 2, Lines 2 and 4 of No. 4, Lines 1 and 3 of No. 6
Only forward lookup table for inverse DCT and inverse DCT
It is a different part in the conversion lookup table for use. Therefore, the number of ROMs may be 2 × 8 + 4 = 20 to construct these look-up tables. Two-dimensional DC
20 × 2 = 40 ROMs to configure the T arithmetic unit
Will be enough.

Incidentally, further observing the contents of the lookup table, half of the portion surrounded by the solid line frame, that is, N of the lookup table for forward DCT
o. 0 and No. 4 and No. 2 and No. 6 of the look-up table for inverse DCT are formed by forming the sum or difference of each input signal of 2 bits and performing a bit shift of 12 bits. can do. That is,
These can be operated without using a look-up table by using an adder / subtractor circuit and a bit shifter.

With such a structure, 20 ROMs are provided.
4 of them can be further omitted, the required ROM
Will be 16. To realize a two-dimensional DCT arithmetic device, 16 × 2 = 32 ROMs are sufficient.

With such a configuration, 20 ROMs
4 of them can be further omitted, the required ROM
Will be 16. To realize a two-dimensional DCT arithmetic device, 16 × 2 = 32 ROMs are sufficient.

FIG. 11 shows a portion of the ROM accumulating unit of the DCT arithmetic unit using the above table. Coefficient ROM 1a,
Reference numeral 1b has a look-up table and uses two types of 2-bit inputs x1, x3, and x2, x4 as input signals. Since the combination of input signals is 4 bits, the content of the coefficient ROM is 16 words.

An adder 7, a bit shift coefficient circuit 8 and a selector 9 are further connected to one coefficient ROM, which is the coefficient ROM 1b in the figure. The circuit formed by the elements 7, 8 and 9 is for forming an output signal from the sum or difference of the input signals when the look-up tables for the forward DCT transform and the inverse DCT transform are different, and for the forward DCT and the inverse DCT. It is omitted when the lookup tables are the same.

Further, although the case where an arithmetic circuit by bit shift is added to the coefficient ROM 1b is shown, depending on the block, this arithmetic circuit is connected to the coefficient ROM 1a side. The selector 9 is for selecting either the output of the coefficient ROM 1b or the output by bit shift.

The output signal of the coefficient ROM 1 a and the output signal of the selector 9 are added by the adder 2 and output via the adder 3. The output signal is fed back to the adder 3 via the coefficient circuit 5 by bit shift.

That is, since the bit positions change sequentially in the subsequent calculation, the positions are aligned to form the cumulative sum. If the input is a sign bit, the signal Ts
The sign is inverted by.

FIG. 12 shows the configuration of a one-dimensional DCT processing system. The input signal is input to the input buffer 11, and is supplied from the input buffer to the parallel / serial conversion circuit 14 via the butterfly circuit 12 or the bypass 13.

In the case of forward DCT, the input signal is supplied from the input buffer 11 to the butterfly circuit 12, and the sum or difference of the two types of input signals, that is, f0 + f7, f1 + f6, f.
2 + f5, f3 + f4, f0-f7, f1-f6, f2
-F5 and f3-f4 are formed. These signals are supplied to the parallel / serial conversion circuit 14, and 2 bits each are output.

In the case of inverse DCT, the output of the input buffer 11 is directly supplied to the parallel / serial conversion circuit 14 via the bypass 13. In the parallel / serial conversion circuit, odd-numbered input signals f0 + f2, f4,
f6 and the even-numbered input signals f1, f3, f5, and f7 are separately stored.

The outputs of the parallel / serial conversion circuit 14 are grouped in groups of four, forming two 8-bit signals. This signal is supplied to the ROM accumulator 10 having a plurality of configurations as shown in FIG. 11, a look-up table is selected according to the calculation position, and an output signal is formed. The output signal of the ROM accumulator 10 is the butterfly circuit 1
6 or is supplied to the output buffer 18 via the bypass 17. In this way, the output signal is supplied from the output buffer 18.

In the forward DCT, the output signal of the ROM accumulator 10 passes through the bypass 17, and in the inverse DCT, the output signal of the ROM accumulator 10 is the butterfly circuit 1.
It is supplied to the output buffer 18 through 6. In this way, the one-dimensional DCT operation is performed.

FIG. 13 shows an equivalent circuit for a two-dimensional DCT operation. In FIG. 13, an input buffer 11, a butterfly circuit 12, a bypass 13, a parallel / serial conversion circuit 14, a ROM accumulator 10a, a butterfly circuit 1
6, the bypass 17, and the output buffer 18 are equivalent to the corresponding parts shown in FIG.

That is, by these elements, one-dimensional D
CT conversion is performed. The transposed ROM 20 converts the one-dimensional DCT-converted signal into rows and columns, and supplies the signals to the input buffer 21. Input buffer 21, butterfly circuit 22, bypass 23, parallel / serial conversion circuit 24, ROM accumulator 10b, butterfly circuit 26,
The bypass 27 and the output buffer 28 are other one-dimensional DCTs.
An arithmetic circuit is configured to execute a second-dimensional DCT operation.
In this way, an output signal subjected to DCT processing in the two-dimensional direction is formed.

The values of the look-up tables shown in Tables 9 to 16 can be halved in capacity by taking the exclusive OR with the most significant bit b2 in the tables. For example, a forward DCT lookup table N
Regarding o.0, by subtracting the average value 12288 from the values in the table, the upper half and the lower half have a symmetrical configuration. With such a configuration, the capacity of the lookup table can be halved.

FIG. 14 shows the structure of a ROM accumulator using such a structure. 4-bit input signal b2, b1, a
2 and a1 are respectively exclusive-ORed with b2 and the remaining three b1, a2, and a1 to be three signals, which are input to the coefficient ROMs 31a and 31b. Coefficient ROM3
1a and 31b receive a 3-bit input signal and have an 8-word structure. The other points are the same as the circuit of FIG.

The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example,
It will be apparent to those skilled in the art that various modifications, improvements, combinations and the like can be made.

[0131]

As described above, according to the present invention,
It is possible to reduce the butterfly circuit of the two-dimensional discrete cosine converter.

It is possible to reduce the chip size and power consumption of the semiconductor device that realizes the discrete cosine converter.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional technique.

FIG. 3 is a schematic diagram illustrating a conventional image data compression technique using DCT.

FIG. 4 is a schematic diagram for explaining a transform matrix of DCT.

FIG. 5 is a block diagram illustrating a configuration of a DCT arithmetic device according to a conventional technique.

FIG. 6 is a block diagram showing a main part of a DCT arithmetic device according to a conventional technique.

FIG. 7 is a block diagram showing a main part of a DCT arithmetic device according to a conventional technique.

FIG. 8 is a table and a block diagram showing a main part of a DCT arithmetic device according to a conventional technique.

FIG. 9 is a block diagram showing a main part of a DCT arithmetic device according to an embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a ROM accumulator of the DCT arithmetic device.

FIG. 11 is a block diagram showing another configuration of the ROM accumulator of the DCT operation device.

FIG. 12 is a block diagram showing a one-dimensional calculation part of a DCT calculation device.

FIG. 13 is a block diagram showing an equivalent circuit of a two-dimensional DCT arithmetic device.

FIG. 14 is a block diagram showing another configuration of the ROM accumulator of the DCT operation device.

[Explanation of symbols]

 1 Look Up Table 2, 3 Adder 4 Register 5 Shifter 6 Accumulator 7 Adder 8 Coefficient Circuit (Shifter) 9 Selector 10 ROM Accumulator 11 Input Buffer 12 Butterfly Circuit 13 Bypass 15 ROM Accumulator 14 Parallel / Serial Conversion Circuit 16 Butterfly Circuit 17 Bypass 18 Output Buffer 20 Transposition RAM 21 Input Buffer 22 Butterfly Circuit 23 Bypass 24 Parallel / Serial Conversion Circuit 26 Butterfly Circuit 27 Bypass 28 Output Buffer 101 Input Buffer 102 Selector 103 Butterfly Circuit 105 1-D DCT 106 Selector 107 Butterfly Circuit 108 Output Buffer 110 transposition circuit 111 input buffer 112 selector 115 one-dimensional DCT 116 selector 117 output buffer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 7/133 Z 4228-5C

Claims (1)

[Claims] 1. A first one-dimensional discrete cosine transform circuit,
A two-dimensional discrete cosine transformer having a transpose circuit and a second one-dimensional discrete cosine transform circuit, wherein the first and second one-dimensional discrete cosine transform circuits are respectively one-dimensional discrete cosine processing circuits (105, 115)
And a pre-processing circuit and a post-processing circuit connected to the input side and the output side thereof, respectively, the pre-processing circuit of the first one-dimensional discrete cosine processing circuit and the second one-dimensional discrete cosine processing circuit The post-processing circuit includes a common first butterfly circuit (103), and the post-processing circuit of the first one-dimensional discrete cosine processing circuit and the pre-processing circuit of the second one-dimensional discrete cosine processing circuit are common. Second butterfly circuit (1
07) Discrete cosine transformer.