JPH05151007A - Crc arithmetic unit - Google Patents

Abstract

PURPOSE:To provide the CRC arithmetic unit enabling the switching of the CRC arithmetic expression from the outside and high-speed calculation. CONSTITUTION:A CRC computing element 4 enables the setting of the generating polynomial and the initial value from the CPU of the terminal. The CRC computing element 4 performs the CRC operation for the data row to be supplied from a shift register 3 for data input based on the set generating polynomial. The arithmetic result of the CRC computing element 4 is outputted to the CPU of the terminal through an output buffer 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CRC calculation device, and more particularly to a device for performing a CRC calculation for detecting an error in an input data string.

[0002]

2. Description of the Related Art CRC (Cyclic Redunda)
ncy Check) is an error detection method often used in the case of synchronous transmission, and is also called a cyclic code method.

In this error detection method, the data string to be sent is regarded as a high-order polynomial (called a message polynomial), which is a predetermined generator polynomial (Checki).
ngPolynomial). The remainder of the division result (BCC: Block Check
Code) is added after the data and transmitted, and the reception side performs division using the same generator polynomial. At this time, if there is no remainder, the transmitted data is judged to be correct.

The following CRC generating polynomials are actually used at present.

(1) CRC-12 CRC-12 is used for synchronous transmission of 6-bit characters. The following equation (1) is used for the generator polynomial, and CR
BCC, which is the result of the C operation, is composed of 12 bits. P (x) = X ¹² + X ¹¹ + X ³ + X ² + X + 1 (1)

(2) CRC-16 CRC-16 is used for synchronous transmission of 8-bit characters, and is often used especially for data transmission of EBCDIC code. The following equation (2) is used for the generator polynomial,
BCC consists of 16 bits. P (x) = X ¹⁶ + X ¹⁵ + X ² +1 (2)

(3) CRC-CCITT CRC-CCITT is also 8 bits as well as CRC-16.
It is used for synchronous transmission of characters and is often used for transmission of ISO codes. The following equation (3) is used as the generator polynomial, and the BCC is composed of 16 bits. P (x) = X ¹⁶ + X ¹² + X ⁵ +1 (3)

The conventional technique for detecting a CRC error by a hard circuit is described in No. 1 of "Transistor Technology SPECIAL" issued by CQ Publishing Company on March 1, 1988.
8, pages 10-11.

[0009]

A conventional CRC calculation device is configured to divide an input data string by only one kind of predetermined generator polynomial. Therefore, when the CRC calculation device provided in the terminal of the other party for communication performs the CRC calculation using different generator polynomials, there is a problem in that the CRC calculation cannot be consistent and data error cannot be detected. there were. Especially, when data communication is performed with a plurality of terminals, such a problem becomes remarkable.

In order to solve the above problems, the computer of the terminal is required to perform CRC by a plurality of types of generator polynomials.
A technique that has a calculation program and executes an arbitrary CRC calculation program according to the user's request is conceivable.
However, with such a technique using software, the load on the computer of the terminal becomes heavy, and the execution processing speed of the program that should be originally executed is significantly reduced. Also, the CRC calculation by the computer is
There is also a problem that it is not suitable for high-speed communication because the calculation speed is slower than the CRC calculation by the dedicated hardware circuit.

Therefore, an object of the present invention is to provide a CRC arithmetic unit capable of freely changing a generator polynomial and capable of high speed arithmetic.

[0012]

CRC according to the present invention
The arithmetic unit includes shift register means, CRC arithmetic means, and switching control means. The shift register means includes N (N is an integer of 2 or more) latch circuits, and each performs a shift operation in synchronization with the same clock signal. The CRC calculation means includes N logic calculation means alternately arranged with each latch circuit, and performs the CRC calculation on the input data string. The switching control means switches between activation and deactivation of the logical operation function of each logical operation means based on the input generator polynomial setting data.

[0013]

In the CRC calculation device according to the present invention,
Based on the input generator polynomial setting data, the switching control means switches between activation and deactivation of the logical operation function of each logical operation means, thereby switching the generator polynomial for the CRC operation. Therefore, C of this invention
The RC arithmetic unit can change the arithmetic expression from the outside.
CRC calculation can be performed while always maintaining consistency with the communication partner. The CRC calculation device of the present invention is a CR
Since it is configured as a dedicated hardware circuit for performing C calculation, high speed calculation is possible.

[0014]

1 is a schematic block diagram showing the structure of an embodiment of the present invention. In the figure, the CRC of this embodiment
The arithmetic unit is provided inside a modem connected to, for example, a terminal body (hereinafter abbreviated as “terminal”), and has an initial value input register 1, a generator polynomial setting register 2, and a data input register 3. , CRC calculator 4, an output buffer 5, and a clock control circuit 6. To the initial value input register 1, a CPU (not shown) included in the terminal gives an initial value of, for example, 16 bits divided into 8 bits via an 8-bit data bus 7. The initial value stored in the initial value input register 1 is the CRC calculator 4
Is given to and set. To the generator polynomial setting register 2, for example, 16-bit generator polynomial setting data is divided by 8 bits from the CPU of the terminal and given via the data bus 7. The generator polynomial setting data stored in the generator polynomial setting register 2 is given to the CRC calculator 4 and set. For example, the 8-bit data input shift register 3 is provided with a data string to be subjected to CRC calculation from the CPU of the terminal. This data string is transmission data to be transmitted to another terminal or reception data received from another terminal. The data string stored in the data input shift register 3 is sequentially read in synchronization with the clock signal CLK and is given to the CRC calculator 4. CRC
The arithmetic unit 4 performs CRC calculation on the data string given from the data input shift register 3. At this time, C
The RC calculator 4 performs a CRC calculation based on the generator polynomial set by the generator polynomial setting register 2. CR
The output (16 bits) of the C arithmetic unit 4 is given to the output buffer 5. The output buffer 5 divides the 16-bit operation result given from the CRC calculator 4 into 8 bits and outputs the result to the data bus 7. The calculation result output to the data bus 7 is given to the CPU of the terminal. The clock control circuit 6 includes a clock oscillator and has a number of clock signals (C
LK), and the number of clock signals corresponding to the number of shifts is given to the CRC calculator 4.

FIG. 2 is a circuit diagram showing a more detailed structure of the CRC calculator shown in FIG. 1, and particularly shows the structure of the CRC calculator 4 in detail.

In FIG. 2, the CRC calculator 4 includes D-type flip-flops 41a to 41p, exclusive OR gates 42a to 42p, and switch circuits 43b to 43q. Each of the D-type flip-flops 41a to 41p includes a data terminal D, an output terminal Q, a preset terminal PRS, a reset terminal RST, and a clock terminal C.

The signals output from the output terminals Q of the D-type flip-flops 41a to 41p are applied to the exclusive OR gates 42a to 42p and the output buffer 5, respectively. Exclusive OR gates 42b-4
The output signals of 2p are the D-type flip-flops 4 respectively.
It is given to the data terminals D of 1a to 41o. The output signal of the exclusive OR gate 42a is output by the switch circuits 43b to 4b.
It is given to the exclusive OR gates 42b to 42p via 3p. Here, the switch circuits 43a to 43p are shown by mechanical switch symbols for simplification in the drawing, but actually, logical switches such as AND gates or logical gates are used. Further, the output signal of the exclusive OR gate 42a is given to the data terminal D of the D-type flip-flop 41p via the switch circuit 43q. Switching of the switch circuits 43b to 43q is controlled based on the logical state of the corresponding bit position of the generator polynomial setting data given from the generator polynomial setting register 2. Each switch 43
b to 43q, when turned on, output signals of the exclusive OR gate 42a to exclusive OR gates 42b to 42p.
And to the D-type flip-flop 41p. on the other hand,
When the switch circuits 43b to 43q are turned off,
Exclusive-OR gates 42b to 42 connected to the ground terminal
An L level signal is applied to p and D type flip-flop 41p. The exclusive OR gate 42a is further supplied with a data string to be subjected to a CRC operation from the data input shift register 3.

The preset terminal PRS and the reset terminal RST of each D-type flip-flop 41a to 41p are
An initial value setting signal is given from the initial value input register 1. When the initial value setting signal given to the preset terminal PRS is at H level and the initial value setting signal given to the reset terminal RST is at L level, the initial value of the output signal of the output terminal Q of the D-type flip-flop is at H level. Becomes
On the other hand, when the initial value setting signal given to the preset terminal PRS is L level and the initial value setting signal given to the reset terminal RST is H level, the initial value of the output signal of the output terminal Q of the D-type flip-flop is L level. Become. Further, the clock signal CLK is applied to the clock terminal C of each of the D-type flip-flops 41a to 41p. Each of the D-type flip-flops 41a to 41p performs a data shift operation in synchronization with this clock signal CLK. Therefore, by the D-type flip-flops 41a to 41p,
A so-called shift register is configured.

FIG. 3 is a schematic diagram for explaining a CRC error detection method realized by the embodiments shown in FIGS. 1 and 2. In the figure, in the terminal on the transmission side, for example, 256 bytes of transmission data (1 byte is made up of, for example, 8 bits) is subjected to a CRC operation to generate, for example, 16 bits of CRC data. The terminal on the transmitting side transmits the original transmission data and the CRC data generated by the CRC calculation to the terminal on the receiving side. The receiving side terminal performs a CRC operation on the received data of 256 bytes and the CRC data of 16 bits. As a result, 16-bit CRC data is generated. The terminal on the receiving side checks whether or not the CRC data generated at this time matches the initial value setting data preset in the CRC calculation device shown in FIG. 1 and FIG. As a result of the check, if the CRC data and the initial value setting data match, it is determined that there is no data error, and if they do not match, it is determined that there is a data error.

FIG. 4 is a flow chart showing the operation of the embodiment shown in FIGS. The operation of the embodiment shown in FIGS. 1 and 2 will be described below with reference to FIG.
First, in step S1, the generator polynomial setting data is given to the generator polynomial setting register 2 from the CPU of the terminal. The generator polynomial setting data is 16 bits, but the bit width of the data bus connecting the CPU of the terminal and the CRC arithmetic unit is 8 bits. Therefore, the CPU of the terminal outputs the generator polynomial setting data to the generator polynomial setting register 2 by dividing it into 8 bits each twice. The generator polynomial setting data stored in the generator polynomial setting register 2 is given to the CRC calculator 4. Thus, the CRC calculator 4 sets the generator polynomial. More specifically, the switch circuit 43b in the CRC calculator 4
.About.43q are individually turned on or off. The switch circuit turned on has the exclusive OR gate 42.
The output signal of a is converted into a corresponding exclusive OR gate or D
Feedback to the type flip-flop 41p. The switch circuit in the off state transmits an L level signal to the corresponding exclusive OR gate or D-type flip-flop 41p. Each exclusive OR gate 42b to 42p
When the output signal of the exclusive OR gate 42a is fed back via the corresponding switch circuits 43b to 43p, the logical operation (exclusive operation) between this feedback signal and the output signal of the corresponding D-type flip-flops 41b to 41p is performed. OR operation). On the other hand, the exclusive OR gates 42b to 42p have corresponding switch circuits 43b to 43, respectively.
When an L level signal is given through p, the above-mentioned logical operation is not performed and the corresponding flip-flop 41
The output signals b to 41p are output as they are. That is,
At this time, the exclusive OR gates 42b to 42p operate merely as drivers and are in a data through state. For reference, the relationship between the switch circuits 43b to 43q and the generator polynomial is shown in FIG. In FIG. 5, the output signal of the exclusive OR gate 42a corresponds to the coefficient a of the generator polynomial P (x) of the following expression (4), and the switch circuit 43b
The on / off states of ~ 43q correspond to the coefficients b ~ q of the generator polynomial P (x) of the following expression (4). Specifically, when the switch circuits 43b to 43q are on, the coefficients b to q are 1, and when the switch circuits 43b to 43q are off, the coefficients b to q are 0 (that is, the X
Is zero). P (x) = aX ¹⁶ + bX ¹⁵ + cX ¹⁴ ... oX ² + pX + q (4)

Next, in step S2, the CP of the terminal
Initial value setting data is supplied from U to the initial value input register 1. Since the initial value setting data is 16 bits,
Similar to the above-mentioned generator polynomial setting data, 8 bits each
It is given in divided times. The 16-bit initial value setting data stored in the initial value input register 1 is converted into two initial value setting signals each having complementary bits, and is supplied to each D-type flip-flop 41a to 41p. For example, when the logic of a bit of the initial value setting data is "1", the preset terminal P of the corresponding D-type flip-flop is
The RS is supplied with an H-level initial value setting signal, and the reset terminal RST is supplied with an L-level initial value setting signal. On the other hand, when the logic of a bit of the initial value setting data is "0", the L-level initial value setting signal is given to the preset terminal PRS of the corresponding D flip-flop, and the H-level initial value is given to the reset terminal RST. A value setting signal is given. For a D-type flip-flop, when an H-level initial value setting signal is applied to the preset terminal PRS and an L-level initial value setting signal is applied to the reset terminal RST, the initial value of the output signal of the D-type flip-flop. Becomes H level. On the other hand, regarding a certain D-type flip-flop, when an L-level initial value setting signal is applied to the preset terminal PRS and an L-level initial value setting signal is applied to the reset terminal RST, the output signal of the D-type flip-flop is changed. The initial value is L level.

Next, in step S3, the CP of the terminal
Data to be subjected to the CRC calculation is given from the U to the data input shift register 3 by 1 byte, that is, by 8 bits. The data stored in the data input shift register 3 is serially output bit by bit in synchronization with the clock signal CLK and is given to the exclusive OR gate 42a. As a result, the CRC calculator 4 shifts by 1 bit each time a shift signal is given from the shift control circuit 6, and corresponds to the product of the number of bytes of input data transmitted from the CPU and the number of bits of 1 byte. CRC of the input data string
Calculation is performed. 256 bytes of data are sequentially applied from the CPU of the terminal to the data input shift register 3, and these data are calculated by the CRC calculator 4.

Next, in step S4, the calculation result of the CRC calculator 4 is read from the output terminal Q of each D-type flip-flop, and is output via the output buffer 5 to the CP of the terminal.
Output to U. At this time, the output buffer 5 divides the 16-bit CRC calculation result data into two by 8 bits, and outputs each divided data in a time division manner.

FIG. 6 is an equivalent circuit diagram showing the configuration of the CRC calculator 4 in the case where the CRC-CCITT generator polynomial is set in the embodiment shown in FIGS. 1 and 2. In the figure, in this case, the switch circuits 43e, 43l and 43q are turned on and the other switch circuits are turned off. Therefore, only the exclusive OR gates 42a, 42e and 42l perform the logical operation, and the other exclusive OR gates are in the data through state. Therefore, D
The type flip-flops 41a to 41d form a 4-bit shift register between the exclusive OR gates 42a and 42e, and the D-type flip-flops 41e to 41k are connected between the exclusive OR gates 42e and 42l. A bit shift register, and D-type flip-flops 41l to 4l
1p constitutes a 5-bit shift register between the exclusive OR gates 42l and 42a.

FIG. 7 shows C in the case where the CRC-16 generator polynomial is set in the embodiment shown in FIGS.
6 is an equivalent circuit diagram showing the configuration of an RC calculator 4. FIG. In this figure, in this case, only the exclusive OR gates 42a, 42b and 42o perform the logical operation, and the other exclusive OR gates are in the data through state. Therefore, the D-type flip-flop 41a is connected to the exclusive OR gates 42a and 4a.
2b constitutes a 1-bit shift register, D-type flip-flops 41b to 41n constitute a 13-bit shift register between exclusive OR gates 42b and 42o, and D-type flip-flops 41o and 41p. Constitutes a 2-bit shift register between the exclusive OR gates 42o and 42a.

FIGS. 6 and 7 are merely examples, and it is of course possible to recompose the configuration of the CRC calculator 4 into another generator polynomial.

In the above embodiment, the CRC calculator 4 has a 16-bit configuration, but this is merely an example, and the number of bits is not limited to 16 bits.

[0028]

As described above, according to the present invention, the CR
The calculation function of the C calculation device can be arbitrarily changed from the outside. As a result, the consistency with the other party's terminal with which communication is performed is improved, and a data error can be reliably detected even when performing data communication with a plurality of terminals. Further, according to the present invention, CR is performed by using a dedicated hardware circuit.
Since the C operation is performed, the operation speed is higher than that in the case where the computer of the terminal performs the CRC operation by software based on the program, which is suitable for high-speed communication.

Further, according to the present invention, even if a new generator polynomial is adopted, the setting can be easily changed and the calculation can be performed.
If the generator polynomial is used as a kind of password, a user who does not know the generator polynomial cannot perform data communication, and the confidentiality of communication can be secured. More specifically, normally, when an error occurs in the CRC calculation result, a retransmission request is sent to the other party (transmission side), but normal CRC data using a new generator polynomial and erroneous CRC data are used. When data and are sent, the sending side checks whether or not there is a resend request, and determines whether the receiving side modem is using the newly determined generator polynomial. You can identify whether or not.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing the configuration of a CRC calculation device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a more detailed configuration of the CRC calculation device shown in FIG.

FIG. 3 is a schematic diagram for explaining a CRC data error detection method implemented in the embodiments shown in FIGS. 1 and 2.

FIG. 4 is a flowchart for explaining the operation of the embodiment shown in FIGS. 1 and 2.

5 is a schematic diagram showing a relationship between each switch circuit and a generator polynomial in the CRC calculator shown in FIG.

FIG. 6 shows a CRC in the embodiment shown in FIGS. 1 and 2.
-C when the generator polynomial of CCITT is set
It is an equivalent circuit diagram which shows the structure of RC arithmetic unit.

FIG. 7 shows a CRC in the embodiment shown in FIGS. 1 and 2.
It is an equivalent circuit diagram which shows the structure of a CRC calculator in case the generator polynomial of -16 is set.

[Explanation of symbols]

 1: Initial value input register 2: Generator polynomial setting register 3: Data input shift register 4: CRC calculator 5: Output buffer 6: Clock control circuit 41a to 41p: D-type flip-flop 42a to 42p: Exclusive OR gate 43b to 43q: switch circuit

Claims (2)

[Claims] 1. C for detecting an error in an input data string
An apparatus for performing RC operation, comprising N (N is an integer of 2 or more) latch circuits, each of which performs shift operation in synchronization with the same clock signal, and shift register means alternately with each of the latch circuits. CRC operation means including the arranged N logic operation means for performing a CRC operation on an input data string, and a logic operation function of each of the logic operation means based on the input generator polynomial setting data. A CRC arithmetic unit comprising switching control means for switching between activation and deactivation. 2. The switching means comprises a generator polynomial storage register including a plurality of bit cells for storing and retaining the input generator polynomial setting data, and a CRC operation based on the bit cell retention data contained in the generator polynomial storage register. 2. The CRC arithmetic unit according to claim 1, further comprising a logic switch circuit connected so as to provide an output of the circuit to the logical operation circuit corresponding to each bit cell.