JPH05145762A - Still picture receiving equipment - Google Patents

Abstract

PURPOSE:To execute a PinP display by constituting a reduced screen from still picture data encoded by a DCT. CONSTITUTION:When a PinP flag is turned on, and DCT code still picture data stored in a buffer memory 12 is read out and decoded by an IDCT circuit 18, the IDCT circuit 18 decodes only low frequency blocks of 2X2 containing a DC component among 8X8 blocks by a switching signal from a control circuit 16. As a result, reduced screen image data which does not contain a high frequency component, that is, is equivalent to that which is processed by a low-pass filter is obtained. In such a way, the low-pass filter and a line memory, etc., become unnecessary, and the inexpensive circuit configuration is simplified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a still image receiving device, and more particularly to, for example, Discrete Cosine Trans.
formation: Hereinafter referred to as "DCT". ) Receives a still image that is compression-coded or hierarchically-coded by) and receives the inverse discrete cosine transform (Inversed Discrete Cosine Transformation:
Hereinafter referred to as "IDCT". ) To obtain the image data for display, the present invention relates to a still image receiving device.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 10, a DCT has been used which expands an image signal having N × N pixels as one block into N × N two-dimensional frequency components. Or, the hierarchically encoded still image is reduced and displayed on the screen of the display device as a sub screen or a multi screen in Picture in Picture (hereinafter sometimes referred to as “PinP”). The technology is known. For example, see "Digital Circuit of TV Signal" (Achiha, Eto: Corona Publishing Co.) or "Latest AV Equipment and Digital Technology" (Mari Fujio Custom: Corona Publishing Co.).

[0003]

The former method is shown in FIG. The still image receiving apparatus 1 of the prior art in FIG. 11 adopts the image generation method of the sequential build-up method, but in order to obtain a PinP child screen image with this still image receiving apparatus 1, A two-dimensional low pass filter 2a and line memory 3a are required. This is to prevent aliasing noise. That is, since the horizontal data thinning process and the vertical scanning line thinning process are performed for the reduced screen, the sampling frequency is lowered both horizontally and vertically, and the high frequency components must be limited. The lower sideband of the sampling frequency folds back into the baseband signal. Therefore, it is necessary to perform a two-dimensional low-pass filter process adapted to the thinning degree (screen reduction degree) of data and scanning lines both horizontally and vertically, which also requires a memory capacity for several lines.

The latter conventional technique is shown in FIG. In the still image receiving device 4 shown in FIG. 12, the input still image data is controlled by the PinP dedicated control LSI 5,
The reduced PinP child screen data is written in the memory 6a. Then, by the read control signal synchronized with the parent screen signal, the memory 6a passes through the PinP dedicated control LSI 5
PinP child screen data is output. However, when the PinP dedicated control LSI 5 is not used, the data thinning process (screen reduction process) executed by controlling the writing to the memory 6b is performed as in the still image receiving device 7 shown in FIG. The above-mentioned folding noise is generated, and the same two-dimensional low-pass filter 2b and line memory 3b are required to prevent it.

Further, also in the still image receiving apparatus 8 shown in FIG. 14 which creates a multi-screen from hierarchically encoded still image data, the two-dimensional low-pass filter 2c and line memory 3c for suppressing aliasing noise are required. there were. In addition, progressive build-up method
Of the image generation methods of Spectral-Sel (Spectral-Sel
section), the generated image containing only low-frequency components is the same as when the low-pass filter processing is applied to the original image, and aliasing noise occurs even if the sampling frequency is reduced for reduced display. do not do. However, the band of the low-frequency component to be decoded and the sampling frequency must satisfy Nyquist's theorem. Moreover, in order to adopt this spectrum selection method for the purpose of obtaining a PinP sub-screen image, a complicated algorithm is required on both the transmitting side and the receiving side, and it is necessary to increase the circuit scale of memory etc. accordingly. ..

That is, in any of the conventional techniques,
A complicated algorithm, a dedicated control LSI, or a two-dimensional low-pass filter and a line memory therefor are required, which increases the circuit scale and cost. Therefore, a main object of the present invention is to provide a still image receiving apparatus capable of reducing and displaying a DCT-coded still image with a simple structure and without aliasing noise.

[0007]

A first aspect of the present invention is a still image receiving apparatus for receiving compression-coded still image data encoded by discrete cosine transform and displaying the still image on a display device. A memory for storing the compressed and encoded still image data, and a decoding means for decoding the compressed and encoded still image data read from the memory and outputting the image data, wherein the still image is reduced and displayed on the screen of the display device. When the instruction signal is on, the decoding means further includes an instruction signal input means for inputting an instruction signal to be turned on when it should be, and the decoding means decodes only the low frequency block of the compression-coded still image data and outputs reduced image data. The still image receiving device is characterized in that.

A second invention is a still image receiving apparatus for receiving hierarchically encoded hierarchically encoded still image data and displaying a still image on a display device, wherein the received hierarchically encoded still image data is An instruction that is turned on when a still image is to be reduced and displayed on the screen of the display device in a memory having a store and a decoding unit that decodes hierarchically encoded still image data read from the memory and outputs image data An instruction signal input means for inputting a signal is further provided, and when the instruction signal is turned on, the decoding means decodes the hierarchically encoded still image data up to a specific layer according to the reduced size and outputs the reduced image data. It is a still image receiving device characterized by the above.

[0009]

According to the first aspect of the present invention, when the instruction signal is on, when decoding the still image data compression-coded by the DCT by the decoding means, only the low-frequency block is decoded, so that the original image is It is possible to obtain a reduced image similar to that obtained by low-pass filter processing. That is, by utilizing the property that still image data encoded by DCT is developed into two-dimensional frequency components, if only the low frequency block in the DCT data is decoded, the decoded data will be data with high frequency components cut off. , That is, the same data as that which has been low-pass filtered.

In the second invention, when the instruction signal is on,
Only the hierarchically higher still image data stored in the memory is decoded by the decoding means. For example, the first
~ When there is a fourth layer, only the first and second layers are decoded. This makes it possible to obtain a reduced image similar to that obtained by low-pass filtering the original image. That is, if the decoding is limited in a certain layer, image data having a block in that layer as the minimum pixel can be obtained. For example, if the target block consists of 4 × 4 pixels,
The maximum frequency is 1/4 of the original image both horizontally and vertically, and the same effect as when the low-pass filter processing is performed is obtained. Therefore, even if the sampling frequency is reduced to 1/4 in order to reduce the obtained still image data horizontally and vertically to 1/4, that is, 1/16, the frequency component is 1 /
Since it is 4, it satisfies the Nyquist theorem,
No aliasing noise occurs.

[0011]

According to the present invention, a complicated algorithm, a dedicated control LSI, a two-dimensional low-pass filter, a line memory, or the like is required to create a reduced image from coded still image data encoded by DCT, for example. Therefore, the circuit configuration is simple and inexpensive.

The above-mentioned objects, other objects, features and advantages of the present invention will become more apparent from the detailed description of the embodiments below with reference to the drawings.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a still image receiving apparatus 10 of this embodiment has a plurality of (five in this embodiment) code still images subjected to DCT of 8 × 8 as shown in FIG. It includes a buffer memory 12 in which data is stored. Where DC
The T and IDCT will be briefly described.

When the original image signal is f (j, k) and the DCT component is F (u, v), F (u, v) is expressed by equation 1.

[0015]

[Equation 1]

However, C (w) = 2 ^−1/2 for w = 0 and C (w) = 1 for w = 1, 2, ..., N−1. Also, I
The DCT is expressed as in Equation 2.

[0017]

[Equation 2]

However, C (w) = 2 ^−1/2 for w = 0 and C (w) = 1 for w = 1, 2, ..., N−1. here,
F (0,0) represents the DC component of the pixel in the block, and F (u,
v) (u, v ≠ 0) represents the AC component of the image. However,
u represents a frequency component in the horizontal direction, and v represents a frequency component in the vertical direction. In general, the energy of the image signal is concentrated in the low frequency component, so that the data amount can be compressed by encoding the DCT coefficient of the low frequency component with many bits and the high frequency component with few bits. ..

The coded still image data compression-coded by the DCT is input to the still image data input terminal 14 and stored in the area indicated by each address of the buffer memory 12. Then, the address of the coded still image data to be decoded is selected by an address selection signal from the control circuit 16 such as a microcomputer, and the coded still image data stored in the area indicated by the address is sent to the IDCT circuit 18. , Will be decrypted. For example, a PinP flag that is turned on or off in response to turning on or off of a PinP switch (not shown) is input. The control circuit 16 receives this PinP flag on / off signal, and based on this, whether the IDCT circuit 18 should be restricted from decoding, that is, whether to decode all blocks or only low-frequency blocks. Is sent.

That is, when the PinP flag is on, the control circuit 16 gives the above-mentioned switching signal to the IDCT circuit 18 so as to limit the decoding to only 2 × 2 blocks. In response, the IDCT circuit 18 performs decoding on the low-frequency 2 × 2 block including the DC component shown in FIG. As a result, the frequency band of the decoded still image data is 1/4 of the original coded still image data both horizontally and vertically.
Then, as shown in FIG. 3, the 8 × 8 data block is converted into a 2 × 2 data block.

The decoded still image data decoded by the IDCT circuit 18 is written in the frame memory 20. At this time, according to the write control signal from the control circuit 16, as shown in FIG. 4, writing is performed once every four pixels in the horizontal direction and once every four lines in the vertical direction to obtain the original code still image data. Decoded still image data (180 × 12) for PinP sub-screen image that is (1720 × 480 pixels) reduced to 1/16
0 pixel) is stored in the frame memory 20.

When this still image data is displayed on the PinP sub-screen, the sync signal is detected by the sync signal detection circuit 24 from the PinP main screen image signal input to the video input terminal 22, and the sync signal is input to the control circuit 16. In the control circuit 16, a read control signal is sent to the frame memory 20 based on the input synchronizing signal, and in response, still image data for PinP child screen display is read from the frame memory 20. Then, it is input to the switch circuit 28 via the digital / analog conversion circuit 26. Switch circuit 28
In the control circuit 16, a parent screen / child screen switching signal based on a synchronization signal which is also synchronized with the PinP parent screen image signal is input from the control circuit 16.
PinP display output is obtained.

On the other hand, when the PinP flag is off, the IDCT circuit 1 is activated by the switching signal from the control circuit 16.
At 8, all 8 × 8 blocks of the coded still image data selected by the address selection signal from the buffer memory 12 are decoded, and all data for one frame is written to the frame memory 20. Then, the switch circuit 28 is fixed to the still image side, and by outputting the still image data written in the frame memory 20, an output for displaying the still image on the full screen can be obtained.

When a still image is displayed on the child screen and the child screen is desired to be displayed as the parent screen, Pi
The nP flag may be turned off, the coded still image data may be read again from the buffer memory 12, and all blocks may be decoded. Next, referring to FIG. 5, a still image receiving apparatus 30 of another embodiment has a plurality of (five in this embodiment) codes hierarchically encoded up to the fourth layer as shown in FIG. It includes a buffer memory 32 for storing still image data. The coded still image data is hierarchically coded by DCT as shown in FIG. Hierarchical coding is performed by first dividing one screen into several blocks as shown in "Journal of the Institute of Electronics and Communication Engineers," vol. Use as hierarchical data. If the difference between the data of the first layer and the data of the original image is large enough to be ignored in a certain block, the block is further divided into blocks and the difference value from the first layer is used as the data of the second layer. Then, the same process is performed for the lower layers corresponding to the original image, such as the third, fourth ... Layers. That is, in the hierarchical coding of this embodiment shown in FIG. 6, the first layer divides a region of 16 × 16 pixels into 2 × 2 blocks, and averages 8 × 8 pixels in each block. 2 × 2 DCT is performed using the values.
Similarly, in the second layer, the area of 8 × 8 pixels is 2 × 2.
Is divided into blocks and subjected to DCT. In the third layer, an area of 4 × 4 pixels is divided into 2 × 2 blocks and DCT is performed. And the final fourth layer is 2
1 × 1 DCT is applied to the region of × 2 pixels.

Such hierarchically encoded still image data is input to the still image input terminal 34 and stored in the area indicated by each address of the buffer memory 32. Then, the address of the coded still image data to be decoded is selected by the address selection signal from the control circuit 36 such as a microcomputer, and the coded still image data stored in the area indicated by the address is transferred from the buffer memory 32 to the IDCT circuit 38. Given to and decrypted. At this time, the control circuit 36 sends to the buffer memory 32 a read control signal for switching how to read the coded still image data from the buffer memory 32 according to the ON / OFF state of the PinP flag.

That is, when the PinP flag is on, the read control signal inhibits the read of the coded still image data from the buffer memory 32 in the third and fourth layers, and the first
And only the second layer is input to the IDCT circuit 38.
Therefore, the IDCT circuit 38 decodes only the first and second layers. The decoded still image data from the IDCT circuit 32 is written in the frame memory 40. At this time, the control circuit 36 sends a write control signal to the frame memory 40, and as shown in FIG. 7, writing is performed once every four pixels in the horizontal direction and once every four lines in the vertical direction. As a result, the original still image data (720 x 48
The PinP child screen still image data (180 × 120 pixels) obtained by reducing 0 pixel) to 1/16 is stored in the frame memory 40.

When the still image data stored in the frame memory 40 is displayed on the PinP child screen, the video input terminal 42
The sync signal is detected by the sync signal detection circuit 44 from the PinP main screen image signal input from the input signal to the control circuit 36, and a read control signal for reading the PinP child screen still image data from the frame memory 40 is created. It This is sent to the frame memory 40, and the PinP child screen still image data is read from the frame memory 40 in synchronization with the PinP parent screen image signal. Then, the PinP child screen still image signal is input to the switch circuit 48 through the digital / analog converter 46. Then, an output switching control signal, which is also generated based on the synchronizing signal from the synchronizing signal detecting circuit 44, is given from the control circuit 36 to the switch circuit 48, and the still image is displayed on the parent screen as a PinP child screen display from the switch circuit 48. Image output is obtained.

In this embodiment, the child screen reduced to 1/16 has been described. However, if only the first layer is decoded, a 1/64 child screen is obtained, and the first to third layers are decoded. By doing so, it is possible to create a 1/4 child screen, and it is possible to arbitrarily set up to which layer decoding is required. On the other hand, when the PinP flag is off, the buffer memory 32
From, all the data of the 1st to 4th layers are read,
Be decrypted. Therefore, the data of all layers is written in the frame memory 40 by the IDCT circuit 38 for all the data of one frame. Then, by fixing the switch circuit 48 to the still image side and outputting the image, an image output for displaying the still image on the full screen is output.

When a still image is displayed on the child screen and the child screen is desired to be displayed as the parent screen, Pi
The nP flag may be turned off, the still image data may be read again from the buffer memory 32, and the first to fourth layers may be decoded. Next, with reference to FIG. 8, a still image receiving device 50 according to still another embodiment has a plurality of hierarchically encoded layers up to the fourth layer (as in the case of the embodiment shown in FIG. 5). It includes a buffer memory 52 for storing 16 coded still image data in the embodiment. Each code still image data is input from the still image input terminal 54, and is stored in the buffer memory 52.
Are stored in the area indicated by each address. For example, a multi-screen flag that is turned on or off in response to turning on or off of a multi-screen display switch (not shown) is input. Then, the control circuit 56 such as a microcomputer controls the reading of the coded still image data read from the buffer memory 52 according to the ON / OFF of the multi-screen flag.

That is, when the multi-screen flag is on, the control circuit 56 receives the address selection signal and
First, an address indicating the area where the first code still image data is stored is selected. At this time, due to the reduced display, reading of the third and fourth layers is prohibited by the read control signal, and only the first and second layers are read by the IDCT circuit 5.
8 and is decoded. The decoded still image data is written in the frame memory 60. At this time, as in the embodiment shown in FIG. 5, the control circuit 56 performs write control as shown in FIG. 7 so as to write once every four pixels in the horizontal direction and once every four lines in the vertical direction. The signal is sent to the frame memory 60. As a result, the still image data (180 × 120 pixels) obtained by reducing the original still image data (720 × 480 pixels) to 1/16 is stored in the frame memory 60. Further, the control circuit 56 sends an address control signal to the frame memory 60 to control the reduced still image data to be written in the position (1) shown in FIG. 9 in the frame memory 60. As a result, one still image data forming a multi-screen is created in the frame memory 60.

Thereafter, similar processing is performed on the second, third, ..., Sixteenth code still image data, and the frame memory 6
By writing at the positions (2), (3), ..., (16) shown in FIG.
The still image data for multi-screen is completed. Then, the still image data in the frame memory 60 is output as a 16-screen multi-screen output through the digital / analog converter 62.

In the embodiment of FIG. 8, if the decoding layer is limited to the first layer and the control signal from the control circuit 56 is changed, 64-screen multi-screen display is possible. Also, if the first to third layers are decoded, four-screen multi-screen display is possible. On the other hand, when the multi-screen flag is off, the coded still image data to be decoded is selected by the address selection signal, and the data of the first to fourth layers is IDCT.
It is sent to the circuit 58. Then, all layers are decoded in the IDCT circuit 58 and written in the frame memory 60. A full-screen output for displaying the selected still image on the full screen is output by digital-to-analog converting this still image data and then outputting it.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a DCT input to the still image receiving apparatus shown in FIG.
It is an illustration figure which shows data.

FIG. 3 is an illustrative view showing a change in a state of still image data in the still image receiving apparatus shown in FIG.

4 is an illustrative view showing a change in a state of still image data when the still image data is written in the frame memory shown in FIG. 1. FIG.

FIG. 5 is a block diagram showing another embodiment of the present invention.

6 is an illustrative view showing a state of data of each layer of coded still image data input to the still image receiving device shown in FIG.

FIG. 7 is an illustrative view showing a change in the state of still image data when the still image data is written in the frame memory shown in FIG.

FIG. 8 is a block diagram showing still another embodiment of the present invention.

9 is an illustrative view showing a state in which still image data for multi-screen is created in the frame memory shown in FIG.

FIG. 10 is an illustrative view showing a state where DCT is applied to a still image.

FIG. 11 is a block diagram showing a conventional technique.

FIG. 12 is a block diagram showing a conventional technique.

FIG. 13 is a block diagram showing a conventional technique.

FIG. 14 is a block diagram showing a conventional technique.

[Explanation of symbols]

 10, 30, 50 ... Still image receiving device 12, 32, 52 ... Buffer memory 16, 36, 56 ... Control circuit 18, 38, 58 ... IDCT circuit 20, 40, 60 ... Frame memory

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 7/08 B 9070-5C 7/133 Z 4228-5C

Claims (4)

[Claims] 1. A still image receiving apparatus for receiving compression encoded still image data encoded by discrete cosine transform and displaying the still image on a display device, wherein the received compression encoded still image data is stored. memory,
And a decoding means for decoding the compression-coded still image data read from the memory and outputting the image data, wherein an instruction signal that turns on when the still image is to be reduced and displayed on the screen of the display device is provided. An instruction signal input means for inputting is further provided, and when the instruction signal is on, the decoding means decodes only the low frequency block of the compression-coded still image data and outputs reduced image data. The still image receiver. 2. When the instruction signal is turned off, the decoding means reads the corresponding compression-coded still image data from the memory, decodes all the blocks, and outputs full-screen image data. Claim 1 characterized by the above-mentioned.
The still image receiving device described. 3. A still image receiving device for receiving hierarchically encoded hierarchically encoded still image data and displaying a still image on a display device, wherein the memory stores the received hierarchically encoded still image data.
And a decoding means for decoding the hierarchically encoded still image data read from the memory and outputting the image data, wherein an instruction signal which is turned on when the still image is to be reduced and displayed on the screen of the display device is provided. An instruction signal input means for inputting is further provided, and when the instruction signal is on, the decoding means decodes up to a specific layer according to the reduction size of the layer encoded still image data and outputs reduced image data. A still image receiving device characterized in that 4. When the instruction signal is turned off, the decoding means reads the corresponding layer-coded still image data from the memory, decodes all the layers, and outputs full-screen image data. The still image receiving device according to claim 3, wherein