JPH0514339B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a tracking control device, and more particularly to a tracking control device that cyclically records a plurality of pilot signals with different frequencies on a recording medium for each information recording track, and uses the pilot signals reproduced by a reproducing head. The present invention is applied to an information recording/reproducing apparatus in which a reproducing head is caused to track an information recording track.

This type of information recording/reproducing device is used, for example, as a tracking servo device in a video tape recorder (VTR). In other words, as one of the phase servo systems in the capstan system of a VTR, a plurality of pilot signals with different frequencies are cyclically recorded on a tape for each video track, and when the video signal is played back, the pilot signals of adjacent tracks are played back. A so-called automatic tracking method (ATF method) is used in which a tracking error signal is obtained by detecting the difference between each pilot signal, and tracking servo is performed using this tracking error signal.

This ATF type tracking control device can perform tracking servo using an information recording track and its reproducing head, so it has the advantage of reducing the number of members dedicated to tracking. However, on the other hand, the tracking lock point is limited to each track position, There was an inconvenience that the tracking lock point could not be set at any position between the two.

As a second tracking method to alleviate this inconvenience, a timing signal is recorded on a control dedicated track provided on the tape by a control signal head (CTL head), and the playback timing signal is used as a tracking phase detection signal. A so-called control signal method (CTL method) is used in which tracking servo of the capstan is performed using a difference signal from a reference signal.

In such a tracking control device, when you want to shift the rotating video head from tracking to a predetermined track to another track during dubbing, for example,
It is desirable to be able to shift the tracking lock point by a predetermined amount as necessary, such as when it is desired to shift the tracking when measuring the amount of tracking deviation versus the amount of crosstalk.

Regarding this point, conventionally in the CTL method, the tracking lock point is shifted at an arbitrary phase by delaying an absolutely adjustable reference signal (for example, 30 [Hz]) by a predetermined amount as necessary. It has been made possible. Incidentally, in practice, in order to shift the tracking, the phase of the reference signal is independently shifted by adjusting a tracking control volume (generally referred to as a track convolution volume).

However, in the case of the ATF method, the tracking detection signal is not theoretically compared with an absolutely adjustable reference signal, so a simple method like the CTL method can be used to set the tracking lock point at an arbitrary phase. Until now, no one has been proposed that can shift the tracking by an arbitrarily large amount of phase shift for practical purposes.

The present invention has been made in consideration of the above points, and in the above-mentioned ATF type tracking control device,
The present invention attempts to propose a tracking control device that can stably shift the tracking phase by an arbitrary amount as necessary.

An embodiment in which the present invention is applied to a two-head helical scanning VTR will be described below in detail with reference to the drawings. As shown in FIG. 1, the tracking control device receives a signal S1, a part of the playback output from a video head as a playback head, through a pilot signal detection circuit 1 having a low-pass filter configuration, and records the signal on a magnetic tape as a recording medium. A detection pilot signal S2 having the reproduced output of the pilot signal as a component is generated, and this detection pilot signal S2 is used as the first and second signal.
is applied to the error signal forming circuits 2 and 3. The first and second error signal forming circuits 2 and 3 provide the error signals S31 and S32 formed under the control of the control signal of the lock point control circuit 4 to the error phase calculation circuit 5, and track them at the output terminal thereof. An error signal S4 is sent out.

The first and second error signal forming circuits 2 and 3 have the same configuration as shown by assigning the same reference numerals to corresponding parts, and in principle, as described below.
It is configured as shown in Figure 2 to operate ATF. That is, as shown in FIG. 3, a plurality of types of pilot signals f ₁ , f ₂ , f ₃ , f ₄ having different frequencies are recorded on the tape 11.
A set of video tracks T1, T2, T3, T4 extend diagonally and closely in a circularly repeating manner. Here, the effective width of the video head constituting the playback head 12 is selected to be approximately equal to the width of the tracks T1 to T4.
When 2 is correctly tracking the track currently being scanned for playback (this is called the playback track), by playing back only the pilot signal recorded on that track, the number of pilot frequency components included in the playback output is reduced to one type. On the other hand, when the reproduction head 12 is shifted to the right or left with respect to the relevant track, the reproduction is performed by also reproducing the pilot signal recorded on the track adjacent to the right or left side of the relevant reproduction track. Two types of pilot frequency components are included in the output.

However, the frequencies f ₁ to _{f 4} of the four types of pilot signals f ₁ to f ₄ are selected as the lower band of the color component converted to a low frequency (600 to 700 [kHz]), and the four tracks T1 circulate. ~T4, for example, centering around the odd-numbered tracks T1 and T3, the frequency difference between the right track and the pilot signal is Δf _A , and the frequency difference between the left track and the pilot signal is Δf _B. Along with being there,
The frequency difference between the even-numbered tracks T2 and T4 and the pilot signal of the right track is Δf _B
and the frequency difference between the left track and the pilot signal is Δf _A.

Therefore, the head 12 is on the odd-numbered track T1,
When reproducing T3, if there is a signal with frequency Δf _A as a frequency component of the pilot signal included in the reproduced signal, it is known that the head 12 is shifted to the right, and if there is a signal with frequency Δf _B , the head 12 is shifted to the right.
It can be seen that is in a left-shifted state, and furthermore, it can be seen that tracking is performed correctly when the frequencies Δf _A and Δf _B are absent.

Similarly, head 12 is an even-numbered track T.
2. When reproducing T4, the frequency Δf _B is the frequency component of the pilot signal included in the reproduced signal.
If there is a signal of frequency Δf A, it is known that the head 12 is shifted to the right, and if there is a signal of frequency Δf _A , it is known that the head 12 is shifted to the left.

In this embodiment, the frequencies f 1 , f 2 , f 3 , f 4 assigned to the first, second, third, and fourth tracks _T1 , _T2 , _T3 , and _T4 are f ₁ =102 [ kHz], _f2
= 116 [kHz], f ₃ 160 [kHz], f ₄ = 146 [kHz], therefore, the frequency differences Δf _A and Δf _B are as follows: Δf _A = |f ₁ −f ₂ |= |f ₃ − f ₄ ｜=14 [kHz]
...(1) Δf _B = |f ₂ −f ₃ |= |f ₁ −f ₄ |=44 [kHz]
...(2) has been selected.

The reproduced signal S1 having such content obtained from the head 12 is given to a pilot signal detection circuit 13 having a low-pass filter configuration, and the reproduced signal S1 is
The detected pilot signal S2 obtained by extracting the pilot signals f ₁ to f ₄ contained in the
is given as the multiplication input. The reference pilot signal S11 of the lock point control circuit 15 is applied to the multiplier 14 as a second multiplication input.

The lock point control circuit 15 includes a pilot frequency generation circuit ₁₆ that generates four types of pilot frequency outputs f1 _{to f4} , and two video head outputs associated with a rotating drum ₍ not shown). It has a switch circuit 17 which receives a head switching pulse RF-SW (FIG. 4A) which changes the logic level each time the head scanning the tape is switched. In this embodiment, the switch circuit 17 has a quaternary counter circuit that performs a counting operation every time the level of the head switching pulse RF-SW changes.
The gate signal corresponding to T4 is sequentially repeated, and the gates are opened by the gate signals of tracks T1 to T4, respectively, and the pilot frequency outputs _f1 to f of the pilot frequency generating circuit 16 are generated as shown in FIG. 4B. ₄ sequentially reference pilot signal S1
It is configured to be sent as 1.

The pilot frequency outputs f ₁ to _{f 4} obtained at the output end of this switch circuit 17 are sent to the video head as pilot signals via the signal line 18 during recording, so that the video head can control the first to fourth tracks T1 to F4. While scanning T4, pilot signals of corresponding frequencies _f1 to _f4 are sequentially applied to the video heads to record on the respective tracks T1 to T4.

In this way, while the head 12 scans the first to fourth tracks T1 to T4, a detection pilot signal S2 obtained at the output terminal of the pilot signal detection circuit 13 is generated in synchronization with the reproduction track. By multiplying the reference pilot signal S11 by the reference pilot signal S11, a multiplication output containing a frequency component having a frequency difference between the frequency component included in the detected pilot signal S2 when there is a tracking error and the frequency of the reference pilot signal S11 is obtained. S
12 (actually, the multiplication output S12 also includes other signal components such as the frequency component of the sum). This multiplication output S12 is obtained from the first and second difference frequency detection circuits 2 each composed of a bandpass filter.
0 and 21. The first difference frequency detection circuit 20 extracts the signal component of the frequency difference Δf _A based on the above-mentioned equation (1) in the multiplication output S12 and converts it into a direct current using the direct current converting circuit 22 having a rectifier circuit configuration. The converted DC level first error detection signal S1
Get 3. Similarly, when the multiplication output S12 includes a signal component of the frequency difference Δf _B based on the above equation (2), the second difference frequency detection circuit 21 extracts the signal component from the DC converting circuit 23 An error detection signal S14 is obtained.

If the head 12 deviates to the right while scanning the first, second, third, and fourth tracks T1, T2, T3, and T4, the playback output S of the head 12
As shown in FIG. 4 C1, the detected pilot signal S2 obtained based on 1 is given frequencies f ₁ and f ₂ , f ₂ and f ₃ ,
By including the pilot signals of f ₃ and f ₄ , f ₄ and f ₁ , the difference frequencies Δf _A (=f ₁ to f ₂ ) and Δf _B (=f ₂ ～
f ₃ ), Δf _A (=f ₃ to _{f 4} ), and Δf _B (=f ₄ to f ₁ ) in sequence. On the other hand, if the head 12 is shifted to the left, the detected pilot signal S2 will be as shown in FIG.
As shown in FIG. 2, pilot signals of frequencies f ₄ and f ₁ , f ₁ and f ₂ , f ₂ and f ₃ , f ₃ and f ₄ are sequentially included, and accordingly, the multiplication output S12 is sequentially generated as shown in FIG. D
As shown in 2, the difference frequencies Δf _B (=f ₄ ~ f ₁ ), Δf _A (= f ₁ ~
f ₂ ), Δf _B (=f ₂ to f ₃ ), and Δf _A (= f ₃ to _{f 4} ) in this order.

Thus, as shown in FIGS. 4E and F (for example, showing a right-shifted state), the first and second error detection signals S13 and S14 whose DC level rises from 0 each time the track scanned by the head 12 is switched. It can be obtained from the DC conversion circuits 22 and 23.

First and second error detection signals S13 and S1
4 are applied to the subtraction circuit 24 as an addition input and a subtraction input, respectively, thereby producing the first and second error detection signals S13 and S1 as shown in FIG. 4G.
4 is obtained alternately, a subtraction output S15 that changes in an alternating current manner is obtained. This subtracted output S15 is applied to the first input terminal a1 of the direct changeover switch circuit 25, and its polarity is inverted in the inverting circuit 26 and applied to the second input terminal a2. The changeover switch circuit 25 switches the head 12, for example, to odd-numbered tracks T1 and T by the head switching pulse RF-SW.
When scanning T3, the switching operation is performed to the first input terminal a1 side, and in contrast, even-numbered tracks T2,
When scanning T4, a switching operation is performed to the second input terminal a2, and thus the head 12 is switched to the second input terminal a2 as shown in FIG. 4H.
is in a right-shifted state, positive polarity DC level output S1
6 (on the other hand, in the left-shift state, the DC level output S16 becomes negative polarity), which is sent out via the DC amplifier 27 as an error signal S17. Incidentally, if the head 12 is shifted to the right, for example, a signal component with a frequency difference Δf _A appears at the output terminal of the multiplier circuit 14 when the reproduced track is an odd numbered track T1, T3, so that the first difference frequency detection circuit 2
The output from the 0 side is given to the subtraction circuit 24, and since the changeover switch circuit 25 is switched to the first input terminal a1 side at this time, it sends out an error signal S17 at a positive DC level. On the other hand, when the reproduced tracks are even numbers T2 and T4, the multiplication circuit 1
When the signal component of the frequency difference Δf _B appears at the output terminal of 4, the output from the second difference frequency detection circuit 21 side is given to the subtraction circuit 24, and at this time, the changeover switch circuit 25 is connected to the second input terminal. Since it is switched to the a2 side, the polarity of the negative output of the subtracting circuit 24 is inverted by the inverting circuit 26 and sent as an error signal S17 at a positive DC level.

Therefore, if this error signal S17 is used as a correction signal in the phase servo circuit of the capstan servo circuit, and is corrected so that when it is positive, the tape running speed is made faster, and when it is negative, it is made slower, the video head and playback track can be corrected. It is possible to correct the phase shift between the two and thus realize correct tracking servo.

The magnitude and polarity of the error signals S31 and S32 obtained from the first and second error signal forming circuits 2 and 3 (FIG. 1) having such a principle configuration are determined by the amount of tracking position deviation from the reproduction track of the head 12. The tracking position of the head 12 can be adjusted to any position as necessary by adding the error signals S31 and S32 at a predetermined ratio in the error phase calculation circuit 5 to obtain the tracking error signal S4. Can be adjusted.

That is, the first and second error signal forming circuits 2
and error signals S31 and S32 obtained from 3.
The voltage values E ₁ and E ₂ are multiplied by coefficients α and β in the coefficient circuits 31 and 32 of the error phase calculation circuit 5, and then added in the addition circuit 33, and the resulting voltage value E ₃ E ₃ =αE ₁ +βE ₂ ...(3) is sent to the amplifier circuit 3 as the tracking error signal S4.
4. Therefore, the value E ₃ of the tracking error signal S4 can be determined based on the values E ₁ and E ₂ of the error signals S31 and S32 by selecting the coefficients α and β to arbitrary values as necessary in equation (3). It will be decided.

First, the first error signal forming circuit 2 detects the first, second, third and fourth tracks T1, T2, T3, T.
The first reference pilot signal S33 is sent to the multiplication circuit 14 by the pilot signals of frequencies f ₁ , f ₂ , f ₃ , f ₄ assigned to the track at the timing of reproducing the track 4.
give as. By doing this, when the head 12 is correctly tracking the first track T1 among the tracks T1 to T4 (FIG. 5A), as shown in FIG. Since only the recorded pilot signal _f1 is reproduced, the difference frequencies Δf _A and Δf _B are not obtained at the output of the multiplier circuit 14, and therefore, the error signal S31 is value E ₁
becomes E ₁ =0. However, Fig. 5 B2, B3, B
4, the head 12 is shifted to the right and straddles the first and second tracks T1 and T2, the entire head 12 is in contact with the second track T2, and the head 12 is in the second position. and third track T
2 and T3, the head 12 reproduces the pilot signal _f2 recorded on the second track T2, thereby
The output of the multiplication circuit 14 includes a component of the difference frequency Δf _A (=f ₁ to f ₂ ). Since the magnitude of the component of this difference frequency Δf _A is determined depending on the length of the portion of the head 12 that is in contact with the second track T2, the voltage value _E1 of the error signal S31 is as shown in FIG. 5C. as,
As the head 12 is shifted to the right from the position x1 where the entire head 12 is in contact with the first track T1, it gradually becomes larger in the positive direction, and at the position x2, the entire head 12 is in contact with the second track T2. It reaches its maximum when they face each other, and gradually decreases as it moves further to the right from this state.

However, as shown in FIG. 5B5, when the entire head 12 is shifted to the position x3 where it is in contact with the third track T3, the head 12 reproduces only the pilot signal _f3 recorded on the third track T3. Therefore, the multiplication circuit 14 has the difference frequency Δf _A (=f ₁ ~
f ₂ ) and Δf _B (=f ₁ to f ₄ ) cannot be obtained, so the fifth
As shown in Figure C, the value E ₁ of the error signal S31 is E ₁
=0.

Further, when the head 12 shifts to the right and comes into contact with the fourth track T4 as shown in B6, B7, and _B8 of FIG. , the output of the multiplication circuit 14 includes a component of the difference frequency Δf _B (=f ₁ to f ₄ ). Since its size is determined according to the length of the portion of the head 12 that is in contact with the fourth track T4, the value _E1 of the error signal S31 is determined by the entire length of the head 12, as shown at position x3 in FIG. As the head 12 shifts to the right from the state in which it is in contact with the third track T3, it gradually becomes larger in the negative direction, and reaches a maximum when the entire head 12 is in contact with the fourth track T4 at position x4. , and as it shifts further to the right from this state and approaches position x1, it gradually becomes smaller.

However, when the error signal S31 has a positive value in the curve of the error signal S31 in _FIG . When the tape running speed is increased and the error signal S31 has a negative value, the capstan servo circuit causes all of the heads 12 to move to the first track T.
Correct tracking can be achieved by slowing down the running speed of the tape so that it returns to the lock point _L1 at position x1, which is in contact with L1.

In the above, the playback head 12 uses the first tracking T.
1, but when reproducing the second, third, and fourth tracks T2, T3, and T4, the first error signal forming circuit generates an error signal S31 that enables correct tracking in the same manner. It will be sent from 2.

On the other hand, as shown in FIGS. 6A to 6C in correspondence with FIGS. An error signal S32 that is shifted to the right by a track amount is generated. Therefore, the multiplier circuit 14 of the second error signal forming circuit 2 receives a second reference signal having the same frequency as the pilot signal recorded on a track shifted by one track compared to the case of the first error signal forming circuit 2. Pilot signal S3
4 is given. That is, when the frequencies of the first reference pilot signal S33 of the first error signal forming circuit 2 are f ₁ , f ₂ , f ₃ , f ₄ , the second reference pilot signal of the second error signal forming circuit 3 The frequencies of S34 are f ₄ , f ₁ , f ₂ , and f ₃ . Therefore, the lock point control circuit 4 uses the head switching pulse RF-SW (7th
Figure A) is divided by the 1/2 divider circuit 41 and the divided output S
41 (FIG. 7D), and this frequency-divided output S41 is given to the first switch circuit 42 as a reset signal. In this embodiment, the first switch circuit 42 resets the counter circuit when the divided output S41 falls from the logic "1" level to the logic "0" level, and at this timing as shown in FIG. 7B. The gates of the pilot frequency outputs f ₁ , f ₂ , f ₃ and f ₄ of the pilot frequency generating circuit 45 are repeated again.

On the other hand, the frequency divided output S41 of the 1/2 frequency divider circuit 41 is delayed in the track delay circuit 43, and the delayed output S42 (FIG. 7E) is sent to the second switch circuit 4.
4 as a reset signal. In this embodiment, the second switch circuit 44, like the first switch circuit 42, resets the counter circuit at the falling edge of the delayed output S41, and restarts the pilot circuit at the timing of this falling edge, as shown in FIG. 7C. The gates of frequency outputs f ₁ , f ₂ , f ₃ , and f ₄ are made to repeat.

Thus, the second reference pilot signal S34 sent out from the second switch circuit 44 (FIG. 7C)
In this case, the first reference pilot signal S33 (FIG. 7B) of the first switch circuit 42 corresponds to the pilot frequencies f ₁ , f of the first, second, third, and fourth tracks T1, T2, T3, and T4. ₂ , _f3 , _f4 , one left track T4, T1,
The second reference pilot signal is outputted with pilot frequencies f ₄ , f ₁ , f ₂ , f ₃ at T2 and T3, and the phase of the frequency cycle is shifted by 90 degrees with respect to the first reference pilot signal S33. S34 is obtained.

In this way, as shown in FIG. 6B1, the reproducing head 12 moves to the first track T1 at the position x1.
Head 12 when being tracked correctly.
By reproducing the pilot signal f ₁ , a difference frequency Δf _B (=f ₄ ~f ₁ ) is obtained at the output of the multiplication circuit 14, and as a result, the value E ₂ (FIG. 6C) of the error signal S32 becomes negative. becomes the maximum value. From this state, head 1
2 begins to straddle the second track T2 (FIG. 6, B2), the value _E2 of the error signal S32 becomes smaller as the contact length with the track T1 becomes shorter. Eventually, head 1 at position x2
2 is in contact with the second track T2, E ₂
= 0 (Fig. 6, B3). From this state, the head 12 shifts further to the right and reaches the third track T.
A state in which the head 12 straddles the third track T3 (FIG. 6 B4), a state in which the entire head 12 is in contact with the third track T3 (FIG. 6 B5), a state in which the head 12 straddles the fourth track T4 (the sixth
In Figure B6), the value _E2 of the error signal S32 increases in the positive direction according to the length of the contact between the head 12 and the third track T3, and after reaching the maximum value at position x3. Getting smaller (6th
When the entire head 12 comes into contact with the fourth track T4 at position x4 (FIG. 6B7), the value E ₂ of the error signal S32 becomes E ₂ =0 (FIG. 6C). When the head 12 straddles the first track T1 from this state (FIG. 6, B8), the error signal S32 again increases in the negative direction in accordance with the contact length (FIG. 6, C).

The above has described changes in the error signal _E2 at the timing when the reproducing head 12 reproduces the first track T1.
2, T3, and T4, the second error signal forming circuit 3 similarly sends out an error signal S32 that locks at a position shifted by one track.

Thus, the first and second error signal forming circuits 2
Error signals S31 and S32 (FIG. 5C and FIG. 6C) formed in steps 3 and 3 are multiplied by coefficients α and β in an error phase calculation circuit 5, and then added together and synthesized into a tracking error signal S4. . Therefore, for example, when α=1/2 and β=1/2 are selected, the tracking error signal S4 changes the 0 point to a positive value within the range of 0 to 1 track deviation amount, as shown in FIG. A curve that intersects with the slope will be drawn, and the intersection with this 0 will become a new tracking lock point _L3 shifted to the right. However, the position of this tracking lock point _L3 is determined by the values of α and β, in other words, the first and second error signals S31 and S3.
By changing the ratio of the size of 2, it can be arbitrarily changed as needed within the range of 0 to 1 track.

FIG. 9 shows another embodiment of the present invention, in which a common error signal forming circuit 51 is used in place of the first and second error signal forming circuits 2 and 3 of FIG. The purpose is to obtain two error signals S31 and S32. In this case, in response to the head switching pulse RF-SW (FIG. 10A), a mode switching pulse signal M-SW having a rise width and a fall width as long as, for example, 50H is generated as shown in FIG. 10B. A mode switching signal generation circuit 52 is provided.
On the other hand, the outputs of the first and second switch circuits 42 and 44 of the lock point control circuit 4 are selectively applied to the multiplier circuit 14 through a reference pilot signal changeover switch circuit 53 which is switched by the mode changeover pulse signal M-SW. At the same time, the mode switching pulse signal M-SW is enabled directly and through the inverting circuit 56 to the first and second sample and hold circuits 54 and 55 which receive the output of the changeover switch circuit 25 of the error signal forming circuit 51 as sample input. Give as a signal. The outputs of the sample and hold circuits 54 and 55 are given to the first and second coefficient circuits 31 and 32 of the error phase calculation circuit 5 as first and second error signals S31 and S32.

In the configuration shown in FIG. 9, the mode switching signal M- generated in the mode switching signal generation circuit 52
The first reference pilot signal S33 sent from the first switch circuit 42 at the rising edge of 50H of SW is applied to the multiplication circuit 14 through the reference pilot signal changeover switch circuit 53, thereby converting the signals shown in FIGS. In the same manner as described above, the first error signal S31 is sampled and held in the first sample and hold circuit 54 through the switch circuit 25, and is sent out from the second switch circuit 44 at the falling edge of 50H. second to be done
The reference pilot signal S34 is applied to the multiplication circuit 14 through the reference pilot signal changeover switch circuit 53, whereby the second error signal S31 is applied to the second The sample and hold circuit 55 samples and holds the signal. Thus, the sample-and-hold circuits 54 and 55 alternately update the sample-and-hold values every 50 hours, thereby practically tracking the playback head 12 to a predetermined tracking lock position in the same manner as described above with respect to FIG. I can do it.

Therefore, according to the configuration shown in FIG. 9, the configuration of the error signal forming circuit 51 can be reduced by half compared to the case shown in FIG.

In the above-described embodiment, a case has been described in which the coefficients α and β of the coefficient circuits 31 and 32 of the error phase calculation circuit 5 are fixed, but they may be made variable. This makes it easier to set the tracking lock point.

In addition, in the above embodiment, the tracking lock point was set in the rightward deviation direction, but if the tracking lock point is set in the leftward deviation direction instead, FIGS.
Correspondingly, as shown in FIGS. 11A to 11E, the frequency of the second reference pilot signal S34 is specified by changing the frequency of the first reference pilot signal S33.
When changing to f ₁ , f ₂ , f ₃ , f ₄ (Figure 11B), 1
It is sufficient to change the frequencies f ₂ , f ₃ , f ₄ , f ₁ shifted to the right by the track amount. In this way, as shown in FIG. 12 corresponding to FIG. 8, the second error signal S32 will draw the same curve as if it were shifted to the left by one track from the first error signal S31.
In this way, the tracking lock point _L3 of the tracking error signal S4 can also be set at a position shifted to the left in the range of 0 to 1 track, as shown in FIG.

Also, in this way, the second reference pilot signal S3
Instead of changing the method of designating the frequency of 4 as shown in FIGS. 11A to 11E, a frequency signal as shown in FIG. The same effect can be obtained by inverting the polarity of the error signal S32 by an inverting circuit and applying it to the error phase calculation circuit 5 after obtaining the second error signal S32. Incidentally, if the polarity of the error signal S32 in FIG. 8 is reversed, the error signal S32 shown in FIG. 12 is obtained.
As is clear from the fact that the same waveform as can be obtained, reversing the polarity of the error signal S31 or S32 changes the tracking lock point to 2.
This is because it means that the same effect can be obtained by shifting the track to the right or left.

In addition, in order to obtain the second error signal S32 described above with reference to FIG. 8, in FIG. 1, as shown in FIG. switch circuit 25 of the first circuit 2
However, instead of this, the frequency assignment of the second reference pilot signal S34 is shifted to the right by one track as shown in FIG. The switching operation of the switch circuit 5 of the circuit 3 may be reversed to that of the switch circuit 25 of the first circuit 2. This reverse operation passes the head switching pulse RF-SW to the switch circuit 2 of the second circuit 3 through the inverting circuit.
5 as a switching operation signal. By the way, in this case, the output of the subtraction circuit 24 of the second error signal formation circuit 3 is transferred to the subtraction circuit 2 of the first error signal formation circuit 2 by the inversion circuit 26.
This means that the same effect as when the phase of the second error signal S32 is shifted by two tracks as described above is obtained, and therefore the second reference pilot signal This is because the shift of the track performed by the frequency assignment in S34 is to be undone.

Furthermore, in the above embodiment, the error phase calculation circuit 5 is connected to the first and second coefficient circuits 31 and 32.
and an adder circuit 33, but instead of this, the first
As shown in Fig. 3, the first and second error signals S3
A variable resistor 61 receiving signals S1 and S32 at both ends is provided, and a tracking error signal S4 is output from the movable element.
You can also try to get . In this case, the ratio of the coefficients α and β in equation (3) above is the dividing resistance of the variable resistor 61.
It is determined by the ratio of R〓 and R〓. In this way, the configuration of the error phase calculation circuit 5 can be further simplified, and the ratio of the coefficients α and β can be easily changed, thereby making it easier to set the tracking lock point.

Furthermore, in the above description, the tracks are shifted by controlling the capstan servo circuit using the tracking error signal, but the playback head is shifted by controlling the drum servo circuit. Also good. Further, the recording medium is not limited to tape, but may also be a disk or the like.

Furthermore, in the above embodiment, in order to obtain an error signal in the error signal forming circuit, the error signal is formed by converting the difference frequencies Δf _A and Δf _B obtained by multiplying the detected pilot signal S2 by the reference pilot signal into direct current. However, instead of this, the levels of each of the pilot signals f 1 to f 4 included in the detected pilot signal S2 are detected separately using, for example, a bandpass filter, and this detection output is used to detect the levels of each of the pilot signals f ₁ to f ₄ included in the detected pilot signal S2. An error signal may be generated by comparing between the two.

As described above, according to the present invention, by creating two error signals with different phases and combining them at a predetermined ratio, it is possible to stably shift the tracking phase by an arbitrary amount as necessary. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a tracking control device according to the present invention, FIG. 2 is a block diagram showing its principle configuration, FIG. 3 is a schematic diagram showing a tape track pattern, and FIG. 5 and 6 are schematic signal waveform diagrams used to explain the operation of the first and second error signal forming circuits in FIG. 1. FIG. FIG. 8 is a signal waveform diagram for explaining the frequency assignment of the reference pilot signal; FIG. 8 is a signal waveform diagram for explaining the error phase calculation circuit of FIG. 1; FIG. 9 is a block diagram showing another embodiment of the present invention; FIG. 10 is a signal variant diagram showing the mode switching signal, FIGS. 11 and 12 are signal waveform diagrams showing a modification of the present invention, and FIG. 13 is a connection diagram showing still another modification of the invention. It is. DESCRIPTION OF SYMBOLS 1... Pilot signal detection circuit, 2, 3... First and second error signal forming circuits, 4... Lock point control circuit, 5... Error phase calculation circuit, 11...
Tape, 12...Reproduction head, 13...Pilot signal detection circuit, 14...Multiplier, 15...Lock point control circuit, 16...Pilot frequency generation circuit, 17...Switch circuit, 20th, 21st... 1. Second difference frequency detection circuit, 22, 23... DC conversion circuit, 24... Subtraction circuit, 25... Changeover switch circuit, 26... Inversion circuit, 31, 32... Coefficient circuit, 33... Addition circuit, 41... 1/2 frequency divider circuit, 42, 44... first and second switch circuits,
45...Pilot frequency generation circuit, 51...Error signal forming circuit, 52...Mode switching signal generation circuit, 53...Pilot signal changeover switch circuit, 54, 55...First and second sample hold circuits, 56 ...Inverting circuit, 61...Variable resistor.

Claims (1)

[Claims] 1. The pilot signal reproduced from a recording medium in which a plurality of pilot signals with different frequencies are cyclically recorded on each track, and the frequency of the pilot signal recorded on the plurality of tracks. A difference frequency component is obtained by multiplying the reference pilot signal by a first reference pilot signal whose frequency order corresponds to the order of frequencies, and a tracking error signal of the reproduction head is detected based on the difference frequency component. a first error detection circuit that detects a second error detection circuit;
a second error detection circuit for detecting a tracking error signal of the reproduction head based on the difference frequency component obtained by multiplying the reference pilot signal by the reference pilot signal of the first and second error detection circuits; an error phase calculation circuit that combines first and second error signals generated from the circuit at a predetermined ratio and sends out a tracking error signal; A tracking control device characterized in that scanning is performed with a tracking phase corresponding to a ratio of .