JPH0513759A - Mis transistor - Google Patents

Abstract

PURPOSE:To prevent a MOS transistor from latching up, the transistor possessing a grid-shaped gate electrode which has a long gate length per unit area. CONSTITUTION:In a MOS transistor wherein a source region 2 and a drain region 3 are alternately disposed in a region defined by a gate electrode l formed into a grid configuration on the first conductivity type semiconductor substrate, a high concentration impurity region 4 of the same type as the first conductivity type semiconductor is formed in the source region 2, and the source region 2 and the high concentration impurity region 4 are interconnected with each other through a conductive electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MIS transistor, and more particularly, to an MIS transistor which occupies a large area used for an output buffer.
Regarding an OS transistor.

[0002]

2. Description of the Related Art Conventionally, a MOS transistor of this type has a shape in which a gate electrode 1 is formed in a lattice shape as shown in FIG. 2 and a drain or source region 2 is formed in a region partitioned by the gate electrode 1.

[0003]

However, with such a shape, the substrate potential bias region is usually formed around the outer periphery of the MOS transistor. However, when a transistor having such a shape is used in the output buffer section that requires high current driving, when a high current flows through the channel of the MOS transistor, the substrate potential changes in the central region, resulting in a latch-up phenomenon. There is a drawback that is likely to occur. In addition, 3 is a drain region, 5 is a contact hole, 6 is a source electrode, and 7 is a drain electrode.

[0004]

SUMMARY OF THE INVENTION The present invention aims to solve the problems of the prior art, and has realized a MOS transistor in which the latch-up phenomenon is unlikely to occur. Specifically, in a MOS transistor in which a source region and a drain region are alternately arranged in a region defined by a gate electrode formed in a grid pattern on a first conductivity type semiconductor substrate, A high-concentration impurity region of a one-conductivity type semiconductor is provided.

[0005]

As shown in FIG. 1, the MOS transistor of the present invention has a high-concentration impurity region of the same conductivity type as that of the substrate in the source region. Because of this, the latch-up phenomenon is unlikely to occur.

[0006]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a schematic view of a MOS transistor according to the present invention. The source regions 2 and the drain regions 3 are alternately formed in a plurality of portions partitioned by the gate electrode 1 formed in a lattice shape. A high-concentration impurity region 4 having the same conductivity type as the substrate is formed in the formed source region. Further, contact holes 5 are provided in all partitioned regions, the source region is connected to the source electrode 6, and the drain region is connected to the drain electrode 7. However, in this case, the contact hole 5 in the source region is formed so as to include the high concentration impurity region.

In this way, each source region is held at the same potential by the high concentration impurity region 4 formed therein and the source electrode 6.

[0008]

As described above, according to the present invention, a conductive type impurity region having the same polarity as that of the substrate is formed in the source region of the island region defined by the gate electrodes arranged in a grid pattern. By doing so, there is an effect that it is possible to realize a high-current driving MOS transistor having high latch-up resistance without breaking the regular structure.

[Brief description of drawings]

FIG. 1 is a plan view of a MOS transistor of the present invention.

FIG. 2 is a plan view of a conventional MOS transistor.

[Explanation of symbols]

 1 gate electrode 2 source region 3 drain region 4 substrate bias region 5 contact hole 6 source electrode 7 drain electrode

Claims (1)

Claim: What is claimed is: 1. A MIS transistor comprising a first conductivity type semiconductor substrate, wherein a source and a drain are regions divided into islands by gate electrodes formed in a grid pattern with an insulating film interposed therebetween. A high-concentration impurity region of the same type as the first conductivity type semiconductor substrate is formed in the region serving as the source, and the region serving as the source and the high-concentration impurity region are connected by a conductive electrode. MIS transistor.