JPH05134998A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To detect the faults of all the processors by dividing plural processors into plural fault detection groups, and connecting a device which detects and processes the fault of the whole system based on fault information from a fault detection processor in each group to a system bus. CONSTITUTION:The plural processors 2 are divided into the plural fault detection groups 3 at every processor related functionally, and the processor that becomes the core of each fault detection group 3 is designated as the fault detection processor 2a which detects the fault in the group. The fault information I1 from the fault detection processor 2a is sent to a fault information processor 4 connected to the system bus 1, and the fault of the whole system can be detected and processed. Thereby, it is possible to detect the faults of all the processors 2, and to suppress burden from increasing since it is enough to process the fault information from the fault detection processor 2a in each group 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system in which a plurality of processors having a self-fault diagnosis function are connected by a system bus. The present invention relates to a multiprocessor system having a fault tolerance (fault tolerance) function such as startup.

[0002]

2. Description of the Related Art In order to improve the reliability of a multiprocessor system, not only the self-fault diagnosis function of each processor but also fault tolerance of the whole system such as fault monitoring, single lung operation, stop, automatic batch restart, etc. It is necessary to have a function.

FIG. 5 is a block diagram showing a conventional example of a multiprocessor system having a fault tolerance function of this type (Japanese Patent Laid-Open No. 64-55669).

As shown in the figure, a plurality of processors 21, 22, 23 having a self-diagnosis function, and a display, a printer, an external storage device and the like which operate according to commands from these processors 21, 22, 23 are installed. The output channel ports (I / Och.) 24 to 27 are connected to the system bus 28.
Are joined by. A system monitoring device 29 (hereinafter abbreviated as monitoring device 29) is connected to the system bus 28. The system monitoring device 29
A failure diagnosis counter 30 (hereinafter abbreviated as counter 30) is provided, and the counter 30 is incremented at a constant cycle after the system starts.

In this multiprocessor system, some of all the processors 21, 22, 23, for example, the processors 21 and 22 are designated in advance as important processors. This important processor is a core processor of the system that can continue the system operation if this processor is normal even if another processor fails.

In the multiprocessor system having the above-mentioned structure, when the power is turned on, the monitoring device 29 causes all the processors 21, 22, 23 and the input / output channel ports 24.about.
A reset signal S1 is sent to 27. Then, all the processors 21, 22, 23 initialize themselves at the stage of receiving the reset signal S1 and simultaneously start the operation. In addition, the important processors 21 and 22 output the alive signal S2 indicating the existence of their own health to the monitoring device 29 in a constant cycle.

The monitoring device 29 includes important processors 21 and 2.
When the alive signal S2 is received from 2, the counter 30 is reset. But all the important processors 21, 22
In the case where a failure occurs and the alive signal S2 is not sent from any of the important processors 21 and 22, the monitoring device 29 continues to increment the counter 30.

The monitoring device 29 then sends the alive signal S2.
If the value of the counter 30 exceeds the preset allowable value without being received, it is recognized that a system failure, that is, a situation in which the operation of the system cannot be continued has occurred, and the reset signal S1 is output. To do. As a result, all the processors 21, 22, 23 will initialize themselves and restart.

However, when one of the important processors 21 and 22 is alive and outputs the alive signal S2, the reset signal S1 is output so that the monitoring device 29 resets the counter 30 at a constant cycle. Therefore, the operation of the system continues.

[0010]

However, in the above conventional multiprocessor system, the important processor 2 is used.
There is a problem that a failure that occurs in the processor 23 not designated as No. 1 or 22 is not detected. If all processors 21, 22, 23 are designated as important processors,
The alive signal S2 to be processed by the monitoring device 29 increases,
The load on the monitoring device 29 becomes very large.

The present invention has been made in order to solve the above-mentioned problems, and not only a system important processor but also
It is an object of the present invention to obtain a multiprocessor system capable of detecting a failure in other processors as well as suppressing an increase in load on a device for detecting and processing the failure.

[0012]

To achieve the above object, in a multiprocessor system according to the present invention, a plurality of processors are divided into a plurality of fault detection groups for each processor functionally associated with each other, and The central processor of each failure detection group is designated as a failure detection processor that detects a failure in each group. Further, a fault information processing device that detects and processes a fault in the entire system based on the fault information from the fault detection processor of each fault detection group is connected to the system bus.

[0013]

In the multiprocessor system having the above configuration, not only the system-important processor designated as the fault detection processor but also other processors are processed by the fault information processing device via the fault detection processors of the respective fault detection groups. The fault is detected.
In other words, for all processors that make up the system,
A fault can be detected for each fault detection group according to function.

Further, since the fault information processing device for detecting and processing the fault only needs to process the fault information from the fault detection processor of each fault detection group, the load on this fault information processing device can be suppressed.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

First Embodiment FIG. 1 is a block diagram showing a first embodiment of a multiprocessor system according to the present invention.

As shown in the figure, in this multiprocessor system, a plurality of processors 2 having a self-fault diagnosis function, which are connected by a system bus 1, are assigned to a plurality of fault detection groups 3 for each processor which is functionally related. It is divided. At the same time, the central processor of each failure detection group 3 is designated as the failure detection processor 2a. The fault detection processor 2a detects a fault in each fault detection group 3 and outputs fault information I1 including a fault occurrence signal and processor recognition data.

A fault information processing device 4 is connected to the system bus 1. This fault information processing device 4 detects and processes a fault of the entire system based on the fault information I1 from the fault detection processor 2a of each fault detection group 3, and as shown in the block diagram of FIG. It is composed of a different fault information storage unit 5, a fault information collection control unit 6, and a fault information processing unit 7.

In the above configuration, each failure detection group 3
The fault detection processor 2a of 1 detects the fault in each fault detection group 3 by polling the other processors 2 in the fault detection group 3 via the system bus 1. That is, the other processors 2 that have received the polling sequence from the fault detection processor 2a inform the fault detection processor 2a of the presence or absence of a fault by the polling signal S. When the fault detection processor 2a recognizes the occurrence of a fault by the polling signal S, it sends fault information I1 to the fault information processing device 4. Further, when a failure occurs in the failure detection processor 2a itself, the failure detection processor 2a immediately sends the failure information I1 to the failure information processing device 4.

In the fault information processing device 4, when the fault information I1 is sent from the fault detection processor 2a of one of the fault detection groups 3, the fault information storage section 5 for each group stores the fault information I1. Next, the fault information collection control unit 6 directly collects information about the fault content from the faulty processor 2 through the system bus 1. Then, the failure information processing unit 7 determines appropriate processing for the failure that has occurred based on the collected information, and detects failure processing information I2 including data necessary for the processing and a reset signal for each failure. It is sent to the processor 2 of the group 3 to perform processing for the failure. In this way, the fault tolerance function works.

As described above, in this multiprocessor system, not only the system-important processor designated as the fault detection processor 2a but also the other processors 2 have their fault detection groups 3 respectively.
The fault can be detected through the fault detection processor 2a. In other words, it is possible to detect a failure for each function-dependent failure detection group 3 for all the processors 2 configuring the system. Moreover, a failure of the failure detection processor 2a, which is a serious failure in the system, can be immediately dealt with because the failure detection processor 2a immediately sends the failure information I1 to the failure information processing device 4. That is, one processor 2 in the failure detection group 3
It is possible to deal with the failure that has occurred in 1) according to the importance of the processor 2 in the failure detection group 3.

Further, since the fault information processing device 4 for detecting and processing the fault has only to process the fault information I1 from the fault detection processor 2a of each fault detection group 3, the load on the fault information processing device 4 is reduced. The increase is suppressed.

Second Embodiment FIG. 3 is a block diagram showing a second embodiment of the multiprocessor system according to the present invention.

As shown in the figure, in the case of the second embodiment, each failure detection group 3 divided as in the first embodiment.
The internal processors 2 are connected to each other through a fault detection dedicated bus 8. Then, the fault detection processor 2a of each fault detection group 3 polls the other processors 2 in the fault detection group 3 via the fault detection dedicated bus 8 so that each fault detection group 3
To detect a fault within. In this way, the fault detection dedicated bus 8
By providing the system bus 1 for fault detection
It is possible to reduce the frequency of using, and suppress the deterioration of the performance of the entire system.

Third Embodiment FIG. 4 is a block diagram showing a third embodiment of the multiprocessor system according to the present invention.

As shown in the figure, in this multiprocessor system, the method of forming the fault detection group 3 is different from that of the above two embodiments 1 and 2. In other words, the plurality of processors 2 connected by the system bus 1 include lower groups, from the highest failure detection group to the lowest failure detection group, for each processor that is functionally related. It is divided into a plurality of failure detection groups 3 in the form. It is assumed that the higher the fault detection group 3, the more important the system has in function.
The central processor of each failure detection group 3 is designated as the failure detection processor that detects a failure in each failure detection group 3. In the case of the third embodiment, as the failure detection group 3, a highest failure detection group 3a, an intermediate quasi-failure detection group 3b, and a lowest quasi-fault failure detection group 3c are formed, and each group 3a, One of the processors 2 of 3b and 3c is designated as the fault detection processor 2a, the quasi-fault detection processor 2b, and the quasi-quarter fault detection processor 2c, respectively.

Further, each of the fault detection groups 3a, 3 described above
If there is a lower group, the processors 2 in b and 3c are connected to the fault detection processors of the lower group by fault detection dedicated buses 9, 10, and 11. That is, the processors 2 in the highest-level failure detection group 3a are connected together with the quasi-failure detection processor 2b in the quasi-failure detection group 3b through the failure detection dedicated bus 9, and the processors 2 in the quasi-failure detection group 3b are detected in the quasi-failure detection. The quasi-fault detection processor 2c of the group 3c is connected to the quasi-fault detection dedicated bus 10. The processors 2 of the lowest quarter-fault detection group 3c are connected by a quarter-fault detection dedicated bus 11.

Further, the system bus 1 is connected to a fault information processing device 4 for detecting and processing a fault in the entire system, as in the above-described first and second embodiments.

In the multiprocessor system having the above-mentioned configuration, the fault detection processors 2a, 2b, 2c of the fault detection groups 3a, 3b, 3c have the fault detection dedicated buses 9,
By polling via 10 and 11, the fault detection processor 2a of the highest fault detection group 3a finally detects the fault in each of the groups 3a, 3b and 3c, and the fault information processing device 4 is faulted. The information I1 is output. Then, the fault information processing device 4 receives the fault information I1 from the fault detection processor 2a of the highest fault detection group 3a.
Based on the above, the fault processing information I2 is sent to the processor 2 of each fault detection group 3a, 3b, 3c as described in the first embodiment, and the process for the fault is performed.

In the case of the multiprocessor system according to the third embodiment, each fault detection group 3a, 3b, 3c classified by function is hierarchically constructed, so that it occurs in one processor 2 in the system. The failure can be dealt with according to the importance of the function of the group 3 to which the processor 2 belongs in the system and according to the importance of the processor 2 in the group 3.

Further, the fault information processing device 4 for detecting and processing the fault of the entire system is the fault detection group 3 at the highest level.
Since it is necessary to process only the fault information I1 from the fault detection processor 2a of a, the load on the fault information processing device 4 can be further suppressed as compared with the cases of the above two embodiments 1 and 2.

[0032]

As described above, according to the multiprocessor system of the present invention, it is possible to detect a fault not only in a system-important processor but also in another processor, and a device for detecting and processing the fault. It is possible to suppress an increase in the load on the.

Furthermore, it becomes possible to deal with a failure occurring in one processor in the system according to the importance of the processor.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a fault information processing device.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a block diagram showing a third embodiment of the present invention.

FIG. 5 is a block diagram showing a conventional example.

[Explanation of symbols]

 1 System Bus 2 Processors 2a, 2b, 2c Fault Detection Processor 3 (3a, 3b, 3c) Fault Detection Group 4 Fault Information Processing Device 8, 9, 10, 11 Fault Dedicated Bus

Claims (3)

[Claims] 1. A multiprocessor system in which a plurality of processors having a self-fault diagnosis function are coupled by a system bus, wherein the plurality of processors are grouped into a plurality of fault detection groups for each processor functionally associated with each other. In addition to dividing, specify the central processor of each fault detection group as the fault detection processor that detects the fault in each group, and specify the fault information from the fault detection processor of each fault detection group on the system bus. A multiprocessor system characterized in that a failure information processing device for detecting and processing a failure of the entire system based on the system is connected. 2. In a multiprocessor system in which a plurality of processors having a self-fault diagnosis function are connected by a system bus, the plurality of processors are grouped into a plurality of fault detection groups for each processor functionally associated with each other. In addition to dividing, specify the central processor of each fault detection group as a fault detection processor that detects a fault in each group, and connect the processors in each fault detection group with a fault detection dedicated bus, A multiprocessor system characterized in that a fault information processing device for detecting and processing a fault of the entire system based on fault information from a fault detection processor of each fault detection group is connected to the system bus. 3. A multiprocessor system in which a plurality of processors having a self-fault diagnosis function are connected by a system bus, and the highest level fault detection is performed for each processor functionally associated with the plurality of processors. From the group to the lowest fault detection group, the upper group divides the lower groups into multiple fault detection groups, and the central processor of each fault detection group is used to identify the faults in each group. Specify the fault detection processor to detect and connect the processors in each fault detection group together with the fault detection processors of the lower groups with the fault detection dedicated bus, and connect the system bus to the fault of the top fault detection group. Detects faults in the entire system based on fault information from the detection processor. Multiprocessor system characterized by connecting the fault information processing apparatus for processing.