JPH05129624A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To share a plurality of cells by one contact and allow high integration by arranging select transistors on the both sides of a plurality of memory transistors, connecting the select transistors in series using a diffused layer and providing one shared contact on the external side of the select transistor of one side. CONSTITUTION:A plurality of memory transistors MT11, MT21, MT31-MT81 are connected in series through a diffused layer 9 and select transistors ST01 and ST91 are connected in series on the both sides of the memory transistors so as to form a memory block. Then, a contact and a conductive film BL1 are provided on the diffused layer 9 of the select transistor ST01 on the opposite side of the memory transistor MT11, in order to apply potential on the memory block. Thus, a plurality of cells are shared by the one contact and high integration is allowed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having an area occupied by 1 bit reduced.

[0002]

2. Description of the Related Art FIG. 1 shows a plan view of a conventional cell structure of this type. The hatched region Y is the gate electrode of each cell, and one contact C is provided for two cells (bits).

[0003]

In this structure, since one contact can share only two bits, the area occupied by one bit (indicated by Q) is large, which hinders high integration. The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor memory device capable of coping with high integration by sharing two bits or more with one contact.

[0004]

SUMMARY OF THE INVENTION The present invention is a trap type non-volatile memory transistor that stores "0" and "1" by storing charges in an insulating film, in which two or more memory transistors are arranged. MOSFETs are arranged on both sides of a transistor row, and a diffusion layer connects the memory transistor and the MOSFET in series to form a memory block. In order to apply a potential to the memory block, a contact and a conductive layer are provided. Membrane and the above-mentioned MOSFE
It is characterized in that it is provided in a diffusion layer of T on the side opposite to the memory transistor.

[0005]

According to the semiconductor device having the above structure, a plurality of cells can be shared by one contact C as shown in FIG. 2, and in this case, the areas Q ₁ and Q ₂ occupied by the cells on both sides of the contact C are Although the same as in the case of FIG. 1, the areas occupied by the other cells Q ₂ , Q _3, ..., Q ₂ ′, Q ₃ ′ ...
The area is smaller than the areas Q ₁ and Q _2, and therefore high integration is possible.

[0006]

EXAMPLE In this example, an 8-bit NAND structure will be described as an example. First, the manufacturing process will be described with reference to FIGS. In FIG. 3, an n-type substrate (N (10
0), ρ = 2 to 3 Ωcm) 1, and the surface concentration N = 2 ¹⁶ c
forming a Pwell substrate 2 of m ⁻³ , xj = 6 μ, and L
The element isolation region 3 is formed by the OCOS method. Furthermore,
An oxide film (Tox: 400 angstrom) 4 is formed thereon, and finally a doped Poly-Si layer 5 is formed.

Next, as shown in FIG. 4, in order to form the gate electrodes SG ₁ and SG ₂ of the select transistor,
By patterning, the unnecessary Poly-Si layer 5 is removed. Then, as shown in FIG. 5, the tunnel oxide film (Tox: 20 angstrom) 6, the SIN film (Tsi
n: 200 Å) 7, doped Poly-S
The i layer 8 is formed.

Then, as shown in FIG. 6, in order to form the gate electrodes MG _{1 to} MG ₈ of the memory transistor,
Poly-Si layer 8 doped by patterning
Is partially removed, and arsenic I is added to the Pwell substrate 2.
The MPLA, ^{n +} diffusion layers (As: E = 70kV, N = 5
¹⁵ cm ⁻³ ) 9 is formed. As a result, as shown in the drawing of FIG. 6, select transistors ST ₀₁ and ST _{91 formed} of enhancement MOSFETs on both sides and eight memory transistors MT ₁₁ to MT _{81 between them.}
Are formed respectively.

Next, as shown in FIG. 7, the n ⁺ diffusion layer 9
The annealing is performed (heat treatment) in order to activate, and further an interlayer film 10, one of the select transistors ST ₀₁
Forming a contact 13 on the diffusion layer 9 further outside, and forming a conductive film 14 on each transistor in contact with the contact 13, and finally forming a passivation layer 15 by P-SIN. Is completed by.

FIG. 8 is a plan view of FIG. 7 and its equivalent circuit is shown in FIG. As shown in FIG. 9, eight memory transistors _{MT 11, MT 21, MT 31} ~MT
₈₁ is connected in series via each diffusion layer 9, and select transistors ST ₀₁ and ST ₉₁ are located on both sides of these memory transistors MT. The memory transistor MT used here is a so-called MNOS transistor using a NO film (nitriding-oxide film) as a trap film.
Further, the vertical line in FIG. 9 is the bit line BL1 for the eight memory transistors MT arranged in columns, which corresponds to the conductive film 14 in FIG.

FIG. 10 shows an example of connection in the semiconductor device of the present invention. As can be seen from this figure, the bit line BL1 has eight memory transistors MT.
_{11 to} MT _{81 as} well as another 8 arranged in the same row
It is also used for the individual memory transistors MT ₁₁ ′ to MT ₈₁ ′, and one contact 13 provides 16 cells.
Share the bits.

Memory write and erase operations of the semiconductor device of FIG. 10 will be described below. The MNOS type memory transistor MT used here exhibits a hysteresis characteristic between the gate voltage and the threshold voltage Vth. As shown in FIG. 11, when the gate voltage is increased to 10 V or higher from the low Vth state, Vth increases, and when the gate voltage is about 15 V, Vth saturates to about 3 V. On the contrary, if the gate pressure is reduced to -10 V or less from the high Vth state, V
The th also decreases, and when the gate voltage is about −15V, Vth is saturated to about −3V. Vth = 3V written state, Vth =
-3V is set to the erased state.

[0013] Now, in FIG. 10, for example, considering the case of writing data "1" into the memory transistor _{MT 21, 0V} to the gate _{SG 2, MG 1, MG 3} ~
7V is applied to MG ₈ , 7 to 15V is applied to SG ₁ , and 15V is applied to the gate MG ₂ of the memory transistor MT ₂₁ . At this time, the select transistor ST ₉₁ is off, and the memory transistors MT _{11 to} MT ₈₁ are on because the voltage Vth or more is applied to their gates.
_{01 is} also on.

In this state, each memory transistor MT
The channel potential of, when BL1 = 0V since it is connected to the potential of the bit line BL1, the potential difference between 15V only memory transistor _{MT 21} is applied between the gate and channel, the other memory transistors _MT 11, M
Only 7V is generated between the gate channels of T _{31 to} MT ₈₁ . Therefore, due to the hysteresis loop of the MNOS transistor, the memory transistor MT
Only No. ₂₁ has the threshold voltage Vth of 3V, which means that the data has been written.

At this time, 7V is applied to the other bit line BL2.
Is applied, the memory transistors MT _{12 to} MT ₈₂
Because each channel surface appears a potential of 7V, the memory transistor _{MT 12, MT} 32 _{~MT 82} between the gate and the channel potential difference 0V, the memory transistor M
T _22, because rests 15V to the gate MG _2, 15-7 = 8V potential difference is generated. Therefore, no data is written to any memory transistor.

At this time, no voltage is applied to the gates MG ₁ ′ to MG ₈ ′, and 0 V is applied to the gate SG ₁ ′ to turn off the select transistors ST ₀₁ ′ and ST ₀₂ ′. The potential of the bit line never appears on the channel. Therefore, the memory transistors MT ₁₁ ′ to M
No data is written to T ₈₁ ′ and MT ₁₂ ′ to MT ₈₂ ′.

Similarly, when writing data to the memory transistor MT ₁₁ , 15 is applied to its gate MG ₁ .
V, and 7V is applied to the other gate _MG 2 _{~MG 8,} only possible to generate a 15V potential difference between the gate and the channel to the memory transistor _{MT 11,} data only in the memory transistor _{MT 11} is written.

Next, the erase operation for the memory transistor (Vth = 3V) in which the data is written will be described.
When the substrate 2 is set to a high potential of 15V and the gate MG _{1 is set} to 0V, a potential difference of −15V is generated between the gate and channel in the memory transistors MT ₁₁ and MT ₁₂ connected to the gate MG ₁ , so that the memory transistor MT
₁₁ , Vth of MT ₁₂ becomes -3V, which means that the data has been erased. In this way, erasing is performed in units of memory transistor gates. When it is desired to erase the data in the memory transistor MT ₂₂ , its gate MG _{2 is set} to 0V, the substrate 1
Is set to 15V.

The read operation of the last written data will be described. Data reading is determined by applying 0V to the gate of the memory transistor MT desired to be read and flowing current. That is, when Vth = 3V (when written), the memory transistor does not turn on even if 0V is applied to the gate, but when Vth = 3V (when erased), when the gate is set to 0V, the memory becomes The transistor turns on.

Consider, for example, the case of reading data from the memory transistor MT ₂₁ . OV to the gate MG _2, to the gate _{MG 1, MG 3 ~MG 8 5V} , gate _SG 1, _SG
When 5V is applied to ₂ , the transistors other than the memory transistor MT ₂₁ are rendered conductive regardless of Vth. Therefore, the memory block (select transistors ST ₀₁ and ST ₉₁ and the memory transistor M
Whether or not the whole of T _{01 to} MT ₈₁ ) is in a conductive state depends on whether or not the memory transistor MT ₂₁ is in a conductive state. Therefore, the presence / absence of data is determined by applying a potential of about 5 V to the bit line BL1 and determining whether or not a current flows through the memory block. At that time, the gate SG ₁ '
0V is applied to the select transistor ST ₀₁ '
Is turned off and 5 V is applied to the bit line BL1, the memory block (select transistors ST ₀₁ ', S
T ₉₁ ′ and memory transistors MT ₀₁ ′ to MT
₈₁ ') so that no current flows into it.

Similarly, in order to read the data of the memory transistor MT ₁₁ , its gate MG ₁ is 0V, the other gates MG _{2 to} MG ₈ are 5V, and the gates SG ₁ and SG ₂ are 5V.
V is given and it is judged whether or not a current flows in this memory block. In this embodiment, one contact 13
Although 6 cells are shared, any number of cells can be shared.

[0022]

As described above, according to the present invention, select transistors are arranged on both sides of a plurality of memory transistors, and each of these transistors is connected in series by a diffusion layer, and one select transistor is connected. Since one shared contact is provided on the outside, a plurality of cells can be shared by one contact, which enables high integration.

[Brief description of drawings]

FIG. 1 is a plan view showing a cell structure of a conventional semiconductor memory device.

FIG. 2 is a plan view showing a cell structure of a semiconductor memory device of the present invention.

FIG. 3 is a cross-sectional view showing the manufacturing process of the semiconductor memory device of the present invention.

FIG. 4 is a sectional view showing a manufacturing process of the semiconductor memory device of the present invention.

FIG. 5 is a sectional view showing a manufacturing process of the semiconductor memory device of the present invention.

FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor memory device of the present invention.

FIG. 7 is a sectional view showing an embodiment of a semiconductor memory device of the present invention.

FIG. 8 is a plan view of the semiconductor memory device of FIG.

9 is an equivalent circuit diagram of the semiconductor memory device of FIG.

FIG. 10 is a connection diagram when the semiconductor memory device of FIG. 7 is actually used.

FIG. 11 is a diagram showing a hysteresis characteristic of a memory transistor.

[Explanation of symbols]

1 n-type substrate 2 Pwell substrate 3 Element isolation region 4 Oxide film 5 Poly-Si layer 6 Tunnel oxide film 7 SIN film 8 Poly-Si layer 9 n ⁺ diffusion layer 10 Interlayer film 13 Contact 14 Conductive film 15 Passivation layer MT memory Transistor ST Select transistor MG gate SG gate BL bit line

Claims (1)

[Claims] 1. A "0" is obtained by storing electric charge in an insulating film.
In a trap type non-volatile memory transistor that stores "1", MOSFETs are arranged on both sides of a memory transistor row in which two or more memory transistors are arranged, and a diffusion layer is provided between the memory transistor and the MOSFETs in series. A semiconductor memory device, characterized in that a contact and a conductive film are provided in a diffusion layer on the opposite side of the memory transistor of the MOSFET in order to form a memory block connected to the memory block and to apply a potential to the memory block. ..