JPH05129564A - Semiconductor memory device and fabrication thereof - Google Patents

Abstract

PURPOSE:To make it possible to arrange a plurality of gate electrodes closely at high density by arranging a plurality of gate electrodes, formed in MIOS structure on a region having same conductivity type between source and drain, closely and linearly in the direction of source and rain. CONSTITUTION:Drain D and source S of n<+> region are provided on an isolated p-type substrate and a p<-> region is formed between the drain D and the source S. A tunnel oxide film 102, a nitride film 103 and an oxide film 104 are formed on the p<-> region and polysilicon gate electrodes CG1-CG8 are provided thereon. The gate electrodes CG1-CG8 are isolated, respectively, through quite thin oxide films. A wiring pattern is formed thereon by means of Al wirings 305a, 305b while interposing an insulation oxide film. According to the invention, memory density is considerably increased and flatness is improved on the top face of the gate electrodes CG1-CG8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MIO structure (MON
The present invention relates to a semiconductor nonvolatile memory having an OS structure, a MNOS structure, and a MAOS structure), and is particularly suitable for further increasing the integration degree of a NAND type memory cell structure.

[0002]

2. Description of the Related Art As a semiconductor non-volatile memory having a MIO structure or a floating gate type structure, a NAND type memory cell structure has been considered in order to increase its integration degree (storage density). For example, as an example of the former, Japanese Patent Laid-Open No. 2-110966 discloses a NAND type memory cell structure as shown in FIG. As an example of the latter, there is a NAND as shown in FIG. 5 in "Japanese Patent Laid-Open No. 2-94197".
Type memory cell structures are described.

[0003]

A semiconductor non-volatile memory having a MIO structure is called an EEPROM and can be electrically rewritten many times, so that it is considered to be applied to a wide range of purposes. However, at present, a low capacity of several kilobits has been put into practical use and put on the market, and there is a demand for higher capacity and higher integration.

[0004]

In order to solve the above-mentioned problems, a semiconductor memory device of the present invention is a semiconductor memory device including an MIO transistor (including a MONOS structure, a MNOS structure, and a MAOS structure). Has a region of the same conductivity type between its source and drain, and the MIO structure (MONOS) is formed on this region.
(Including a structure, a MNOS structure, and a MAOS structure), a plurality of gate electrodes are arranged linearly close to each other in the source / drain direction.

Further, a method of manufacturing a semiconductor memory device according to the present invention is a method of manufacturing a MIO transistor (MONOS structure, MNOS).
Structure, including a MAOS structure), a polysilicon film and a second nitride film on the polysilicon film are formed on a substrate on which an oxide film and a first nitride film are sequentially formed. A first step of forming a film and a polysilicon film and a second nitride film are alternately removed at a predetermined pitch,
A second step of forming a plurality of gate electrodes of one group forming the MIO transistor, a third step of oxidizing a side surface of the gate electrodes of the one group to form an insulating film, and a gate of one group A fourth step of depositing polysilicon between the electrodes to form the other group of gate electrodes;
It is characterized in that the gate of the OS transistor is formed.

Further, in the first step, a polysilicon film and a second nitride film are formed on the polysilicon film on a substrate on which an oxide film, a first nitride film and an oxide film are sequentially formed. You may feature that.

[0007]

In the semiconductor memory device of the present invention, the plurality of gate electrodes between the source and the drain accumulate charges on the surface level of the nitride / oxide film of the MIO structure near the gate electrodes. As a result, one MIO transistor stores data of the number of bits corresponding to the number of gate electrodes.
A plurality of gate electrodes are closely arranged at high density as regions of the same conductivity type between the source and the drain to form a NAND type memory cell structure.

According to the method of manufacturing the semiconductor memory device of the present invention,
Since the insulating film is formed on the side surface of the gate electrode formed in the second step and the gate electrode is further formed between the gate electrodes, the gate electrodes can be closely arranged at high density.

[0009]

Embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a MONOS constituting a semiconductor memory device of the present invention.
3 shows an MIOS transistor (memory cell) having a structure.

In this MIO S transistor, a drain D and a source S in an n ⁺ region are provided on a p-type substrate separated from each other, and a p ⁻ region is provided between the drain D and the source S. On this p ⁻ region, a tunnel oxide film (SiO 2
₂ ) 102, nitride film (SiN) 103, oxide film (SiO
₂ ) 104 is formed and polysilicon gate electrode CG
1 to CG8 are provided. Each gate electrode CG1 to C
G8 is insulated with a very thin oxide film between them. Then, the Al wiring 305 is sandwiched by the insulating oxide film.
A wiring pattern of a and 305b is formed.

The MIOS transistor of FIG. 1 is equivalently expressed as a MIOS transistor having a large number of gates such as Q1 of FIG. 2 like the one of FIG. 4 or FIG. Illustrated those with electrodes). There is no n ⁺ region between the drain D and the source S as compared with the one shown in FIG. 4, and the gate electrodes CG1 to CG8
It is characterized by the fact that the intervals between are very narrow.
Therefore, the memory density is very high, and the gate electrodes CG1 to CG1
The upper surface of CG8 has good flatness.

The operation of the MIOS transistor of FIG. 1 will be described with reference to the circuit of FIG.

First, as an example of the write / read operation,
It is assumed that writing is performed on the gate electrode CG5. At this time, the gate electrodes AG1, CG1 to CG4 are set to low (0 V) to turn off the gate electrodes CG1 to CG4 of the transistor Q2 and the transistor Q1. Gate electrode AG2
CG6 to CG8 are set to high (5V) and the transistor Q
3 and the gate electrodes CG6 to CG8 of the transistor Q1 are turned on. A voltage of 20 V is applied to the gate electrode CG5 for a predetermined time, and the tunnel oxide film 102.
Negative charges are accumulated and stored in the surface level of the nitride film 103.

When reading data from the gate electrode CG5, the gate electrodes CG1 to CG4 of the transistor Q1 are read.
Bring CG6-CG8 (other than CG5) high. The threshold voltage V _th is different between that the negative charge is accumulated in the vicinity of the gate electrode CG5 and that it is not. Threshold voltage V
_The data is read by detecting the difference in _th .

The step of forming the gate of this MIO transistor will be described with reference to FIG.

After element isolation by a normal LOCOS process, a tunnel oxide film 102 and a nitride film 10 are formed on a substrate 101.
3, the oxide film 104 is formed (step of FIG. 3A). Here, the tunnel oxide film 102 is diluted and oxidized at 900 degrees Celsius to form about 20 angstroms. The nitride film 103 is nitrided at 700 degrees Celsius to form about 150 angstroms. The oxide film 104 is oxidized at 950 ° C. to form about 80 angstrom. Next, the polysilicon film 10
5 and the nitride film 106 are formed (step of FIG. 3B).
The polysilicon film 105 and the nitride film 106 are patterned (step in FIG. 3C). RIE is used for etching here, and fine etching with good directionality is performed. Polysilicon film 105 and nitride film 106
Are alternately removed at a predetermined pitch to form one group of gate electrodes 105a.

After removing the resist 107, dry thermal oxidation is performed to form a thin oxide film 108 on the side surface of the gate electrode 105a (step of FIG. 3D). Next, by depositing polysilicon by the CVD method, the gate electrode 105b of the other group is deposited.
Are formed (step of FIG. 3E). Here, polysilicon is not deposited on SiN but is deposited between the gate electrodes 105a without the nitride film 106. The gate electrodes 105a and the gate electrodes 105b are alternately arranged with the same width via the thin oxide film 108, and the gate electrodes are formed with high density.

After that, the MIOS transistor of FIG. 1 is formed by the usual diffusion process and wiring process. Gate electrode 10
When forming an oxide film on 5a and 105b, the nitride film 106
May or may not be removed since it is not related to electrical operation.

The present invention is not limited to the above-mentioned embodiment, but various modifications can be made.

For example, the MIOS transistor of the semiconductor memory device has the MONOS structure.
A structure, a MAOS structure, or the like may be used, and the operations are almost the same. At this time, the insulating film (tunnel oxide film, alumina film in the case of the MAOS structure) suitable for these structures may be formed in advance on the substrate in the step of forming the gate of the MIOS transistor.

[0021]

As described above, according to the semiconductor memory device of the present invention, since the source and drain of the MIO transistor are regions of the same conductivity type, a plurality of gate electrodes can be closely arranged at high density. A semiconductor memory device having excellent flatness on those electrodes and a very high memory density can be obtained.

Further, according to the method of manufacturing a semiconductor memory device of the present invention, since the gate electrode is further formed between the gate electrodes, the density of the gate electrode can be increased, and therefore the semiconductor memory device of the present invention. Can be made.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a MIO transistor which constitutes a semiconductor memory device of the present invention.

FIG. 2 is an application circuit diagram of the MIOs transistor of FIG.

FIG. 3 is a process drawing of forming a gate of the MIO transistor shown in FIG.

FIG. 4 is a structural diagram of a NAND type memory cell having a MIO structure.

FIG. 5 is a structural diagram of a floating gate type memory cell.

[Explanation of symbols]

101 ... Substrate, 102 ... Tunnel oxide film, 103 ... Nitride film, 104 ... Oxide film, 105 ... Polysilicon film, 105
a, 105b ... Gate electrode, 106 ... Nitride film, 108 ...
Thin oxide film, CG1 to CG4 ... Gate electrode, D ... Source, S ... Drain, Q1 ... MIOS transistor

Claims (3)

[Claims] 1. A semiconductor memory device comprising an MIO transistor, wherein the MIO transistor has a region of the same conductivity type between its source and drain, and the MIO is formed on this region.
A semiconductor memory device having a structure in which a plurality of gate electrodes formed of an S structure are linearly arranged close to each other in the source / drain direction. 2. A method of manufacturing a semiconductor memory device comprising a MIO transistor, comprising: a polysilicon film on a substrate on which an oxide film and a first nitride film are sequentially formed; and a second nitride film on the polysilicon film. A first step of forming a film, and the polysilicon film and the second nitride film are alternately removed at a predetermined pitch to form a plurality of gate electrodes of one group forming the MIO transistor. A second step; a third step of oxidizing a side surface of the gate electrode of the one group to form an insulating film; and a step of depositing polysilicon between the gate electrodes of the one group to form an insulating film. A fourth step of forming a gate electrode, the gate of the MIO transistor is formed, and the method for manufacturing a semiconductor memory device. 3. In the first step, a polysilicon film and a second nitride film are formed on the polysilicon film on a substrate on which an oxide film, a first nitride film, and an oxide film are sequentially formed. The method of manufacturing a semiconductor memory device according to claim 2, wherein