JPH05128044A - Input/output processing system - Google Patents

Abstract

PURPOSE:To reduce the overrun of data by comparing the condition of a data buffer in each channel device with a threshold appropriately set up in accordance with the type of an interface and changing the priority order of memory requests. CONSTITUTION:A control circuit 21 sets up a proper threshold in a threshold register 35 in accordance with the using condition of a data buffer 31 in each channel device 30 and the interface type of a corresponding peripheral device 40. In the case of transferring data from a main storage device 10 to the peripheral device 40 for instance, comparator 36 sends a high priority signal to a priority order determining circuit 23 in a channel control device 23 when the value of a difference generating circuit 34 becomes less than the threshold. The value of the circuit 34 indicates the volume of data in the buffer 31. When plural memory requests compete, the circuit 23 commands a request selection replay distributing circuit 22 to receive the memory request of the channel device 30 sending the signal with priority. Consequently the overrun of data can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output processing system having a plurality of channel devices including data buffers and performing priority control of memory access competition between the channel devices during data transfer.

[0002]

2. Description of the Related Art Conventionally, this type of input / output processing system has been
There are restrictions on the interface performance between the channel control device and the main memory device, and memory requests from all channel devices cannot be sent to the main memory device at the same time. Therefore, when a plurality of memory requests compete with each other, the channel control device selects the memory requests according to the priority order and sequentially sends them to the main storage device.
The determination of the priority order in the case of a memory access conflict from the channel device of this conventional input / output processing system is fixed, and there is, for example, a younger priority assignment of the channel device connection port of the channel control device.

[0003]

The above-mentioned conventional input / output processing system employs a fixed priority assignment, and a specific channel device is always prioritized regardless of the transfer status of each channel device. However, there is a problem that the channel device assigned to low priority has a high possibility of causing data overrun.

An object of the present invention is to realize a mechanism for maximizing the overall performance by reflecting the overrun tolerance state of each channel device in the priority assignment with the minimum amount of hardware.

[0005]

An input / output processing system of the present invention has a main storage device, a channel control device, and a data buffer, and sends a memory request to the main storage device via the channel control device. An input / output processing system having a plurality of channel devices for performing data transfer with a peripheral device, the register holding a predetermined threshold in the channel device, and the amount of data in the buffer. In the case of comparing means for comparing the threshold value in the register and data transfer in the direction from the main memory device to the peripheral device, if the amount of data in the data buffer is less than or equal to the threshold value in the register, a high priority signal. Is sent from the channel device to the channel control device, and in the case of data transfer in the direction from the peripheral device to the main memory device, the data buffer is sent. If the amount of data in the register is greater than or equal to the value in the register, a high priority signal transmitting means for transmitting a high priority signal from the channel device to the channel control device and a plurality of memory requests for the channel control device compete with each other. In this case, the memory request from the channel device transmitting the high priority signal is prioritized over the memory request from the channel device not transmitting the high priority signal. .. Further, the input / output processing system according to claim 1 is provided with threshold setting means for setting a different threshold in the register for each of the channel devices depending on an interface type of the channel device with the peripheral device. preferable.

[0006]

When the requested data is transferred from the main memory device to the peripheral device, the channel control device receives the data from the main memory device and sends it to the requesting peripheral device via the corresponding channel device. At this time, when the amount of data in the data buffer becomes equal to or less than the threshold value of the register, the high priority signal transmitting means transmits the high priority signal to the channel control device,
Data is preferentially sent from the main memory device to the corresponding channel device. When transferring data from the peripheral device to the main storage device, the channel control device receives the data from the corresponding channel device and stores it in the main storage device. At this time, when the amount of data in the data buffer becomes equal to or larger than the threshold value of the register, the high-priority signal sending means sends a high-priority signal to the channel control device, and the channel device corresponding to the main memory device preferentially sends the data. Store.

[0007]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the input / output processing system of the present invention. In this embodiment, the main storage device 10, the channel control device 20 connected to the main storage device 10 via the interface 50, the channel control device 20 and the interfaces 60 ₁ , 60 ₂ , ..., 6 respectively.
0 _n and the signal lines 70 _1, 70 _2, -, 70 via the _n connection channels device 30 _1, 30 _2, -, 30 _n
When the channel device 30 _1, 30 _2, -, 30 _n respectively interfaces 80 _1, 80 _2, -, 80 _n connected peripheral device via the 40 _1, 40 _2, ~, it is composed of a 40 _n There is.

The channel control device 20 comprises a control circuit 21, a request selection reply distribution circuit 22, and a priority order determination circuit 23. Channel device 30
₁ , 30 ₂ , ..., 30 _n are data buffers 3 respectively
1, a write pointer 32 indicating a write address of the data buffer 31, a read pointer 33 indicating a read address, a difference generator 34 generating a difference between the values of the write pointer 32 and the read pointer 33, a self-channel device and a peripheral device. Data buffer 31 in combination
The threshold register 35 holds a value indicating the overrun tolerance of the above, a difference generator 34, and a comparator 36 for comparing the values of the threshold register 35.

Next, the operation of this embodiment will be described. First, the initial setting operation will be described. Channel controller 20
Sets the threshold registers 35 of the channel devices 30 ₁ , 30 ₂ , ..., 30 _n . Specifically, there is a configuration table in the main storage device, and in this configuration table, the peripheral devices 40 ₁ , 40 ₂ , ..., respectively connected to the respective channel devices 30 ₁ , 30 ₂ , ..., 30 _n . 40 _n types are described, which determine the data transfer rate between the channel device and the peripheral device.
This data transfer rate determines the amount of data to be held during data transfer in the data buffer 31 of each channel device. That is, even if there is a suspension of data transfer that may occur temporarily due to fluctuations due to competition in data transfer between the main memory device 10 and the channel device, it is a value that can be tolerated by the data capacity or free capacity in the data buffer.
A request for reading the configuration table in the main storage device 10 is sent from the control circuit 21 of the channel control device 20 through the request selection reply distribution circuit 22, and the control circuit 21 receives the control table information through the same route. Based on each channel device 30 ₁ , 30
₂ to 30 _n are set, and the set values are sent from the control circuit 21 through the request selection reply distribution circuit 22 and the interfaces 60 ₁ , 60 ₂ , ..., 60 _n to the channel devices 30 ₁ , 30 ₂ . ~, 30 _n threshold registers 35 are set.

Next, the case where data is transferred from the main memory device to the peripheral device will be described. A memory read request is sent from the channel device (specifically, the channel device 30 ₁ here) to the request selection reply distribution circuit 22 through the interface 60 ₁ .
When the request is selected by the request selection reply distribution circuit 22, it is sent to the main storage device 10 through the interface 50. When the main memory device 10 receives the memory read request, it returns the memory content at the address indicated by the request as a reply to the request selection reply distribution circuit 22 through the interface 50. Upon receipt of the reply, the request selection reply distribution circuit 22 determines the return destination of the reply and returns it to the request source channel device 30 ₁ through the interface 60 ₁ . The channel device 30 ₁ receiving the reply sends the reply data to the data buffer 3 indicated by the write pointer 32.
Write to the entry of 1 and increment the write pointer 32. The above request operation from the channel device 30 ₁ to the main memory device 10 is continued as long as the data transfer is not completed and there is a free entry in the data buffer 31. On the other hand, data transfer between the channel device 30 ₁ and the peripheral device 40 ₁ is performed at a constant transfer rate, and the read pointer 33 is incremented each time the entry indicated by the read pointer 33 of the data buffer 31 is read. In this case, the difference generator 34 creates the number of data existing entries in the data buffer 31 based on the value of the write pointer 32 and the value of the read pointer 33, and sends it to the comparator 36.

Further, the case where data transfer is performed from the peripheral device to the main memory will be described. Peripherals (here specifically with peripheral devices 40 ₁₎ data transfer via the interface 80 ₁ to the channel device 30 ₁ from the is carried out, the write pointer data is written received the entry of the data buffer 31 indicated by the write pointer 32 32 is incremented. When the data exists in the data buffer 31, a memory write request is sent from the channel device 30 ₁ to the channel control device 20 through the interface 60 ₁ together with the data.
At this time, the read pointer 33 is incremented.
This request is a request selection reply distribution circuit 22.
Selected and sent to the main storage device 10 through the interface 50. When the main memory device 10 receives the memory write request, it writes data to the address indicated by this request and returns a reply to the channel control device 20. Upon receiving the reply, the request selection reply distribution circuit 22 determines the return destination of the reply, and through the interface 60 ₁ , the request source channel device 3
Return to 0 ₁ . In this case, the difference generator 34 creates the number of empty entries in the data buffer 31 based on the value of the write pointer 32 and the value of the read pointer 33, and the comparator 3
Send to 6.

In the data transfer in any of the above directions, when the value of the output of the difference generator 34 is smaller than the value of the threshold register 35, the comparator 36 to the signal line 70.
High priority signal is sent through ₁ . In this case, it is shown that a data overrun may be caused between the channel device 30 ₁ and the peripheral device 40 ₁ if the memory device cannot accept the memory request. The priority order determination circuit 23 instructs the request selection reply distribution circuit 22 to directly send the request received from the channel device 30 ₁ to the main memory control device 10 as long as there is no conflict with the requests of other channel devices. When memory requests are received from a plurality of channel devices at the same time, the priority order determination circuit 23 accepts a predetermined priority order, in this case, for example, the channel ports of the channel control device in the ascending order of priority, and receives the requests. After sending the request to 10, the request selection reply distribution circuit 22 is instructed to accept the waiting request and send it to the main storage device 10. In the case where a plurality of requests compete at the same time, but when the high priority signal is sent from the old channel device through the signal line,
The priority order determining circuit 23 requests the priority selection of the old channel to receive the request selection reply distribution circuit 22.
Instruct.

In the above description, the channel device 30 ₁
The peripheral device 40 ₁ has been mainly described, but the same applies to other channel devices and peripheral devices.

[0014]

As described above, the present invention compares the status of the data buffer in each channel device with a threshold value set appropriately according to the interface type, so that data shortage at the time of data transmission to the peripheral device, Data overrun is reduced with a small amount of hardware by generating a high-priority signal according to the lack of storage area in the data buffer when fetching data from the device and reflecting that signal in the memory request acceptance order of the channel controller. The effect is that the total transfer capacity can be efficiently obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an input / output processing system of the present invention.

[Explanation of symbols]

10 main memory device 20 channel control device 30 ₁ , 30 ₂ , ~, 30 _n channel device 40 ₁ , 40 ₂ , ~, 40 _n peripheral device 21 control circuit 22 request selection reply distribution circuit 23 priority determination circuit 31 data buffer 32 Write pointer 33 Read pointer 34 Difference generation circuit 35 Threshold register 36 Comparator 50, 60 ₁ , 60 ₂ , ~, 60 _n , 80 ₁ , 80 ₂ , ~, 80 _n interface 70 ₁ , 70 ₂ , 70, 70, _n signal line

Claims (2)

[Claims] 1. A main storage device, a channel control device, and a data buffer, wherein a memory request is made to the main storage device through the channel control device, and data is transferred to and from a peripheral device. In an input / output processing system having a plurality of channel devices, a register that holds a predetermined threshold value in the channel device, a comparison unit that compares a data amount in the buffer with a threshold value in the register, In the case of data transfer from the storage device to the peripheral device, if the amount of data in the data buffer is less than or equal to the threshold value in the register, a high priority signal is sent from the channel device to the channel control device, In the case of data transfer from the device to the main memory, if the amount of data in the data buffer is greater than or equal to the value in the register For example, when a plurality of memory requests compete with the channel control device and a high priority signal transmission means for transmitting a high priority signal from the channel device to the channel control device, the high priority signal is transmitted. An input / output processing system comprising: priority determination means for prioritizing the memory request from the channel device over the memory request from the channel device that is not sending the high priority signal. 2. The input / output processing system according to claim 1, further comprising threshold setting means for setting a different threshold in said register for each of said channel devices depending on an interface type of said channel device with said peripheral device. An input / output processing system characterized in that